2 * Copyright (c) 2013-2015 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * This is a simulation model for a UFS interface
40 * The UFS interface consists of a host controller and (at least) one device.
41 * The device can contain multiple logic units.
42 * To make this interface as usefull as possible for future development, the
43 * decision has been made to split the UFS functionality from the SCSI
44 * functionality. The class UFS SCSIDevice can therefor be used as a starting
45 * point for creating a more generic SCSI device. This has as a consequence
46 * that the UFSHostDevice class contains functionality from both the host
47 * controller and the device. The current UFS standard (1.1) allows only one
48 * device, and up to 8 logic units. the logic units only handle the SCSI part
49 * of the command, and the device mainly the UFS part. Yet the split between
50 * the SCSIresume function and the SCSICMDHandle might seem a bit awkward.
51 * The SCSICMDHandle function is in essence a SCSI reply generator, and it
52 * distils the essential information from the command. A disktransfer cannot
53 * be made from this position because the scatter gather list is not included
54 * in the SCSI command, but in the Transfer Request descriptor. The device
55 * needs to manage the data transfer. This file is build up as follows: first
56 * the UFSSCSIDevice functions will be presented; then the UFSHostDevice
57 * functions. The UFSHostDevice functions are split in three parts: UFS
58 * transaction flow, data write transfer and data read transfer. The
59 * functions are then ordered in the order in which a transfer takes place.
63 * Reference material can be found at the JEDEC website:
65 * http://www.jedec.org/standards-documents/results/jesd220
66 * UFS HCI specification
67 * http://www.jedec.org/standards-documents/results/jesd223
70 #include "dev/arm/ufs_device.hh"
73 * Constructor and destructor functions of UFSHCM device
75 UFSHostDevice::UFSSCSIDevice::UFSSCSIDevice(const UFSHostDeviceParams
&p
,
76 uint32_t lun_id
, const Callback
&transfer_cb
,
77 const Callback
&read_cb
):
79 flashDisk(p
.image
[lun_id
]),
80 flashDevice(p
.internalflash
[lun_id
]),
81 blkSize(p
.img_blk_size
),
82 lunAvail(p
.image
.size()),
83 diskSize(flashDisk
->size()),
84 capacityLower((diskSize
- 1) & 0xffffffff),
85 capacityUpper((diskSize
- SectorSize
) >> 32),
87 transferCompleted(false),
91 amountOfWriteTransfers(0),
92 amountOfReadTransfers(0)
95 * These callbacks are used to communicate the events that are
96 * triggered upstream; e.g. from the Memory Device to the UFS SCSI Device
97 * or from the UFS SCSI device to the UFS host.
99 signalDone
= transfer_cb
;
100 memReadCallback
= [this]() { readCallback(); };
101 deviceReadCallback
= read_cb
;
102 memWriteCallback
= [this]() { SSDWriteDone(); };
105 * make ascii out of lun_id (and add more characters)
106 * UFS allows up to 8 logic units, so the numbering should work out
108 uint32_t temp_id
= ((lun_id
| 0x30) << 24) | 0x3A4449;
109 lunInfo
.dWord0
= 0x02060000; //data
110 lunInfo
.dWord1
= 0x0200001F;
111 lunInfo
.vendor0
= 0x484D5241; //ARMH (HMRA)
112 lunInfo
.vendor1
= 0x424D4143; //CAMB (BMAC)
113 lunInfo
.product0
= 0x356D6567; //gem5 (5meg)
114 lunInfo
.product1
= 0x4D534655; //UFSM (MSFU)
115 lunInfo
.product2
= 0x4C45444F; //ODEL (LEDO)
116 lunInfo
.product3
= temp_id
; // ID:"lun_id" ("lun_id":DI)
117 lunInfo
.productRevision
= 0x01000000; //0x01
119 DPRINTF(UFSHostDevice
, "Logic unit %d assumes that %d logic units are"
120 " present in the system\n", lunID
, lunAvail
);
121 DPRINTF(UFSHostDevice
,"The disksize of lun: %d should be %d blocks\n",
123 flashDevice
->initializeMemory(diskSize
, SectorSize
);
128 * These pages are SCSI specific. For more information refer to:
129 * Universal Flash Storage (UFS) JESD220 FEB 2011 (JEDEC)
130 * http://www.jedec.org/standards-documents/results/jesd220
132 const unsigned int UFSHostDevice::UFSSCSIDevice::controlPage
[3] =
133 {0x01400A0A, 0x00000000,
135 const unsigned int UFSHostDevice::UFSSCSIDevice::recoveryPage
[3] =
136 {0x03800A01, 0x00000000,
138 const unsigned int UFSHostDevice::UFSSCSIDevice::cachingPage
[5] =
139 {0x00011208, 0x00000000,
140 0x00000000, 0x00000020,
143 UFSHostDevice::UFSSCSIDevice::~UFSSCSIDevice() {}
146 * UFS specific SCSI handling function.
147 * The following attributes may still be added: SCSI format unit,
148 * Send diagnostic and UNMAP;
149 * Synchronize Cache and buffer read/write could not be tested yet
150 * All parameters can be found in:
151 * Universal Flash Storage (UFS) JESD220 FEB 2011 (JEDEC)
152 * http://www.jedec.org/standards-documents/results/jesd220
153 * (a JEDEC acount may be required {free of charge})
156 struct UFSHostDevice::SCSIReply
157 UFSHostDevice::UFSSCSIDevice::SCSICMDHandle(uint32_t* SCSI_msg
)
159 struct SCSIReply scsi_out
;
163 * Create the standard SCSI reponse information
164 * These values might changes over the course of a transfer
166 scsi_out
.message
.header
.dWord0
= UPIUHeaderDataIndWord0
|
168 scsi_out
.message
.header
.dWord1
= UPIUHeaderDataIndWord1
;
169 scsi_out
.message
.header
.dWord2
= UPIUHeaderDataIndWord2
;
170 statusCheck(SCSIGood
, scsi_out
.senseCode
);
171 scsi_out
.senseSize
= scsi_out
.senseCode
[0];
172 scsi_out
.LUN
= lunID
;
173 scsi_out
.status
= SCSIGood
;
175 DPRINTF(UFSHostDevice
, "SCSI command:%2x\n", SCSI_msg
[4]);
176 /**Determine what the message is and fill the response packet*/
178 switch (SCSI_msg
[4] & 0xFF) {
182 * SCSI inquiry: tell about this specific logic unit
184 scsi_out
.msgSize
= 36;
185 scsi_out
.message
.dataMsg
.resize(9);
187 for (uint8_t count
= 0; count
< 9; count
++)
188 scsi_out
.message
.dataMsg
[count
] =
189 (reinterpret_cast<uint32_t*> (&lunInfo
))[count
];
194 * Read command. Number indicates the length of the command.
196 scsi_out
.expectMore
= 0x02;
197 scsi_out
.msgSize
= 0;
199 uint8_t* tempptr
= reinterpret_cast<uint8_t*>(&SCSI_msg
[4]);
201 /**BE and not nicely aligned. Apart from that it only has
202 * information in five bits of the first byte that is relevant
205 uint32_t tmp
= *reinterpret_cast<uint32_t*>(tempptr
);
206 uint64_t read_offset
= betoh(tmp
) & 0x1FFFFF;
208 uint32_t read_size
= tempptr
[4];
211 scsi_out
.msgSize
= read_size
* blkSize
;
212 scsi_out
.offset
= read_offset
* blkSize
;
214 if ((read_offset
+ read_size
) > diskSize
)
215 scsi_out
.status
= SCSIIllegalRequest
;
217 DPRINTF(UFSHostDevice
, "Read6 offset: 0x%8x, for %d blocks\n",
218 read_offset
, read_size
);
221 * Renew status check, for the request may have been illegal
223 statusCheck(scsi_out
.status
, scsi_out
.senseCode
);
224 scsi_out
.senseSize
= scsi_out
.senseCode
[0];
225 scsi_out
.status
= (scsi_out
.status
== SCSIGood
) ? SCSIGood
:
231 scsi_out
.expectMore
= 0x02;
232 scsi_out
.msgSize
= 0;
234 uint8_t* tempptr
= reinterpret_cast<uint8_t*>(&SCSI_msg
[4]);
236 /**BE and not nicely aligned.*/
237 uint32_t tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[2]);
238 uint64_t read_offset
= betoh(tmp
);
240 uint16_t tmpsize
= *reinterpret_cast<uint16_t*>(&tempptr
[7]);
241 uint32_t read_size
= betoh(tmpsize
);
243 scsi_out
.msgSize
= read_size
* blkSize
;
244 scsi_out
.offset
= read_offset
* blkSize
;
246 if ((read_offset
+ read_size
) > diskSize
)
247 scsi_out
.status
= SCSIIllegalRequest
;
249 DPRINTF(UFSHostDevice
, "Read10 offset: 0x%8x, for %d blocks\n",
250 read_offset
, read_size
);
253 * Renew status check, for the request may have been illegal
255 statusCheck(scsi_out
.status
, scsi_out
.senseCode
);
256 scsi_out
.senseSize
= scsi_out
.senseCode
[0];
257 scsi_out
.status
= (scsi_out
.status
== SCSIGood
) ? SCSIGood
:
263 scsi_out
.expectMore
= 0x02;
264 scsi_out
.msgSize
= 0;
266 uint8_t* tempptr
= reinterpret_cast<uint8_t*>(&SCSI_msg
[4]);
268 /**BE and not nicely aligned.*/
269 uint32_t tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[2]);
270 uint64_t read_offset
= betoh(tmp
);
272 tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[6]);
273 read_offset
= (read_offset
<< 32) | betoh(tmp
);
275 tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[10]);
276 uint32_t read_size
= betoh(tmp
);
278 scsi_out
.msgSize
= read_size
* blkSize
;
279 scsi_out
.offset
= read_offset
* blkSize
;
281 if ((read_offset
+ read_size
) > diskSize
)
282 scsi_out
.status
= SCSIIllegalRequest
;
284 DPRINTF(UFSHostDevice
, "Read16 offset: 0x%8x, for %d blocks\n",
285 read_offset
, read_size
);
288 * Renew status check, for the request may have been illegal
290 statusCheck(scsi_out
.status
, scsi_out
.senseCode
);
291 scsi_out
.senseSize
= scsi_out
.senseCode
[0];
292 scsi_out
.status
= (scsi_out
.status
== SCSIGood
) ? SCSIGood
:
297 case SCSIReadCapacity10
: {
299 * read the capacity of the device
301 scsi_out
.msgSize
= 8;
302 scsi_out
.message
.dataMsg
.resize(2);
303 scsi_out
.message
.dataMsg
[0] =
304 betoh(capacityLower
);//last block
305 scsi_out
.message
.dataMsg
[1] = betoh(blkSize
);//blocksize
308 case SCSIReadCapacity16
: {
309 scsi_out
.msgSize
= 32;
310 scsi_out
.message
.dataMsg
.resize(8);
311 scsi_out
.message
.dataMsg
[0] =
312 betoh(capacityUpper
);//last block
313 scsi_out
.message
.dataMsg
[1] =
314 betoh(capacityLower
);//last block
315 scsi_out
.message
.dataMsg
[2] = betoh(blkSize
);//blocksize
316 scsi_out
.message
.dataMsg
[3] = 0x00;//
317 scsi_out
.message
.dataMsg
[4] = 0x00;//reserved
318 scsi_out
.message
.dataMsg
[5] = 0x00;//reserved
319 scsi_out
.message
.dataMsg
[6] = 0x00;//reserved
320 scsi_out
.message
.dataMsg
[7] = 0x00;//reserved
324 case SCSIReportLUNs
: {
326 * Find out how many Logic Units this device has.
328 scsi_out
.msgSize
= (lunAvail
* 8) + 8;//list + overhead
329 scsi_out
.message
.dataMsg
.resize(2 * lunAvail
+ 2);
330 scsi_out
.message
.dataMsg
[0] = (lunAvail
* 8) << 24;//LUN listlength
331 scsi_out
.message
.dataMsg
[1] = 0x00;
333 for (uint8_t count
= 0; count
< lunAvail
; count
++) {
335 scsi_out
.message
.dataMsg
[2 + 2 * count
] = (count
& 0x7F) << 8;
336 scsi_out
.message
.dataMsg
[3 + 2 * count
] = 0x00;
341 case SCSIStartStop
: {
342 //Just acknowledge; not deemed relevant ATM
343 scsi_out
.msgSize
= 0;
347 case SCSITestUnitReady
: {
348 //Just acknowledge; not deemed relevant ATM
349 scsi_out
.msgSize
= 0;
355 * See if the blocks that the host plans to request are in range of
358 scsi_out
.msgSize
= 0;
360 uint8_t* tempptr
= reinterpret_cast<uint8_t*>(&SCSI_msg
[4]);
362 /**BE and not nicely aligned.*/
363 uint32_t tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[2]);
364 uint64_t read_offset
= betoh(tmp
);
366 uint16_t tmpsize
= *reinterpret_cast<uint16_t*>(&tempptr
[7]);
367 uint32_t read_size
= betoh(tmpsize
);
369 if ((read_offset
+ read_size
) > diskSize
)
370 scsi_out
.status
= SCSIIllegalRequest
;
373 * Renew status check, for the request may have been illegal
375 statusCheck(scsi_out
.status
, scsi_out
.senseCode
);
376 scsi_out
.senseSize
= scsi_out
.senseCode
[0];
377 scsi_out
.status
= (scsi_out
.status
== SCSIGood
) ? SCSIGood
:
387 uint8_t* tempptr
= reinterpret_cast<uint8_t*>(&SCSI_msg
[4]);
389 /**BE and not nicely aligned. Apart from that it only has
390 * information in five bits of the first byte that is relevant
393 uint32_t tmp
= *reinterpret_cast<uint32_t*>(tempptr
);
394 uint64_t write_offset
= betoh(tmp
) & 0x1FFFFF;
396 uint32_t write_size
= tempptr
[4];
398 scsi_out
.msgSize
= write_size
* blkSize
;
399 scsi_out
.offset
= write_offset
* blkSize
;
400 scsi_out
.expectMore
= 0x01;
402 if ((write_offset
+ write_size
) > diskSize
)
403 scsi_out
.status
= SCSIIllegalRequest
;
405 DPRINTF(UFSHostDevice
, "Write6 offset: 0x%8x, for %d blocks\n",
406 write_offset
, write_size
);
409 * Renew status check, for the request may have been illegal
411 statusCheck(scsi_out
.status
, scsi_out
.senseCode
);
412 scsi_out
.senseSize
= scsi_out
.senseCode
[0];
413 scsi_out
.status
= (scsi_out
.status
== SCSIGood
) ? SCSIGood
:
419 uint8_t* tempptr
= reinterpret_cast<uint8_t*>(&SCSI_msg
[4]);
421 /**BE and not nicely aligned.*/
422 uint32_t tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[2]);
423 uint64_t write_offset
= betoh(tmp
);
425 uint16_t tmpsize
= *reinterpret_cast<uint16_t*>(&tempptr
[7]);
426 uint32_t write_size
= betoh(tmpsize
);
428 scsi_out
.msgSize
= write_size
* blkSize
;
429 scsi_out
.offset
= write_offset
* blkSize
;
430 scsi_out
.expectMore
= 0x01;
432 if ((write_offset
+ write_size
) > diskSize
)
433 scsi_out
.status
= SCSIIllegalRequest
;
435 DPRINTF(UFSHostDevice
, "Write10 offset: 0x%8x, for %d blocks\n",
436 write_offset
, write_size
);
439 * Renew status check, for the request may have been illegal
441 statusCheck(scsi_out
.status
, scsi_out
.senseCode
);
442 scsi_out
.senseSize
= scsi_out
.senseCode
[0];
443 scsi_out
.status
= (scsi_out
.status
== SCSIGood
) ? SCSIGood
:
449 uint8_t* tempptr
= reinterpret_cast<uint8_t*>(&SCSI_msg
[4]);
451 /**BE and not nicely aligned.*/
452 uint32_t tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[2]);
453 uint64_t write_offset
= betoh(tmp
);
455 tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[6]);
456 write_offset
= (write_offset
<< 32) | betoh(tmp
);
458 tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[10]);
459 uint32_t write_size
= betoh(tmp
);
461 scsi_out
.msgSize
= write_size
* blkSize
;
462 scsi_out
.offset
= write_offset
* blkSize
;
463 scsi_out
.expectMore
= 0x01;
465 if ((write_offset
+ write_size
) > diskSize
)
466 scsi_out
.status
= SCSIIllegalRequest
;
468 DPRINTF(UFSHostDevice
, "Write16 offset: 0x%8x, for %d blocks\n",
469 write_offset
, write_size
);
472 * Renew status check, for the request may have been illegal
474 statusCheck(scsi_out
.status
, scsi_out
.senseCode
);
475 scsi_out
.senseSize
= scsi_out
.senseCode
[0];
476 scsi_out
.status
= (scsi_out
.status
== SCSIGood
) ? SCSIGood
:
481 case SCSIFormatUnit
: {//not yet verified
482 scsi_out
.msgSize
= 0;
483 scsi_out
.expectMore
= 0x01;
487 case SCSISendDiagnostic
: {//not yet verified
488 scsi_out
.msgSize
= 0;
492 case SCSISynchronizeCache
: {
493 //do we have cache (we don't have cache at this moment)
494 //TODO: here will synchronization happen when cache is modelled
495 scsi_out
.msgSize
= 0;
499 //UFS SCSI additional command set for full functionality
500 case SCSIModeSelect10
:
502 //scsi_out.expectMore = 0x01;//not supported due to modepage support
503 //code isn't dead, code suggest what is to be done when implemented
506 case SCSIModeSense6
: case SCSIModeSense10
: {
508 * Get more discriptive information about the SCSI functionality
509 * within this logic unit.
511 if ((SCSI_msg
[4] & 0x3F0000) >> 16 == 0x0A) {//control page
512 scsi_out
.message
.dataMsg
.resize((sizeof(controlPage
) >> 2) + 2);
513 scsi_out
.message
.dataMsg
[0] = 0x00000A00;//control page code
514 scsi_out
.message
.dataMsg
[1] = 0x00000000;//See JEDEC220 ch8
516 for (uint8_t count
= 0; count
< 3; count
++)
517 scsi_out
.message
.dataMsg
[2 + count
] = controlPage
[count
];
519 scsi_out
.msgSize
= 20;
520 DPRINTF(UFSHostDevice
, "CONTROL page\n");
522 } else if ((SCSI_msg
[4] & 0x3F0000) >> 16 == 0x01) {//recovery page
523 scsi_out
.message
.dataMsg
.resize((sizeof(recoveryPage
) >> 2)
526 scsi_out
.message
.dataMsg
[0] = 0x00000100;//recovery page code
527 scsi_out
.message
.dataMsg
[1] = 0x00000000;//See JEDEC220 ch8
529 for (uint8_t count
= 0; count
< 3; count
++)
530 scsi_out
.message
.dataMsg
[2 + count
] = recoveryPage
[count
];
532 scsi_out
.msgSize
= 20;
533 DPRINTF(UFSHostDevice
, "RECOVERY page\n");
535 } else if ((SCSI_msg
[4] & 0x3F0000) >> 16 == 0x08) {//caching page
537 scsi_out
.message
.dataMsg
.resize((sizeof(cachingPage
) >> 2) + 2);
538 scsi_out
.message
.dataMsg
[0] = 0x00001200;//caching page code
539 scsi_out
.message
.dataMsg
[1] = 0x00000000;//See JEDEC220 ch8
541 for (uint8_t count
= 0; count
< 5; count
++)
542 scsi_out
.message
.dataMsg
[2 + count
] = cachingPage
[count
];
544 scsi_out
.msgSize
= 20;
545 DPRINTF(UFSHostDevice
, "CACHE page\n");
547 } else if ((SCSI_msg
[4] & 0x3F0000) >> 16 == 0x3F) {//ALL the pages!
549 scsi_out
.message
.dataMsg
.resize(((sizeof(controlPage
) +
550 sizeof(recoveryPage
) +
551 sizeof(cachingPage
)) >> 2)
553 scsi_out
.message
.dataMsg
[0] = 0x00003200;//all page code
554 scsi_out
.message
.dataMsg
[1] = 0x00000000;//See JEDEC220 ch8
556 for (uint8_t count
= 0; count
< 3; count
++)
557 scsi_out
.message
.dataMsg
[2 + count
] = recoveryPage
[count
];
559 for (uint8_t count
= 0; count
< 5; count
++)
560 scsi_out
.message
.dataMsg
[5 + count
] = cachingPage
[count
];
562 for (uint8_t count
= 0; count
< 3; count
++)
563 scsi_out
.message
.dataMsg
[10 + count
] = controlPage
[count
];
565 scsi_out
.msgSize
= 52;
566 DPRINTF(UFSHostDevice
, "Return ALL the pages!!!\n");
568 } else inform("Wrong mode page requested\n");
570 scsi_out
.message
.dataCount
= scsi_out
.msgSize
<< 24;
573 case SCSIRequestSense
: {
574 scsi_out
.msgSize
= 0;
578 case SCSIUnmap
:break;//not yet verified
580 case SCSIWriteBuffer
: {
581 scsi_out
.expectMore
= 0x01;
583 uint8_t* tempptr
= reinterpret_cast<uint8_t*>(&SCSI_msg
[4]);
585 /**BE and not nicely aligned.*/
586 uint32_t tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[2]);
587 uint64_t write_offset
= betoh(tmp
) & 0xFFFFFF;
589 tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[5]);
590 uint32_t write_size
= betoh(tmp
) & 0xFFFFFF;
592 scsi_out
.msgSize
= write_size
;
593 scsi_out
.offset
= write_offset
;
597 case SCSIReadBuffer
: {
599 * less trivial than normal read. Size is in bytes instead
600 * of blocks, and it is assumed (though not guaranteed) that
601 * reading is from cache.
603 scsi_out
.expectMore
= 0x02;
605 uint8_t* tempptr
= reinterpret_cast<uint8_t*>(&SCSI_msg
[4]);
607 /**BE and not nicely aligned.*/
608 uint32_t tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[2]);
609 uint64_t read_offset
= betoh(tmp
) & 0xFFFFFF;
611 tmp
= *reinterpret_cast<uint32_t*>(&tempptr
[5]);
612 uint32_t read_size
= betoh(tmp
) & 0xFFFFFF;
614 scsi_out
.msgSize
= read_size
;
615 scsi_out
.offset
= read_offset
;
617 if ((read_offset
+ read_size
) > capacityLower
* blkSize
)
618 scsi_out
.status
= SCSIIllegalRequest
;
620 DPRINTF(UFSHostDevice
, "Read buffer location: 0x%8x\n",
622 DPRINTF(UFSHostDevice
, "Number of bytes: 0x%8x\n", read_size
);
624 statusCheck(scsi_out
.status
, scsi_out
.senseCode
);
625 scsi_out
.senseSize
= scsi_out
.senseCode
[0];
626 scsi_out
.status
= (scsi_out
.status
== SCSIGood
) ? SCSIGood
:
631 case SCSIMaintenanceIn
: {
633 * linux sends this command three times from kernel 3.9 onwards,
634 * UFS does not support it, nor does this model. Linux knows this,
635 * but tries anyway (useful for some SD card types).
636 * Lets make clear we don't want it and just ignore it.
638 DPRINTF(UFSHostDevice
, "Ignoring Maintenance In command\n");
639 statusCheck(SCSIIllegalRequest
, scsi_out
.senseCode
);
640 scsi_out
.senseSize
= scsi_out
.senseCode
[0];
641 scsi_out
.status
= (scsi_out
.status
== SCSIGood
) ? SCSIGood
:
643 scsi_out
.msgSize
= 0;
647 statusCheck(SCSIIllegalRequest
, scsi_out
.senseCode
);
648 scsi_out
.senseSize
= scsi_out
.senseCode
[0];
649 scsi_out
.status
= (scsi_out
.status
== SCSIGood
) ? SCSIGood
:
651 scsi_out
.msgSize
= 0;
652 inform("Unsupported scsi message type: %2x\n", SCSI_msg
[4] & 0xFF);
653 inform("0x%8x\n", SCSI_msg
[0]);
654 inform("0x%8x\n", SCSI_msg
[1]);
655 inform("0x%8x\n", SCSI_msg
[2]);
656 inform("0x%8x\n", SCSI_msg
[3]);
657 inform("0x%8x\n", SCSI_msg
[4]);
665 * SCSI status check function. generic device test, creates sense codes
666 * Future versions may include TODO: device checks, which is why this is
667 * in a separate function.
671 UFSHostDevice::UFSSCSIDevice::statusCheck(uint8_t status
,
672 uint8_t* sensecodelist
)
674 for (uint8_t count
= 0; count
< 19; count
++)
675 sensecodelist
[count
] = 0;
677 sensecodelist
[0] = 18; //sense length
678 sensecodelist
[1] = 0x70; //we send a valid frame
679 sensecodelist
[3] = status
& 0xF; //mask to be sure + sensecode
680 sensecodelist
[8] = 0x1F; //data length
684 * read from the flashdisk
688 UFSHostDevice::UFSSCSIDevice::readFlash(uint8_t* readaddr
, uint64_t offset
,
691 /** read from image, and get to memory */
692 for (int count
= 0; count
< (size
/ SectorSize
); count
++)
693 flashDisk
->read(&(readaddr
[SectorSize
*count
]), (offset
/
694 SectorSize
) + count
);
698 * Write to the flashdisk
702 UFSHostDevice::UFSSCSIDevice::writeFlash(uint8_t* writeaddr
, uint64_t offset
,
705 /** Get from fifo and write to image*/
706 for (int count
= 0; count
< (size
/ SectorSize
); count
++)
707 flashDisk
->write(&(writeaddr
[SectorSize
* count
]),
708 (offset
/ SectorSize
) + count
);
712 * Constructor for the UFS Host device
715 UFSHostDevice::UFSHostDevice(const UFSHostDeviceParams
&p
) :
719 pioDelay(p
.pio_latency
),
722 lunAvail(p
.image
.size()),
723 UFSSlots(p
.ufs_slots
- 1),
733 SCSIResumeEvent([this]{ SCSIStart(); }, name()),
734 UTPEvent([this]{ finalUTP(); }, name())
736 DPRINTF(UFSHostDevice
, "The hostcontroller hosts %d Logic units\n",
738 UFSDevice
.resize(lunAvail
);
740 for (int count
= 0; count
< lunAvail
; count
++) {
741 UFSDevice
[count
] = new UFSSCSIDevice(p
, count
,
742 [this]() { LUNSignal(); },
743 [this]() { readCallback(); });
747 warn("UFSSlots = %d, this will results in %d command slots",
748 UFSSlots
, (UFSSlots
& 0x1F));
750 if ((UFSSlots
& 0x1F) == 0)
751 fatal("Number of UFS command slots should be between 1 and 32.");
757 UFSHostDeviceStats::UFSHostDeviceStats(UFSHostDevice
*parent
)
758 : Stats::Group(parent
, "UFSDiskHost"),
759 ADD_STAT(currentSCSIQueue
,
760 "Most up to date length of the command queue"),
761 ADD_STAT(currentReadSSDQueue
,
762 "Most up to date length of the read SSD queue"),
763 ADD_STAT(currentWriteSSDQueue
,
764 "Most up to date length of the write SSD queue"),
765 /** Amount of data read/written */
766 ADD_STAT(totalReadSSD
, "Number of bytes read from SSD"),
767 ADD_STAT(totalWrittenSSD
, "Number of bytes written to SSD"),
768 ADD_STAT(totalReadDiskTransactions
,"Number of transactions from disk"),
769 ADD_STAT(totalWriteDiskTransactions
, "Number of transactions to disk"),
770 ADD_STAT(totalReadUFSTransactions
, "Number of transactions from device"),
771 ADD_STAT(totalWriteUFSTransactions
, "Number of transactions to device"),
772 /** Average bandwidth for reads and writes */
773 ADD_STAT(averageReadSSDBW
, "Average read bandwidth (bytes/s)",
774 totalReadSSD
/ simSeconds
),
775 ADD_STAT(averageWriteSSDBW
, "Average write bandwidth (bytes/s)",
776 totalWrittenSSD
/ simSeconds
),
777 ADD_STAT(averageSCSIQueue
, "Average command queue length"),
778 ADD_STAT(averageReadSSDQueue
, "Average read queue length"),
779 ADD_STAT(averageWriteSSDQueue
, "Average write queue length"),
780 /** Number of doorbells rung*/
781 ADD_STAT(curDoorbell
, "Most up to date number of doorbells used",
782 parent
->activeDoorbells
),
783 ADD_STAT(maxDoorbell
, "Maximum number of doorbells utilized"),
784 ADD_STAT(averageDoorbell
, "Average number of Doorbells used"),
786 ADD_STAT(transactionLatency
, "Histogram of transaction times"),
787 ADD_STAT(idleTimes
, "Histogram of idle times")
789 using namespace Stats
;
791 // Register the stats
800 /** Amount of data read/written */
807 totalReadDiskTransactions
809 totalWriteDiskTransactions
811 totalReadUFSTransactions
813 totalWriteUFSTransactions
816 /** Average bandwidth for reads and writes */
830 /** Number of doorbells rung*/
852 void UFSHostDevice::setValues()
855 * The capability register is built up as follows:
856 * 31-29 RES; Testmode support; O3 delivery; 64 bit addr;
857 * 23-19 RES; 18-16 #TM Req slots; 15-5 RES;4-0 # TR slots
859 UFSHCIMem
.HCCAP
= 0x06070000 | (UFSSlots
& 0x1F);
860 UFSHCIMem
.HCversion
= 0x00010000; //version is 1.0
861 UFSHCIMem
.HCHCDDID
= 0xAA003C3C;// Arbitrary number
862 UFSHCIMem
.HCHCPMID
= 0x41524D48; //ARMH (not an official MIPI number)
863 UFSHCIMem
.TRUTRLDBR
= 0x00;
864 UFSHCIMem
.TMUTMRLDBR
= 0x00;
865 UFSHCIMem
.CMDUICCMDR
= 0x00;
866 // We can process CMD, TM, TR, device present
867 UFSHCIMem
.ORHostControllerStatus
= 0x08;
868 UFSHCIMem
.TRUTRLBA
= 0x00;
869 UFSHCIMem
.TRUTRLBAU
= 0x00;
870 UFSHCIMem
.TMUTMRLBA
= 0x00;
871 UFSHCIMem
.TMUTMRLBAU
= 0x00;
875 * Determine address ranges
879 UFSHostDevice::getAddrRanges() const
881 AddrRangeList ranges
;
882 ranges
.push_back(RangeSize(pioAddr
, pioSize
));
887 * UFSHCD read register. This function allows the system to read the
892 UFSHostDevice::read(PacketPtr pkt
)
896 switch (pkt
->getAddr() & 0xFF)
899 case regControllerCapabilities
:
900 data
= UFSHCIMem
.HCCAP
;
904 data
= UFSHCIMem
.HCversion
;
907 case regControllerDEVID
:
908 data
= UFSHCIMem
.HCHCDDID
;
911 case regControllerPRODID
:
912 data
= UFSHCIMem
.HCHCPMID
;
915 case regInterruptStatus
:
916 data
= UFSHCIMem
.ORInterruptStatus
;
917 UFSHCIMem
.ORInterruptStatus
= 0x00;
918 //TODO: Revise and extend
922 case regInterruptEnable
:
923 data
= UFSHCIMem
.ORInterruptEnable
;
926 case regControllerStatus
:
927 data
= UFSHCIMem
.ORHostControllerStatus
;
930 case regControllerEnable
:
931 data
= UFSHCIMem
.ORHostControllerEnable
;
934 case regUICErrorCodePHYAdapterLayer
:
935 data
= UFSHCIMem
.ORUECPA
;
938 case regUICErrorCodeDataLinkLayer
:
939 data
= UFSHCIMem
.ORUECDL
;
942 case regUICErrorCodeNetworkLayer
:
943 data
= UFSHCIMem
.ORUECN
;
946 case regUICErrorCodeTransportLayer
:
947 data
= UFSHCIMem
.ORUECT
;
950 case regUICErrorCodeDME
:
951 data
= UFSHCIMem
.ORUECDME
;
954 case regUTPTransferREQINTAGGControl
:
955 data
= UFSHCIMem
.ORUTRIACR
;
958 case regUTPTransferREQListBaseL
:
959 data
= UFSHCIMem
.TRUTRLBA
;
962 case regUTPTransferREQListBaseH
:
963 data
= UFSHCIMem
.TRUTRLBAU
;
966 case regUTPTransferREQDoorbell
:
967 data
= UFSHCIMem
.TRUTRLDBR
;
970 case regUTPTransferREQListClear
:
971 data
= UFSHCIMem
.TRUTRLCLR
;
974 case regUTPTransferREQListRunStop
:
975 data
= UFSHCIMem
.TRUTRLRSR
;
978 case regUTPTaskREQListBaseL
:
979 data
= UFSHCIMem
.TMUTMRLBA
;
982 case regUTPTaskREQListBaseH
:
983 data
= UFSHCIMem
.TMUTMRLBAU
;
986 case regUTPTaskREQDoorbell
:
987 data
= UFSHCIMem
.TMUTMRLDBR
;
990 case regUTPTaskREQListClear
:
991 data
= UFSHCIMem
.TMUTMRLCLR
;
994 case regUTPTaskREQListRunStop
:
995 data
= UFSHCIMem
.TMUTMRLRSR
;
999 data
= UFSHCIMem
.CMDUICCMDR
;
1002 case regUICCommandArg1
:
1003 data
= UFSHCIMem
.CMDUCMDARG1
;
1006 case regUICCommandArg2
:
1007 data
= UFSHCIMem
.CMDUCMDARG2
;
1010 case regUICCommandArg3
:
1011 data
= UFSHCIMem
.CMDUCMDARG3
;
1019 pkt
->setLE
<uint32_t>(data
);
1020 pkt
->makeResponse();
1025 * UFSHCD write function. This function allows access to the writeable
1026 * registers. If any function attempts to write value to an unwriteable
1027 * register entry, then the value will not be written.
1030 UFSHostDevice::write(PacketPtr pkt
)
1032 assert(pkt
->getSize() <= 4);
1034 const uint32_t data
= pkt
->getUintX(ByteOrder::little
);
1036 switch (pkt
->getAddr() & 0xFF)
1038 case regControllerCapabilities
://you shall not write to this
1041 case regUFSVersion
://you shall not write to this
1044 case regControllerDEVID
://you shall not write to this
1047 case regControllerPRODID
://you shall not write to this
1050 case regInterruptStatus
://you shall not write to this
1053 case regInterruptEnable
:
1054 UFSHCIMem
.ORInterruptEnable
= data
;
1057 case regControllerStatus
:
1058 UFSHCIMem
.ORHostControllerStatus
= data
;
1061 case regControllerEnable
:
1062 UFSHCIMem
.ORHostControllerEnable
= data
;
1065 case regUICErrorCodePHYAdapterLayer
:
1066 UFSHCIMem
.ORUECPA
= data
;
1069 case regUICErrorCodeDataLinkLayer
:
1070 UFSHCIMem
.ORUECDL
= data
;
1073 case regUICErrorCodeNetworkLayer
:
1074 UFSHCIMem
.ORUECN
= data
;
1077 case regUICErrorCodeTransportLayer
:
1078 UFSHCIMem
.ORUECT
= data
;
1081 case regUICErrorCodeDME
:
1082 UFSHCIMem
.ORUECDME
= data
;
1085 case regUTPTransferREQINTAGGControl
:
1086 UFSHCIMem
.ORUTRIACR
= data
;
1089 case regUTPTransferREQListBaseL
:
1090 UFSHCIMem
.TRUTRLBA
= data
;
1091 if (((UFSHCIMem
.TRUTRLBA
| UFSHCIMem
.TRUTRLBAU
) != 0x00) &&
1092 ((UFSHCIMem
.TMUTMRLBA
| UFSHCIMem
.TMUTMRLBAU
)!= 0x00))
1093 UFSHCIMem
.ORHostControllerStatus
|= UICCommandReady
;
1096 case regUTPTransferREQListBaseH
:
1097 UFSHCIMem
.TRUTRLBAU
= data
;
1098 if (((UFSHCIMem
.TRUTRLBA
| UFSHCIMem
.TRUTRLBAU
) != 0x00) &&
1099 ((UFSHCIMem
.TMUTMRLBA
| UFSHCIMem
.TMUTMRLBAU
) != 0x00))
1100 UFSHCIMem
.ORHostControllerStatus
|= UICCommandReady
;
1103 case regUTPTransferREQDoorbell
:
1104 if (!(UFSHCIMem
.TRUTRLDBR
) && data
)
1105 stats
.idleTimes
.sample(curTick() - idlePhaseStart
);
1106 UFSHCIMem
.TRUTRLDBR
|= data
;
1110 case regUTPTransferREQListClear
:
1111 UFSHCIMem
.TRUTRLCLR
= data
;
1114 case regUTPTransferREQListRunStop
:
1115 UFSHCIMem
.TRUTRLRSR
= data
;
1118 case regUTPTaskREQListBaseL
:
1119 UFSHCIMem
.TMUTMRLBA
= data
;
1120 if (((UFSHCIMem
.TRUTRLBA
| UFSHCIMem
.TRUTRLBAU
) != 0x00) &&
1121 ((UFSHCIMem
.TMUTMRLBA
| UFSHCIMem
.TMUTMRLBAU
) != 0x00))
1122 UFSHCIMem
.ORHostControllerStatus
|= UICCommandReady
;
1125 case regUTPTaskREQListBaseH
:
1126 UFSHCIMem
.TMUTMRLBAU
= data
;
1127 if (((UFSHCIMem
.TRUTRLBA
| UFSHCIMem
.TRUTRLBAU
) != 0x00) &&
1128 ((UFSHCIMem
.TMUTMRLBA
| UFSHCIMem
.TMUTMRLBAU
) != 0x00))
1129 UFSHCIMem
.ORHostControllerStatus
|= UICCommandReady
;
1132 case regUTPTaskREQDoorbell
:
1133 UFSHCIMem
.TMUTMRLDBR
|= data
;
1137 case regUTPTaskREQListClear
:
1138 UFSHCIMem
.TMUTMRLCLR
= data
;
1141 case regUTPTaskREQListRunStop
:
1142 UFSHCIMem
.TMUTMRLRSR
= data
;
1146 UFSHCIMem
.CMDUICCMDR
= data
;
1150 case regUICCommandArg1
:
1151 UFSHCIMem
.CMDUCMDARG1
= data
;
1154 case regUICCommandArg2
:
1155 UFSHCIMem
.CMDUCMDARG2
= data
;
1158 case regUICCommandArg3
:
1159 UFSHCIMem
.CMDUCMDARG3
= data
;
1162 default:break;//nothing happens, you try to access a register that
1167 pkt
->makeResponse();
1172 * Request handler. Determines where the request comes from and initiates the
1173 * appropriate actions accordingly.
1177 UFSHostDevice::requestHandler()
1179 Addr address
= 0x00;
1183 struct taskStart task_info
;
1184 struct transferStart transferstart_info
;
1185 transferstart_info
.done
= 0;
1188 * step1 determine what called us
1189 * step2 determine where to get it
1190 * Look for any request of which we where not yet aware
1192 while (((UFSHCIMem
.CMDUICCMDR
> 0x00) |
1193 ((UFSHCIMem
.TMUTMRLDBR
^ taskCommandTrack
) > 0x00) |
1194 ((UFSHCIMem
.TRUTRLDBR
^ transferTrack
) > 0x00)) ) {
1196 if (UFSHCIMem
.CMDUICCMDR
> 0x00) {
1198 * Command; general control of the Host controller.
1199 * no DMA transfer needed
1202 UFSHCIMem
.ORInterruptStatus
|= UICCommandCOMPL
;
1203 generateInterrupt();
1204 UFSHCIMem
.CMDUICCMDR
= 0x00;
1205 return; //command, nothing more we can do
1207 } else if ((UFSHCIMem
.TMUTMRLDBR
^ taskCommandTrack
) > 0x00) {
1209 * Task; flow control, meant for the device/Logic unit
1210 * DMA transfer is needed, flash will not be approached
1212 size
= sizeof(UTPUPIUTaskReq
);
1213 /**Find the position that is not handled yet*/
1214 count
= findLsbSet((UFSHCIMem
.TMUTMRLDBR
^ taskCommandTrack
));
1215 address
= UFSHCIMem
.TMUTMRLBAU
;
1217 address
= (count
* size
) + (address
<< 32) +
1218 UFSHCIMem
.TMUTMRLBA
;
1219 taskCommandTrack
|= mask
<< count
;
1221 inform("UFSmodel received a task from the system; this might"
1222 " lead to untested behaviour.\n");
1224 task_info
.mask
= mask
<< count
;
1225 task_info
.address
= address
;
1226 task_info
.size
= size
;
1227 task_info
.done
= UFSHCIMem
.TMUTMRLDBR
;
1228 taskInfo
.push_back(task_info
);
1229 taskEventQueue
.push_back(
1230 EventFunctionWrapper([this]{ taskStart(); }, name()));
1231 writeDevice(&taskEventQueue
.back(), false, address
, size
,
1232 reinterpret_cast<uint8_t*>
1233 (&taskInfo
.back().destination
), 0, 0);
1235 } else if ((UFSHCIMem
.TRUTRLDBR
^ transferTrack
) > 0x00) {
1237 * Transfer; Data transfer from or to the disk. There will be DMA
1238 * transfers, and the flash might be approached. Further
1239 * commands, are needed to specify the exact command.
1241 size
= sizeof(UTPTransferReqDesc
);
1242 /**Find the position that is not handled yet*/
1243 count
= findLsbSet((UFSHCIMem
.TRUTRLDBR
^ transferTrack
));
1244 address
= UFSHCIMem
.TRUTRLBAU
;
1246 address
= (count
* size
) + (address
<< 32) + UFSHCIMem
.TRUTRLBA
;
1248 transferTrack
|= mask
<< count
;
1249 DPRINTF(UFSHostDevice
, "Doorbell register: 0x%8x select #:"
1250 " 0x%8x completion info: 0x%8x\n", UFSHCIMem
.TRUTRLDBR
,
1251 count
, transferstart_info
.done
);
1253 transferstart_info
.done
= UFSHCIMem
.TRUTRLDBR
;
1256 transactionStart
[count
] = curTick(); //note the start time
1258 stats
.maxDoorbell
= (stats
.maxDoorbell
.value() < activeDoorbells
)
1259 ? activeDoorbells
: stats
.maxDoorbell
.value();
1260 stats
.averageDoorbell
= stats
.maxDoorbell
.value();
1263 * step3 start transfer
1264 * step4 register information; allowing the host to respond in
1267 transferstart_info
.mask
= mask
<< count
;
1268 transferstart_info
.address
= address
;
1269 transferstart_info
.size
= size
;
1270 transferstart_info
.done
= UFSHCIMem
.TRUTRLDBR
;
1271 transferStartInfo
.push_back(transferstart_info
);
1273 /**Deleted in readDone, queued in finalUTP*/
1274 transferStartInfo
.back().destination
= new struct
1276 DPRINTF(UFSHostDevice
, "Initial transfer start: 0x%8x\n",
1277 transferstart_info
.done
);
1278 transferEventQueue
.push_back(
1279 EventFunctionWrapper([this]{ transferStart(); }, name()));
1281 if (transferEventQueue
.size() < 2) {
1282 writeDevice(&transferEventQueue
.front(), false,
1283 address
, size
, reinterpret_cast<uint8_t*>
1284 (transferStartInfo
.front().destination
),0, 0);
1285 DPRINTF(UFSHostDevice
, "Transfer scheduled\n");
1296 UFSHostDevice::taskStart()
1298 DPRINTF(UFSHostDevice
, "Task start");
1299 taskHandler(&taskInfo
.front().destination
, taskInfo
.front().mask
,
1300 taskInfo
.front().address
, taskInfo
.front().size
);
1301 taskInfo
.pop_front();
1302 taskEventQueue
.pop_front();
1306 * Transfer start event
1310 UFSHostDevice::transferStart()
1312 DPRINTF(UFSHostDevice
, "Enter transfer event\n");
1313 transferHandler(transferStartInfo
.front().destination
,
1314 transferStartInfo
.front().mask
,
1315 transferStartInfo
.front().address
,
1316 transferStartInfo
.front().size
,
1317 transferStartInfo
.front().done
);
1319 transferStartInfo
.pop_front();
1320 DPRINTF(UFSHostDevice
, "Transfer queue size at end of event: "
1321 "0x%8x\n", transferEventQueue
.size());
1325 * Handles the commands that are given. At this point in time, not many
1326 * commands have been implemented in the driver.
1330 UFSHostDevice::commandHandler()
1332 if (UFSHCIMem
.CMDUICCMDR
== 0x16) {
1333 UFSHCIMem
.ORHostControllerStatus
|= 0x0F;//link startup
1339 * Handles the tasks that are given. At this point in time, not many tasks
1340 * have been implemented in the driver.
1344 UFSHostDevice::taskHandler(struct UTPUPIUTaskReq
* request_in
,
1345 uint32_t req_pos
, Addr finaladdress
, uint32_t
1349 * For now, just unpack and acknowledge the task without doing anything.
1350 * TODO Implement UFS tasks.
1352 inform("taskHandler\n");
1353 inform("%8x\n", request_in
->header
.dWord0
);
1354 inform("%8x\n", request_in
->header
.dWord1
);
1355 inform("%8x\n", request_in
->header
.dWord2
);
1357 request_in
->header
.dWord2
&= 0xffffff00;
1359 UFSHCIMem
.TMUTMRLDBR
&= ~(req_pos
);
1360 taskCommandTrack
&= ~(req_pos
);
1361 UFSHCIMem
.ORInterruptStatus
|= UTPTaskREQCOMPL
;
1363 readDevice(true, finaladdress
, finalsize
, reinterpret_cast<uint8_t*>
1364 (request_in
), true, NULL
);
1369 * Obtains the SCSI command (if any)
1370 * Two possibilities: if it contains a SCSI command, then it is a usable
1371 * message; if it doesnt contain a SCSI message, then it can't be handeld
1373 * This is the second stage of the transfer. We have the information about
1374 * where the next command can be found and what the type of command is. The
1375 * actions that are needed from the device its side are: get the information
1376 * and store the information such that we can reply.
1380 UFSHostDevice::transferHandler(struct UTPTransferReqDesc
* request_in
,
1381 int req_pos
, Addr finaladdress
, uint32_t
1382 finalsize
, uint32_t done
)
1385 Addr cmd_desc_addr
= 0x00;
1388 //acknowledge handling of the message
1389 DPRINTF(UFSHostDevice
, "SCSI message detected\n");
1390 request_in
->header
.dWord2
&= 0xffffff00;
1391 SCSIInfo
.RequestIn
= request_in
;
1392 SCSIInfo
.reqPos
= req_pos
;
1393 SCSIInfo
.finalAddress
= finaladdress
;
1394 SCSIInfo
.finalSize
= finalsize
;
1395 SCSIInfo
.destination
.resize(request_in
->PRDTableOffset
* 4
1396 + request_in
->PRDTableLength
* sizeof(UFSHCDSGEntry
));
1397 SCSIInfo
.done
= done
;
1399 assert(!SCSIResumeEvent
.scheduled());
1401 *Get the UTP command that has the SCSI command
1403 cmd_desc_addr
= request_in
->commandDescBaseAddrHi
;
1404 cmd_desc_addr
= (cmd_desc_addr
<< 32) |
1405 (request_in
->commandDescBaseAddrLo
& 0xffffffff);
1407 writeDevice(&SCSIResumeEvent
, false, cmd_desc_addr
,
1408 SCSIInfo
.destination
.size(), &SCSIInfo
.destination
[0],0, 0);
1410 DPRINTF(UFSHostDevice
, "SCSI scheduled\n");
1412 transferEventQueue
.pop_front();
1416 * Obtain LUN and put it in the right LUN queue. Each LUN has its own queue
1417 * of commands that need to be executed. This is the first instance where it
1418 * can be determined which Logic unit should handle the transfer. Then check
1419 * wether it should wait and queue or if it can continue.
1423 UFSHostDevice::SCSIStart()
1425 DPRINTF(UFSHostDevice
, "SCSI message on hold until ready\n");
1426 uint32_t LUN
= SCSIInfo
.destination
[2];
1427 UFSDevice
[LUN
]->SCSIInfoQueue
.push_back(SCSIInfo
);
1429 DPRINTF(UFSHostDevice
, "SCSI queue %d has %d elements\n", LUN
,
1430 UFSDevice
[LUN
]->SCSIInfoQueue
.size());
1432 /**There are 32 doorbells, so at max there can be 32 transactions*/
1433 if (UFSDevice
[LUN
]->SCSIInfoQueue
.size() < 2) //LUN is available
1436 else if (UFSDevice
[LUN
]->SCSIInfoQueue
.size() > 32)
1437 panic("SCSI queue is getting too big %d\n", UFSDevice
[LUN
]->
1438 SCSIInfoQueue
.size());
1441 * First transfer is done, fetch the next;
1442 * At this point, the device is busy, not the HC
1444 if (!transferEventQueue
.empty()) {
1447 * loading next data packet in case Another LUN
1448 * is approached in the mean time
1450 writeDevice(&transferEventQueue
.front(), false,
1451 transferStartInfo
.front().address
,
1452 transferStartInfo
.front().size
, reinterpret_cast<uint8_t*>
1453 (transferStartInfo
.front().destination
), 0, 0);
1455 DPRINTF(UFSHostDevice
, "Transfer scheduled");
1460 * Handles the transfer requests that are given.
1461 * There can be three types of transfer. SCSI specific, Reads and writes
1462 * apart from the data transfer, this also generates its own reply (UPIU
1463 * response). Information for this reply is stored in transferInfo and will
1464 * be used in transferDone
1468 UFSHostDevice::SCSIResume(uint32_t lun_id
)
1470 DPRINTF(UFSHostDevice
, "SCSIresume\n");
1471 if (UFSDevice
[lun_id
]->SCSIInfoQueue
.empty())
1472 panic("No SCSI message scheduled lun:%d Doorbell: 0x%8x", lun_id
,
1473 UFSHCIMem
.TRUTRLDBR
);
1475 /**old info, lets form it such that we can understand it*/
1476 struct UTPTransferReqDesc
* request_in
= UFSDevice
[lun_id
]->
1477 SCSIInfoQueue
.front().RequestIn
;
1479 uint32_t req_pos
= UFSDevice
[lun_id
]->SCSIInfoQueue
.front().reqPos
;
1481 Addr finaladdress
= UFSDevice
[lun_id
]->SCSIInfoQueue
.front().
1484 uint32_t finalsize
= UFSDevice
[lun_id
]->SCSIInfoQueue
.front().finalSize
;
1486 uint32_t* transfercommand
= reinterpret_cast<uint32_t*>
1487 (&(UFSDevice
[lun_id
]->SCSIInfoQueue
.front().destination
[0]));
1489 DPRINTF(UFSHostDevice
, "Task tag: 0x%8x\n", transfercommand
[0]>>24);
1490 /**call logic unit to handle SCSI command*/
1491 request_out_datain
= UFSDevice
[(transfercommand
[0] & 0xFF0000) >> 16]->
1492 SCSICMDHandle(transfercommand
);
1494 DPRINTF(UFSHostDevice
, "LUN: %d\n", request_out_datain
.LUN
);
1497 * build response stating that it was succesful
1498 * command completion, Logic unit number, and Task tag
1500 request_in
->header
.dWord0
= ((request_in
->header
.dWord0
>> 24) == 0x21)
1502 UFSDevice
[lun_id
]->transferInfo
.requestOut
.header
.dWord0
=
1503 request_in
->header
.dWord0
| (request_out_datain
.LUN
<< 8)
1504 | (transfercommand
[0] & 0xFF000000);
1505 /**SCSI status reply*/
1506 UFSDevice
[lun_id
]->transferInfo
.requestOut
.header
.dWord1
= 0x00000000 |
1507 (request_out_datain
.status
<< 24);
1508 /**segment size + EHS length (see UFS standard ch7)*/
1509 UFSDevice
[lun_id
]->transferInfo
.requestOut
.header
.dWord2
= 0x00000000 |
1510 ((request_out_datain
.senseSize
+ 2) << 24) | 0x05;
1511 /**amount of data that will follow*/
1512 UFSDevice
[lun_id
]->transferInfo
.requestOut
.senseDataLen
=
1513 request_out_datain
.senseSize
;
1516 for (uint8_t count
= 0; count
<request_out_datain
.senseSize
; count
++) {
1517 UFSDevice
[lun_id
]->transferInfo
.requestOut
.senseData
[count
] =
1518 request_out_datain
.senseCode
[count
+ 1];
1522 * At position defined by "request_in->PRDTableOffset" (counting 32 bit
1523 * words) in array "transfercommand" we have a scatter gather list, which
1524 * is usefull to us if we interpreted it as a UFSHCDSGEntry structure.
1526 struct UFSHCDSGEntry
* sglist
= reinterpret_cast<UFSHCDSGEntry
*>
1527 (&(transfercommand
[(request_in
->PRDTableOffset
)]));
1529 uint32_t length
= request_in
->PRDTableLength
;
1530 DPRINTF(UFSHostDevice
, "# PRDT entries: %d\n", length
);
1532 Addr response_addr
= request_in
->commandDescBaseAddrHi
;
1533 response_addr
= (response_addr
<< 32) |
1534 ((request_in
->commandDescBaseAddrLo
+
1535 (request_in
->responseUPIULength
<< 2)) & 0xffffffff);
1537 /**transferdone information packet filling*/
1538 UFSDevice
[lun_id
]->transferInfo
.responseStartAddr
= response_addr
;
1539 UFSDevice
[lun_id
]->transferInfo
.reqPos
= req_pos
;
1540 UFSDevice
[lun_id
]->transferInfo
.size
= finalsize
;
1541 UFSDevice
[lun_id
]->transferInfo
.address
= finaladdress
;
1542 UFSDevice
[lun_id
]->transferInfo
.destination
= reinterpret_cast<uint8_t*>
1543 (UFSDevice
[lun_id
]->SCSIInfoQueue
.front().RequestIn
);
1544 UFSDevice
[lun_id
]->transferInfo
.finished
= true;
1545 UFSDevice
[lun_id
]->transferInfo
.lunID
= request_out_datain
.LUN
;
1548 * In this part the data that needs to be transfered will be initiated
1549 * and the chain of DMA (and potentially) disk transactions will be
1552 if (request_out_datain
.expectMore
== 0x01) {
1554 manageWriteTransfer(request_out_datain
.LUN
, request_out_datain
.offset
,
1557 } else if (request_out_datain
.expectMore
== 0x02) {
1559 manageReadTransfer(request_out_datain
.msgSize
, request_out_datain
.LUN
,
1560 request_out_datain
.offset
, length
, sglist
);
1563 /**not disk related transfer, SCSI maintanance*/
1565 uint32_t size_accum
= 0;
1566 DPRINTF(UFSHostDevice
, "Data DMA size: 0x%8x\n",
1567 request_out_datain
.msgSize
);
1569 /**Transport the SCSI reponse data according to the SG list*/
1570 while ((length
> count
) && size_accum
1571 < (request_out_datain
.msgSize
- 1) &&
1572 (request_out_datain
.msgSize
!= 0x00)) {
1573 Addr SCSI_start
= sglist
[count
].upperAddr
;
1574 SCSI_start
= (SCSI_start
<< 32) |
1575 (sglist
[count
].baseAddr
& 0xFFFFFFFF);
1576 DPRINTF(UFSHostDevice
, "Data DMA start: 0x%8x\n", SCSI_start
);
1577 DPRINTF(UFSHostDevice
, "Data DMA size: 0x%8x\n",
1578 (sglist
[count
].size
+ 1));
1580 * safetynet; it has been shown that sg list may be optimistic in
1581 * the amount of data allocated, which can potentially lead to
1582 * some garbage data being send over. Hence this construction
1583 * that finds the least amount of data that needs to be
1586 uint32_t size_to_send
= sglist
[count
].size
+ 1;
1588 if (request_out_datain
.msgSize
< (size_to_send
+ size_accum
))
1589 size_to_send
= request_out_datain
.msgSize
- size_accum
;
1591 readDevice(false, SCSI_start
, size_to_send
,
1592 reinterpret_cast<uint8_t*>
1593 (&(request_out_datain
.message
.dataMsg
[size_accum
])),
1596 size_accum
+= size_to_send
;
1597 DPRINTF(UFSHostDevice
, "Total remaining: 0x%8x,accumulated so far"
1598 " : 0x%8x\n", (request_out_datain
.msgSize
- size_accum
),
1602 DPRINTF(UFSHostDevice
, "Transfer #: %d\n", count
);
1605 /**Go to the next stage of the answering process*/
1606 transferDone(response_addr
, req_pos
, UFSDevice
[lun_id
]->
1607 transferInfo
.requestOut
, finalsize
, finaladdress
,
1608 reinterpret_cast<uint8_t*>(request_in
), true, lun_id
);
1611 DPRINTF(UFSHostDevice
, "SCSI resume done\n");
1615 * Find finished transfer. Callback function. One of the LUNs is done with
1616 * the disk transfer and reports back to the controller. This function finds
1617 * out who it was, and calls transferDone.
1620 UFSHostDevice::LUNSignal()
1622 uint8_t this_lun
= 0;
1624 //while we haven't found the right lun, keep searching
1625 while ((this_lun
< lunAvail
) && !UFSDevice
[this_lun
]->finishedCommand())
1628 if (this_lun
< lunAvail
) {
1630 UFSDevice
[this_lun
]->clearSignal();
1631 //found it; call transferDone
1632 transferDone(UFSDevice
[this_lun
]->transferInfo
.responseStartAddr
,
1633 UFSDevice
[this_lun
]->transferInfo
.reqPos
,
1634 UFSDevice
[this_lun
]->transferInfo
.requestOut
,
1635 UFSDevice
[this_lun
]->transferInfo
.size
,
1636 UFSDevice
[this_lun
]->transferInfo
.address
,
1637 UFSDevice
[this_lun
]->transferInfo
.destination
,
1638 UFSDevice
[this_lun
]->transferInfo
.finished
,
1639 UFSDevice
[this_lun
]->transferInfo
.lunID
);
1643 panic("no LUN finished in tick %d\n", curTick());
1647 * Transfer done. When the data transfer is done, this function ensures
1648 * that the application is notified.
1652 UFSHostDevice::transferDone(Addr responseStartAddr
, uint32_t req_pos
,
1653 struct UTPUPIURSP request_out
, uint32_t size
,
1654 Addr address
, uint8_t* destination
,
1655 bool finished
, uint32_t lun_id
)
1657 /**Test whether SCSI queue hasn't popped prematurely*/
1658 if (UFSDevice
[lun_id
]->SCSIInfoQueue
.empty())
1659 panic("No SCSI message scheduled lun:%d Doorbell: 0x%8x", lun_id
,
1660 UFSHCIMem
.TRUTRLDBR
);
1662 DPRINTF(UFSHostDevice
, "DMA start: 0x%8x; DMA size: 0x%8x\n",
1663 responseStartAddr
, sizeof(request_out
));
1665 struct transferStart lastinfo
;
1666 lastinfo
.mask
= req_pos
;
1667 lastinfo
.done
= finished
;
1668 lastinfo
.address
= address
;
1669 lastinfo
.size
= size
;
1670 lastinfo
.destination
= reinterpret_cast<UTPTransferReqDesc
*>
1672 lastinfo
.lun_id
= lun_id
;
1674 transferEnd
.push_back(lastinfo
);
1676 DPRINTF(UFSHostDevice
, "Transfer done start\n");
1678 readDevice(false, responseStartAddr
, sizeof(request_out
),
1679 reinterpret_cast<uint8_t*>
1680 (&(UFSDevice
[lun_id
]->transferInfo
.requestOut
)),
1685 * finalUTP. Second part of the transfer done event.
1686 * this sends the final response: the UTP response. After this transaction
1687 * the doorbell shall be cleared, and the interupt shall be set.
1691 UFSHostDevice::finalUTP()
1693 uint32_t lun_id
= transferEnd
.front().lun_id
;
1695 UFSDevice
[lun_id
]->SCSIInfoQueue
.pop_front();
1696 DPRINTF(UFSHostDevice
, "SCSIInfoQueue size: %d, lun: %d\n",
1697 UFSDevice
[lun_id
]->SCSIInfoQueue
.size(), lun_id
);
1700 if (UFSHCIMem
.TRUTRLDBR
& transferEnd
.front().mask
) {
1702 while (!(transferEnd
.front().mask
& (0x1 << count
)))
1704 stats
.transactionLatency
.sample(curTick() -
1705 transactionStart
[count
]);
1708 /**Last message that will be transfered*/
1709 readDevice(true, transferEnd
.front().address
,
1710 transferEnd
.front().size
, reinterpret_cast<uint8_t*>
1711 (transferEnd
.front().destination
), true, NULL
);
1713 /**clean and ensure that the tracker is updated*/
1714 transferTrack
&= ~(transferEnd
.front().mask
);
1717 garbage
.push_back(transferEnd
.front().destination
);
1718 transferEnd
.pop_front();
1719 DPRINTF(UFSHostDevice
, "UTP handled\n");
1722 stats
.averageDoorbell
= stats
.maxDoorbell
.value();
1724 DPRINTF(UFSHostDevice
, "activeDoorbells: %d, pendingDoorbells: %d,"
1725 " garbage: %d, TransferEvent: %d\n", activeDoorbells
,
1726 pendingDoorbells
, garbage
.size(), transferEventQueue
.size());
1728 /**This is the moment that the device is available again*/
1729 if (!UFSDevice
[lun_id
]->SCSIInfoQueue
.empty())
1734 * Read done handling function, is only initiated at the end of a transaction
1737 UFSHostDevice::readDone()
1739 DPRINTF(UFSHostDevice
, "Read done start\n");
1742 /**Garbage collection; sort out the allocated UTP descriptor*/
1743 if (garbage
.size() > 0) {
1744 delete garbage
.front();
1745 garbage
.pop_front();
1748 /**done, generate interrupt if we havent got one already*/
1749 if (!(UFSHCIMem
.ORInterruptStatus
& 0x01)) {
1750 UFSHCIMem
.ORInterruptStatus
|= UTPTransferREQCOMPL
;
1751 generateInterrupt();
1755 if (!readDoneEvent
.empty()) {
1756 readDoneEvent
.pop_front();
1761 * set interrupt and sort out the doorbell register.
1765 UFSHostDevice::generateInterrupt()
1767 /**just to keep track of the transactions*/
1770 /**step5 clear doorbell*/
1771 UFSHCIMem
.TRUTRLDBR
&= transferTrack
;
1772 pendingDoorbells
= 0;
1773 DPRINTF(UFSHostDevice
, "Clear doorbell %X\n", UFSHCIMem
.TRUTRLDBR
);
1777 /**step6 raise interrupt*/
1778 gic
->sendInt(intNum
);
1779 DPRINTF(UFSHostDevice
, "Send interrupt @ transaction: 0x%8x!\n",
1788 UFSHostDevice::clearInterrupt()
1790 gic
->clearInt(intNum
);
1791 DPRINTF(UFSHostDevice
, "Clear interrupt: 0x%8x!\n", countInt
);
1795 if (!(UFSHCIMem
.TRUTRLDBR
)) {
1796 idlePhaseStart
= curTick();
1798 /**end of a transaction*/
1802 * Important to understand about the transfer flow:
1803 * We have basically three stages, The "system memory" stage, the "device
1804 * buffer" stage and the "disk" stage. In this model we assume an infinite
1805 * buffer, or a buffer that is big enough to store all the data in the
1806 * biggest transaction. Between the three stages are two queues. Those queues
1807 * store the messages to simulate their transaction from one stage to the
1808 * next. The manage{Action} function fills up one of the queues and triggers
1809 * the first event, which causes a chain reaction of events executed once
1810 * they pass through their queues. For a write action the stages are ordered
1811 * "system memory", "device buffer" and "disk", whereas the read transfers
1812 * happen "disk", "device buffer" and "system memory". The dma action in the
1813 * dma device is written from a bus perspective whereas this model is written
1814 * from a device perspective. To avoid confusion, the translation between the
1815 * two has been made in the writeDevice and readDevice funtions.
1820 * Dma transaction function: write device. Note that the dma action is
1821 * from a device perspective, while this function is from an initiator
1826 UFSHostDevice::writeDevice(Event
* additional_action
, bool toDisk
, Addr
1827 start
, int size
, uint8_t* destination
, uint64_t
1828 SCSIDiskOffset
, uint32_t lun_id
)
1830 DPRINTF(UFSHostDevice
, "Write transaction Start: 0x%8x; Size: %d\n",
1833 /**check whether transfer is all the way to the flash*/
1837 while (!writeDoneEvent
.empty() && (writeDoneEvent
.front().when()
1839 writeDoneEvent
.pop_front();
1841 writeDoneEvent
.push_back(
1842 EventFunctionWrapper([this]{ writeDone(); },
1844 assert(!writeDoneEvent
.back().scheduled());
1846 /**destination is an offset here since we are writing to a disk*/
1847 struct transferInfo new_transfer
;
1848 new_transfer
.offset
= SCSIDiskOffset
;
1849 new_transfer
.size
= size
;
1850 new_transfer
.lunID
= lun_id
;
1851 new_transfer
.filePointer
= 0;
1852 SSDWriteinfo
.push_back(new_transfer
);
1854 /**allocate appropriate buffer*/
1855 SSDWriteinfo
.back().buffer
.resize(size
);
1858 dmaPort
.dmaAction(MemCmd::ReadReq
, start
, size
,
1859 &writeDoneEvent
.back(),
1860 &SSDWriteinfo
.back().buffer
[0], 0);
1861 //yes, a readreq at a write device function is correct.
1862 DPRINTF(UFSHostDevice
, "Write to disk scheduled\n");
1865 assert(!additional_action
->scheduled());
1866 dmaPort
.dmaAction(MemCmd::ReadReq
, start
, size
,
1867 additional_action
, destination
, 0);
1868 DPRINTF(UFSHostDevice
, "Write scheduled\n");
1873 * Manage write transfer. Manages correct transfer flow and makes sure that
1874 * the queues are filled on time
1878 UFSHostDevice::manageWriteTransfer(uint8_t LUN
, uint64_t offset
, uint32_t
1879 sg_table_length
, struct UFSHCDSGEntry
*
1882 struct writeToDiskBurst next_packet
;
1884 next_packet
.SCSIDiskOffset
= offset
;
1886 UFSDevice
[LUN
]->setTotalWrite(sg_table_length
);
1889 * Break-up the transactions into actions defined by the scatter gather
1892 for (uint32_t count
= 0; count
< sg_table_length
; count
++) {
1893 next_packet
.start
= sglist
[count
].upperAddr
;
1894 next_packet
.start
= (next_packet
.start
<< 32) |
1895 (sglist
[count
].baseAddr
& 0xFFFFFFFF);
1896 next_packet
.LUN
= LUN
;
1897 DPRINTF(UFSHostDevice
, "Write data DMA start: 0x%8x\n",
1899 DPRINTF(UFSHostDevice
, "Write data DMA size: 0x%8x\n",
1900 (sglist
[count
].size
+ 1));
1901 assert(sglist
[count
].size
> 0);
1904 next_packet
.SCSIDiskOffset
= next_packet
.SCSIDiskOffset
+
1905 (sglist
[count
- 1].size
+ 1);
1907 next_packet
.size
= sglist
[count
].size
+ 1;
1909 /**If the queue is empty, the transaction should be initiated*/
1910 if (dmaWriteInfo
.empty())
1911 writeDevice(NULL
, true, next_packet
.start
, next_packet
.size
,
1912 NULL
, next_packet
.SCSIDiskOffset
, next_packet
.LUN
);
1914 DPRINTF(UFSHostDevice
, "Write not initiated queue: %d\n",
1915 dmaWriteInfo
.size());
1917 dmaWriteInfo
.push_back(next_packet
);
1918 DPRINTF(UFSHostDevice
, "Write Location: 0x%8x\n",
1919 next_packet
.SCSIDiskOffset
);
1921 DPRINTF(UFSHostDevice
, "Write transfer #: 0x%8x\n", count
+ 1);
1924 stats
.totalWrittenSSD
+= (sglist
[count
].size
+ 1);
1928 ++stats
.totalWriteUFSTransactions
;
1932 * Write done handling function. Is only initiated when the flash is directly
1937 UFSHostDevice::writeDone()
1939 /**DMA is done, information no longer needed*/
1940 assert(dmaWriteInfo
.size() > 0);
1941 dmaWriteInfo
.pop_front();
1942 assert(SSDWriteinfo
.size() > 0);
1943 uint32_t lun
= SSDWriteinfo
.front().lunID
;
1945 /**If there is nothing on the way, we need to start the events*/
1946 DPRINTF(UFSHostDevice
, "Write done entered, queue: %d\n",
1947 UFSDevice
[lun
]->SSDWriteDoneInfo
.size());
1949 UFSDevice
[lun
]->writeFlash(&SSDWriteinfo
.front().buffer
[0],
1950 SSDWriteinfo
.front().offset
,
1951 SSDWriteinfo
.front().size
);
1954 * Move to the second queue, enter the logic unit
1955 * This is where the disk is approached and the flash transaction is
1956 * handled SSDWriteDone will take care of the timing
1958 UFSDevice
[lun
]->SSDWriteDoneInfo
.push_back(SSDWriteinfo
.front());
1959 SSDWriteinfo
.pop_front();
1962 /**so far, only the DMA part has been handled, lets do the disk delay*/
1963 UFSDevice
[lun
]->SSDWriteStart();
1966 stats
.currentWriteSSDQueue
= UFSDevice
[lun
]->SSDWriteDoneInfo
.size();
1967 stats
.averageWriteSSDQueue
= UFSDevice
[lun
]->SSDWriteDoneInfo
.size();
1968 ++stats
.totalWriteDiskTransactions
;
1970 /**initiate the next dma action (if any)*/
1971 if (!dmaWriteInfo
.empty())
1972 writeDevice(NULL
, true, dmaWriteInfo
.front().start
,
1973 dmaWriteInfo
.front().size
, NULL
,
1974 dmaWriteInfo
.front().SCSIDiskOffset
,
1975 dmaWriteInfo
.front().LUN
);
1976 DPRINTF(UFSHostDevice
, "Write done end\n");
1980 * SSD write start. Starts the write action in the timing model
1983 UFSHostDevice::UFSSCSIDevice::SSDWriteStart()
1985 assert(SSDWriteDoneInfo
.size() > 0);
1986 flashDevice
->writeMemory(
1987 SSDWriteDoneInfo
.front().offset
,
1988 SSDWriteDoneInfo
.front().size
, memWriteCallback
);
1990 SSDWriteDoneInfo
.pop_front();
1992 DPRINTF(UFSHostDevice
, "Write is started; left in queue: %d\n",
1993 SSDWriteDoneInfo
.size());
2002 UFSHostDevice::UFSSCSIDevice::SSDWriteDone()
2004 DPRINTF(UFSHostDevice
, "Write disk, aiming for %d messages, %d so far\n",
2005 totalWrite
, amountOfWriteTransfers
);
2007 //we have done one extra transfer
2008 ++amountOfWriteTransfers
;
2010 /**test whether call was correct*/
2011 assert(totalWrite
>= amountOfWriteTransfers
&& totalWrite
!= 0);
2013 /**are we there yet? (did we do everything)*/
2014 if (totalWrite
== amountOfWriteTransfers
) {
2015 DPRINTF(UFSHostDevice
, "Write transactions finished\n");
2017 amountOfWriteTransfers
= 0;
2027 * Dma transaction function: read device. Notice that the dma action is from
2028 * a device perspective, while this function is from an initiator perspective
2032 UFSHostDevice::readDevice(bool lastTransfer
, Addr start
, uint32_t size
,
2033 uint8_t* destination
, bool no_cache
, Event
*
2036 DPRINTF(UFSHostDevice
, "Read start: 0x%8x; Size: %d, data[0]: 0x%8x\n",
2037 start
, size
, (reinterpret_cast<uint32_t *>(destination
))[0]);
2039 /** check wether interrupt is needed */
2042 readDoneEvent
.push_back(
2043 EventFunctionWrapper([this]{ readDone(); },
2045 assert(!readDoneEvent
.back().scheduled());
2046 dmaPort
.dmaAction(MemCmd::WriteReq
, start
, size
,
2047 &readDoneEvent
.back(), destination
, 0);
2048 //yes, a writereq at a read device function is correct.
2051 if (additional_action
!= NULL
)
2052 assert(!additional_action
->scheduled());
2054 dmaPort
.dmaAction(MemCmd::WriteReq
, start
, size
,
2055 additional_action
, destination
, 0);
2062 * Manage read transfer. Manages correct transfer flow and makes sure that
2063 * the queues are filled on time
2067 UFSHostDevice::manageReadTransfer(uint32_t size
, uint32_t LUN
, uint64_t
2068 offset
, uint32_t sg_table_length
,
2069 struct UFSHCDSGEntry
* sglist
)
2071 uint32_t size_accum
= 0;
2073 DPRINTF(UFSHostDevice
, "Data READ size: %d\n", size
);
2076 * Break-up the transactions into actions defined by the scatter gather
2079 for (uint32_t count
= 0; count
< sg_table_length
; count
++) {
2080 struct transferInfo new_transfer
;
2081 new_transfer
.offset
= sglist
[count
].upperAddr
;
2082 new_transfer
.offset
= (new_transfer
.offset
<< 32) |
2083 (sglist
[count
].baseAddr
& 0xFFFFFFFF);
2084 new_transfer
.filePointer
= offset
+ size_accum
;
2085 new_transfer
.size
= (sglist
[count
].size
+ 1);
2086 new_transfer
.lunID
= LUN
;
2088 DPRINTF(UFSHostDevice
, "Data READ start: 0x%8x; size: %d\n",
2089 new_transfer
.offset
, new_transfer
.size
);
2091 UFSDevice
[LUN
]->SSDReadInfo
.push_back(new_transfer
);
2092 UFSDevice
[LUN
]->SSDReadInfo
.back().buffer
.resize(sglist
[count
].size
2096 * The disk image is read here; but the action is simultated later
2097 * You can see this as the preparation stage, whereas later is the
2100 UFSDevice
[LUN
]->readFlash(&UFSDevice
[LUN
]->
2101 SSDReadInfo
.back().buffer
[0],
2102 offset
+ size_accum
,
2103 sglist
[count
].size
+ 1);
2105 size_accum
+= (sglist
[count
].size
+ 1);
2107 DPRINTF(UFSHostDevice
, "Transfer %d; Remaining: 0x%8x, Accumulated:"
2108 " 0x%8x\n", (count
+ 1), (size
-size_accum
), size_accum
);
2111 stats
.totalReadSSD
+= (sglist
[count
].size
+ 1);
2112 stats
.currentReadSSDQueue
= UFSDevice
[LUN
]->SSDReadInfo
.size();
2113 stats
.averageReadSSDQueue
= UFSDevice
[LUN
]->SSDReadInfo
.size();
2116 UFSDevice
[LUN
]->SSDReadStart(sg_table_length
);
2119 ++stats
.totalReadUFSTransactions
;
2126 * SSDisk start read; this function was created to keep the interfaces
2127 * between the layers simpler. Without this function UFSHost would need to
2128 * know about the flashdevice.
2132 UFSHostDevice::UFSSCSIDevice::SSDReadStart(uint32_t total_read
)
2134 totalRead
= total_read
;
2135 for (uint32_t number_handled
= 0; number_handled
< SSDReadInfo
.size();
2138 * Load all the read request to the Memory device.
2139 * It will call back when done.
2141 flashDevice
->readMemory(SSDReadInfo
.front().filePointer
,
2142 SSDReadInfo
.front().size
, memReadCallback
);
2153 UFSHostDevice::UFSSCSIDevice::SSDReadDone()
2155 DPRINTF(UFSHostDevice
, "SSD read done at lun %d, Aiming for %d messages,"
2156 " %d so far\n", lunID
, totalRead
, amountOfReadTransfers
);
2158 if (totalRead
== amountOfReadTransfers
) {
2160 amountOfReadTransfers
= 0;
2162 /**Callback: transferdone*/
2170 * Read callback, on the way from the disk to the DMA. Called by the flash
2171 * layer. Intermediate step to the host layer
2174 UFSHostDevice::UFSSCSIDevice::readCallback()
2176 ++amountOfReadTransfers
;
2178 /**Callback; make sure data is transfered upstream:
2179 * UFSHostDevice::readCallback
2182 deviceReadCallback();
2189 * Read callback, on the way from the disk to the DMA. Called by the UFSSCSI
2194 UFSHostDevice::readCallback()
2196 DPRINTF(UFSHostDevice
, "Read Callback\n");
2197 uint8_t this_lun
= 0;
2199 //while we haven't found the right lun, keep searching
2200 while ((this_lun
< lunAvail
) && !UFSDevice
[this_lun
]->finishedRead())
2203 DPRINTF(UFSHostDevice
, "Found LUN %d messages pending for clean: %d\n",
2204 this_lun
, SSDReadPending
.size());
2206 if (this_lun
< lunAvail
) {
2208 UFSDevice
[this_lun
]->clearReadSignal();
2209 SSDReadPending
.push_back(UFSDevice
[this_lun
]->SSDReadInfo
.front());
2210 UFSDevice
[this_lun
]->SSDReadInfo
.pop_front();
2211 readGarbageEventQueue
.push_back(
2212 EventFunctionWrapper([this]{ readGarbage(); }, name()));
2214 //make sure the queue is popped a the end of the dma transaction
2215 readDevice(false, SSDReadPending
.front().offset
,
2216 SSDReadPending
.front().size
,
2217 &SSDReadPending
.front().buffer
[0], false,
2218 &readGarbageEventQueue
.back());
2221 ++stats
.totalReadDiskTransactions
;
2224 panic("no read finished in tick %d\n", curTick());
2228 * After a disk read DMA transfer, the structure needs to be freed. This is
2229 * done in this function.
2232 UFSHostDevice::readGarbage()
2234 DPRINTF(UFSHostDevice
, "Clean read data, %d\n", SSDReadPending
.size());
2235 SSDReadPending
.pop_front();
2236 readGarbageEventQueue
.pop_front();
2240 * Serialize; needed to make checkpoints
2244 UFSHostDevice::serialize(CheckpointOut
&cp
) const
2246 DmaDevice::serialize(cp
);
2248 const uint8_t* temp_HCI_mem
= reinterpret_cast<const uint8_t*>(&UFSHCIMem
);
2249 SERIALIZE_ARRAY(temp_HCI_mem
, sizeof(HCIMem
));
2251 uint32_t lun_avail
= lunAvail
;
2252 SERIALIZE_SCALAR(lun_avail
);
2257 * Unserialize; needed to restore from checkpoints
2261 UFSHostDevice::unserialize(CheckpointIn
&cp
)
2263 DmaDevice::unserialize(cp
);
2264 uint8_t* temp_HCI_mem
= reinterpret_cast<uint8_t*>(&UFSHCIMem
);
2265 UNSERIALIZE_ARRAY(temp_HCI_mem
, sizeof(HCIMem
));
2268 UNSERIALIZE_SCALAR(lun_avail
);
2269 assert(lunAvail
== lun_avail
);
2274 * Drain; needed to enable checkpoints
2278 UFSHostDevice::drain()
2280 if (UFSHCIMem
.TRUTRLDBR
) {
2281 DPRINTF(UFSHostDevice
, "UFSDevice is draining...\n");
2282 return DrainState::Draining
;
2284 DPRINTF(UFSHostDevice
, "UFSDevice drained\n");
2285 return DrainState::Drained
;
2290 * Checkdrain; needed to enable checkpoints
2294 UFSHostDevice::checkDrain()
2296 if (drainState() != DrainState::Draining
)
2299 if (UFSHCIMem
.TRUTRLDBR
) {
2300 DPRINTF(UFSHostDevice
, "UFSDevice is still draining; with %d active"
2301 " doorbells\n", activeDoorbells
);
2303 DPRINTF(UFSHostDevice
, "UFSDevice is done draining\n");