ARM: Boilerplate full-system code.
[gem5.git] / src / dev / arm / versatile.cc
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2009 ARM Limited
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Ali Saidi
30 */
31
32 /** @file
33 * Implementation of Versatile platform.
34 */
35
36 #include <deque>
37 #include <string>
38 #include <vector>
39
40 #include "config/the_isa.hh"
41 #include "cpu/intr_control.hh"
42 #include "dev/arm/versatile.hh"
43 #include "dev/terminal.hh"
44 #include "sim/system.hh"
45
46 using namespace std;
47 using namespace TheISA;
48
49 Versatile::Versatile(const Params *p)
50 : Platform(p), system(p->system)
51 {
52 // set the back pointer from the system to myself
53 system->platform = this;
54 }
55
56 Tick
57 Versatile::intrFrequency()
58 {
59 panic("Need implementation\n");
60 M5_DUMMY_RETURN
61 }
62
63 void
64 Versatile::postConsoleInt()
65 {
66 warn_once("Don't know what interrupt to post for console.\n");
67 //panic("Need implementation\n");
68 }
69
70 void
71 Versatile::clearConsoleInt()
72 {
73 warn_once("Don't know what interrupt to clear for console.\n");
74 //panic("Need implementation\n");
75 }
76
77 void
78 Versatile::postPciInt(int line)
79 {
80 panic("Need implementation\n");
81 }
82
83 void
84 Versatile::clearPciInt(int line)
85 {
86 panic("Need implementation\n");
87 }
88
89 Addr
90 Versatile::pciToDma(Addr pciAddr) const
91 {
92 panic("Need implementation\n");
93 M5_DUMMY_RETURN
94 }
95
96
97 Addr
98 Versatile::calcPciConfigAddr(int bus, int dev, int func)
99 {
100 panic("Need implementation\n");
101 M5_DUMMY_RETURN
102 }
103
104 Addr
105 Versatile::calcPciIOAddr(Addr addr)
106 {
107 panic("Need implementation\n");
108 M5_DUMMY_RETURN
109 }
110
111 Addr
112 Versatile::calcPciMemAddr(Addr addr)
113 {
114 panic("Need implementation\n");
115 M5_DUMMY_RETURN
116 }
117
118 Versatile *
119 VersatileParams::create()
120 {
121 return new Versatile(this);
122 }