src/dev/arm/watchdog_sp805.hh

   1 /*
   2  * Copyright (c) 2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Adrian Herrera
  38  */
  39
  40 #ifndef __DEV_ARM_WATCHDOG_SP805_HH__
  41 #define __DEV_ARM_WATCHDOG_SP805_HH__
  42
  43 #include "dev/arm/amba_device.hh"
  44
  45 class Sp805Params;
  46
  47 /**
  48  * @file
  49  * Arm Watchdog Module (SP805)
  50  * Reference:
  51  *     Arm Watchdog Module (SP805) - Technical Reference Manual - rev. r1p0
  52  *     Doc. ID: ARM DDI 0270B
  53  */
  54 class Sp805 : public AmbaIntDevice
  55 {
  56   public:
  57     Sp805(Sp805Params const* params);
  58
  59     void serialize(CheckpointOut &cp) const override;
  60     void unserialize(CheckpointIn &cp) override;
  61
  62   protected:
  63     Tick read(PacketPtr pkt) override;
  64     Tick write(PacketPtr pkt) override;
  65
  66   private:
  67     enum Offset : Addr {
  68         WDOGLOAD      = 0x000,
  69         WDOGVALUE     = 0x004,
  70         WDOGCONTROL   = 0x008,
  71         WDOGINTCLR    = 0x00c,
  72         WDOGRIS       = 0x010,
  73         WDOGMIS       = 0x014,
  74         // 0x018 - 0xbfc -> Reserved
  75         WDOGLOCK      = 0xc00,
  76         // 0xc04 - 0xefc -> Reserved
  77         WDOGITCR      = 0xf00,
  78         WDOGITOP      = 0xf04,
  79         // 0xf08 - 0xfdc -> Reserved
  80         // 0xfe0 - 0xfff -> CoreSight / Peripheral ID (AMBA ID)
  81     };
  82
  83     /** Timeout interval (in cycles) as specified in WdogLoad */
  84     uint32_t timeoutInterval;
  85
  86     /** Timeout start tick to keep track of the counter value */
  87     Tick timeoutStartTick;
  88
  89     /** Value as persisted when the watchdog is stopped */
  90     uint32_t persistedValue;
  91
  92     /** Indicates if watchdog (counter and interrupt) is enabled */
  93     bool enabled;
  94
  95     /** Indicates if reset behaviour is enabled when counter reaches 0 */
  96     bool resetEnabled;
  97
  98     /** Indicates if an interrupt has been raised by the counter reaching 0 */
  99     bool intRaised;
 100
 101     /** Indicates if write access to registers is enabled */
 102     bool writeAccessEnabled;
 103
 104     /** Indicates if integration test harness is enabled */
 105     bool integrationTestEnabled;
 106
 107     /** Timeout event, triggered when the counter value reaches 0 */
 108     EventFunctionWrapper timeoutEvent;
 109
 110     /** Returns the current counter value */
 111     uint32_t value(void) const;
 112
 113     /** Triggered when value reaches 0 */
 114     void timeoutExpired(void);
 115
 116     /** Restarts the counter to the current timeout interval */
 117     void restartCounter(void);
 118
 119     /** Stops the counter when watchdog becomes disabled */
 120     void stopCounter(void);
 121
 122     /**
 123      * Raises an interrupt. If there is already a pending interrupt and
 124      * reset behaviour is enabled, asserts system reset
 125      */
 126     void sendInt(void);
 127
 128     /** Clears any active interrupts */
 129     void clearInt(void);
 130
 131     /** If written into WdogLock, registers are unlocked for writes */
 132     static constexpr uint32_t WDOGLOCK_MAGIC = 0x1acce551;
 133 };
 134
 135 #endif // __DEV_ARM_WATCHDOG_SP805_HH__