3c759ac1dfe16125c9fb1a311ebd781c6cd4db9a
2 * Copyright (c) 2008 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * Device model for Intel's I/O AT DMA copy engine.
37 #include "base/cp_annotate.hh"
38 #include "base/trace.hh"
39 #include "dev/copy_engine.hh"
40 #include "mem/packet.hh"
41 #include "mem/packet_access.hh"
42 #include "params/CopyEngine.hh"
43 #include "sim/stats.hh"
44 #include "sim/system.hh"
46 using namespace CopyEngineReg
;
49 CopyEngine::CopyEngine(const Params
*p
)
52 // All Reg regs are initialized to 0 by default
53 regs
.chanCount
= p
->ChanCnt
;
54 regs
.xferCap
= findMsbSet(p
->XferCap
);
57 if (regs
.chanCount
> 64)
58 fatal("CopyEngine interface doesn't support more than 64 DMA engines\n");
60 for (int x
= 0; x
< regs
.chanCount
; x
++) {
61 CopyEngineChannel
*ch
= new CopyEngineChannel(this, x
);
67 CopyEngine::CopyEngineChannel::CopyEngineChannel(CopyEngine
*_ce
, int cid
)
68 : ce(_ce
), channelId(cid
), busy(false), underReset(false),
69 refreshNext(false), latBeforeBegin(ce
->params()->latBeforeBegin
),
70 latAfterCompletion(ce
->params()->latAfterCompletion
),
71 completionDataReg(0), nextState(Idle
), drainEvent(NULL
),
72 fetchCompleteEvent(this), addrCompleteEvent(this),
73 readCompleteEvent(this), writeCompleteEvent(this),
74 statusCompleteEvent(this)
77 cr
.status
.dma_transfer_status(3);
79 cr
.completionAddr
= 0;
81 curDmaDesc
= new DmaDesc
;
82 memset(curDmaDesc
, 0, sizeof(DmaDesc
));
83 copyBuffer
= new uint8_t[ce
->params()->XferCap
];
86 CopyEngine::~CopyEngine()
88 for (int x
= 0; x
< chan
.size(); x
++) {
93 CopyEngine::CopyEngineChannel::~CopyEngineChannel()
104 for (int x
= 0; x
< chan
.size(); x
++)
109 CopyEngine::CopyEngineChannel::init()
113 cePort
= new DmaPort(ce
, ce
->sys
);
114 peer
= ce
->dmaPort
->getPeer()->getOwner()->getPort("");
115 peer
->setPeer(cePort
);
116 cePort
->setPeer(peer
);
120 CopyEngine::CopyEngineChannel::recvCommand()
122 if (cr
.command
.start_dma()) {
124 cr
.status
.dma_transfer_status(0);
125 nextState
= DescriptorFetch
;
126 fetchAddress
= cr
.descChainAddr
;
127 if (ce
->getState() == SimObject::Running
)
128 fetchDescriptor(cr
.descChainAddr
);
129 } else if (cr
.command
.append_dma()) {
131 nextState
= AddressFetch
;
132 if (ce
->getState() == SimObject::Running
)
133 fetchNextAddr(lastDescriptorAddr
);
136 } else if (cr
.command
.reset_dma()) {
140 cr
.status
.dma_transfer_status(3);
143 } else if (cr
.command
.resume_dma() || cr
.command
.abort_dma() ||
144 cr
.command
.suspend_dma())
145 panic("Resume, Abort, and Suspend are not supported\n");
150 CopyEngine::read(PacketPtr pkt
)
155 if (!getBAR(pkt
->getAddr(), bar
, daddr
))
156 panic("Invalid PCI memory access to unmapped memory.\n");
158 // Only Memory register BAR is allowed
161 int size
= pkt
->getSize();
162 if (size
!= sizeof(uint64_t) && size
!= sizeof(uint32_t) &&
163 size
!= sizeof(uint16_t) && size
!= sizeof(uint8_t)) {
164 panic("Unknown size for MMIO access: %d\n", pkt
->getSize());
167 DPRINTF(DMACopyEngine
, "Read device register %#X size: %d\n", daddr
, size
);
172 /// Handle read of register here
178 assert(size
== sizeof(regs
.chanCount
));
179 pkt
->set
<uint8_t>(regs
.chanCount
);
182 assert(size
== sizeof(regs
.xferCap
));
183 pkt
->set
<uint8_t>(regs
.xferCap
);
186 assert(size
== sizeof(uint8_t));
187 pkt
->set
<uint8_t>(regs
.intrctrl());
188 regs
.intrctrl
.master_int_enable(0);
191 assert(size
== sizeof(regs
.attnStatus
));
192 pkt
->set
<uint32_t>(regs
.attnStatus
);
196 panic("Read request to unknown register number: %#x\n", daddr
);
198 pkt
->makeAtomicResponse();
203 // Find which channel we're accessing
206 while (daddr
>= 0x80) {
211 if (chanid
>= regs
.chanCount
)
212 panic("Access to channel %d (device only configured for %d channels)",
213 chanid
, regs
.chanCount
);
216 /// Channel registers are handled here
218 chan
[chanid
]->channelRead(pkt
, daddr
, size
);
220 pkt
->makeAtomicResponse();
225 CopyEngine::CopyEngineChannel::channelRead(Packet
*pkt
, Addr daddr
, int size
)
229 assert(size
== sizeof(uint16_t));
230 pkt
->set
<uint16_t>(cr
.ctrl());
234 assert(size
== sizeof(uint64_t));
235 pkt
->set
<uint64_t>(cr
.status() | ~busy
);
238 assert(size
== sizeof(uint64_t) || size
== sizeof(uint32_t));
239 if (size
== sizeof(uint64_t))
240 pkt
->set
<uint64_t>(cr
.descChainAddr
);
242 pkt
->set
<uint32_t>(bits(cr
.descChainAddr
,0,31));
244 case CHAN_CHAINADDR_HIGH
:
245 assert(size
== sizeof(uint32_t));
246 pkt
->set
<uint32_t>(bits(cr
.descChainAddr
,32,63));
249 assert(size
== sizeof(uint8_t));
250 pkt
->set
<uint32_t>(cr
.command());
253 assert(size
== sizeof(uint64_t) || size
== sizeof(uint32_t));
254 if (size
== sizeof(uint64_t))
255 pkt
->set
<uint64_t>(cr
.completionAddr
);
257 pkt
->set
<uint32_t>(bits(cr
.completionAddr
,0,31));
259 case CHAN_CMPLNADDR_HIGH
:
260 assert(size
== sizeof(uint32_t));
261 pkt
->set
<uint32_t>(bits(cr
.completionAddr
,32,63));
264 assert(size
== sizeof(uint32_t));
265 pkt
->set
<uint32_t>(cr
.error());
268 panic("Read request to unknown channel register number: (%d)%#x\n",
275 CopyEngine::write(PacketPtr pkt
)
281 if (!getBAR(pkt
->getAddr(), bar
, daddr
))
282 panic("Invalid PCI memory access to unmapped memory.\n");
284 // Only Memory register BAR is allowed
287 int size
= pkt
->getSize();
290 /// Handle write of register here
293 if (size
== sizeof(uint64_t)) {
294 uint64_t val M5_VAR_USED
= pkt
->get
<uint64_t>();
295 DPRINTF(DMACopyEngine
, "Wrote device register %#X value %#X\n", daddr
, val
);
296 } else if (size
== sizeof(uint32_t)) {
297 uint32_t val M5_VAR_USED
= pkt
->get
<uint32_t>();
298 DPRINTF(DMACopyEngine
, "Wrote device register %#X value %#X\n", daddr
, val
);
299 } else if (size
== sizeof(uint16_t)) {
300 uint16_t val M5_VAR_USED
= pkt
->get
<uint16_t>();
301 DPRINTF(DMACopyEngine
, "Wrote device register %#X value %#X\n", daddr
, val
);
302 } else if (size
== sizeof(uint8_t)) {
303 uint8_t val M5_VAR_USED
= pkt
->get
<uint8_t>();
304 DPRINTF(DMACopyEngine
, "Wrote device register %#X value %#X\n", daddr
, val
);
306 panic("Unknown size for MMIO access: %d\n", size
);
314 DPRINTF(DMACopyEngine
, "Warning, ignorning write to register %x\n",
318 regs
.intrctrl
.master_int_enable(bits(pkt
->get
<uint8_t>(),0,1));
321 panic("Read request to unknown register number: %#x\n", daddr
);
323 pkt
->makeAtomicResponse();
327 // Find which channel we're accessing
330 while (daddr
>= 0x80) {
335 if (chanid
>= regs
.chanCount
)
336 panic("Access to channel %d (device only configured for %d channels)",
337 chanid
, regs
.chanCount
);
340 /// Channel registers are handled here
342 chan
[chanid
]->channelWrite(pkt
, daddr
, size
);
344 pkt
->makeAtomicResponse();
349 CopyEngine::CopyEngineChannel::channelWrite(Packet
*pkt
, Addr daddr
, int size
)
353 assert(size
== sizeof(uint16_t));
355 old_int_disable
= cr
.ctrl
.interrupt_disable();
356 cr
.ctrl(pkt
->get
<uint16_t>());
357 if (cr
.ctrl
.interrupt_disable())
358 cr
.ctrl
.interrupt_disable(0);
360 cr
.ctrl
.interrupt_disable(old_int_disable
);
363 assert(size
== sizeof(uint64_t));
364 DPRINTF(DMACopyEngine
, "Warning, ignorning write to register %x\n",
368 assert(size
== sizeof(uint64_t) || size
== sizeof(uint32_t));
369 if (size
== sizeof(uint64_t))
370 cr
.descChainAddr
= pkt
->get
<uint64_t>();
372 cr
.descChainAddr
= (uint64_t)pkt
->get
<uint32_t>() |
373 (cr
.descChainAddr
& ~mask(32));
374 DPRINTF(DMACopyEngine
, "Chain Address %x\n", cr
.descChainAddr
);
376 case CHAN_CHAINADDR_HIGH
:
377 assert(size
== sizeof(uint32_t));
378 cr
.descChainAddr
= ((uint64_t)pkt
->get
<uint32_t>() <<32) |
379 (cr
.descChainAddr
& mask(32));
380 DPRINTF(DMACopyEngine
, "Chain Address %x\n", cr
.descChainAddr
);
383 assert(size
== sizeof(uint8_t));
384 cr
.command(pkt
->get
<uint8_t>());
388 assert(size
== sizeof(uint64_t) || size
== sizeof(uint32_t));
389 if (size
== sizeof(uint64_t))
390 cr
.completionAddr
= pkt
->get
<uint64_t>();
392 cr
.completionAddr
= pkt
->get
<uint32_t>() |
393 (cr
.completionAddr
& ~mask(32));
395 case CHAN_CMPLNADDR_HIGH
:
396 assert(size
== sizeof(uint32_t));
397 cr
.completionAddr
= ((uint64_t)pkt
->get
<uint32_t>() <<32) |
398 (cr
.completionAddr
& mask(32));
401 assert(size
== sizeof(uint32_t));
402 cr
.error(~pkt
->get
<uint32_t>() & cr
.error());
405 panic("Read request to unknown channel register number: (%d)%#x\n",
411 CopyEngine::regStats()
413 using namespace Stats
;
415 .init(regs
.chanCount
)
416 .name(name() + ".bytes_copied")
417 .desc("Number of bytes copied by each engine")
421 .init(regs
.chanCount
)
422 .name(name() + ".copies_processed")
423 .desc("Number of copies processed by each engine")
429 CopyEngine::CopyEngineChannel::fetchDescriptor(Addr address
)
432 anBegin("FetchDescriptor");
433 DPRINTF(DMACopyEngine
, "Reading descriptor from at memory location %#x(%#x)\n",
434 address
, ce
->platform
->pciToDma(address
));
438 DPRINTF(DMACopyEngine
, "dmaAction: %#x, %d bytes, to addr %#x\n",
439 ce
->platform
->pciToDma(address
), sizeof(DmaDesc
), curDmaDesc
);
441 cePort
->dmaAction(MemCmd::ReadReq
, ce
->platform
->pciToDma(address
),
442 sizeof(DmaDesc
), &fetchCompleteEvent
, (uint8_t*)curDmaDesc
,
444 lastDescriptorAddr
= address
;
448 CopyEngine::CopyEngineChannel::fetchDescComplete()
450 DPRINTF(DMACopyEngine
, "Read of descriptor complete\n");
452 if ((curDmaDesc
->command
& DESC_CTRL_NULL
)) {
453 DPRINTF(DMACopyEngine
, "Got NULL descriptor, skipping\n");
454 assert(!(curDmaDesc
->command
& DESC_CTRL_CP_STS
));
455 if (curDmaDesc
->command
& DESC_CTRL_CP_STS
) {
456 panic("Shouldn't be able to get here\n");
457 nextState
= CompletionWrite
;
458 if (inDrain()) return;
459 writeCompletionStatus();
470 if (curDmaDesc
->command
& ~DESC_CTRL_CP_STS
)
471 panic("Descriptor has flag other that completion status set\n");
474 if (inDrain()) return;
479 CopyEngine::CopyEngineChannel::readCopyBytes()
481 anBegin("ReadCopyBytes");
482 DPRINTF(DMACopyEngine
, "Reading %d bytes from buffer to memory location %#x(%#x)\n",
483 curDmaDesc
->len
, curDmaDesc
->dest
,
484 ce
->platform
->pciToDma(curDmaDesc
->src
));
485 cePort
->dmaAction(MemCmd::ReadReq
, ce
->platform
->pciToDma(curDmaDesc
->src
),
486 curDmaDesc
->len
, &readCompleteEvent
, copyBuffer
, 0);
490 CopyEngine::CopyEngineChannel::readCopyBytesComplete()
492 DPRINTF(DMACopyEngine
, "Read of bytes to copy complete\n");
494 nextState
= DMAWrite
;
495 if (inDrain()) return;
500 CopyEngine::CopyEngineChannel::writeCopyBytes()
502 anBegin("WriteCopyBytes");
503 DPRINTF(DMACopyEngine
, "Writing %d bytes from buffer to memory location %#x(%#x)\n",
504 curDmaDesc
->len
, curDmaDesc
->dest
,
505 ce
->platform
->pciToDma(curDmaDesc
->dest
));
507 cePort
->dmaAction(MemCmd::WriteReq
, ce
->platform
->pciToDma(curDmaDesc
->dest
),
508 curDmaDesc
->len
, &writeCompleteEvent
, copyBuffer
, 0);
510 ce
->bytesCopied
[channelId
] += curDmaDesc
->len
;
511 ce
->copiesProcessed
[channelId
]++;
515 CopyEngine::CopyEngineChannel::writeCopyBytesComplete()
517 DPRINTF(DMACopyEngine
, "Write of bytes to copy complete user1: %#x\n",
520 cr
.status
.compl_desc_addr(lastDescriptorAddr
>> 6);
521 completionDataReg
= cr
.status() | 1;
523 anQ("DMAUsedDescQ", channelId
, 1);
524 anQ("AppRecvQ", curDmaDesc
->user1
, curDmaDesc
->len
);
525 if (curDmaDesc
->command
& DESC_CTRL_CP_STS
) {
526 nextState
= CompletionWrite
;
527 if (inDrain()) return;
528 writeCompletionStatus();
532 continueProcessing();
536 CopyEngine::CopyEngineChannel::continueProcessing()
550 if (curDmaDesc
->next
) {
551 nextState
= DescriptorFetch
;
552 fetchAddress
= curDmaDesc
->next
;
553 if (inDrain()) return;
554 fetchDescriptor(curDmaDesc
->next
);
555 } else if (refreshNext
) {
556 nextState
= AddressFetch
;
558 if (inDrain()) return;
559 fetchNextAddr(lastDescriptorAddr
);
569 CopyEngine::CopyEngineChannel::writeCompletionStatus()
571 anBegin("WriteCompletionStatus");
572 DPRINTF(DMACopyEngine
, "Writing completion status %#x to address %#x(%#x)\n",
573 completionDataReg
, cr
.completionAddr
,
574 ce
->platform
->pciToDma(cr
.completionAddr
));
576 cePort
->dmaAction(MemCmd::WriteReq
, ce
->platform
->pciToDma(cr
.completionAddr
),
577 sizeof(completionDataReg
), &statusCompleteEvent
,
578 (uint8_t*)&completionDataReg
, latAfterCompletion
);
582 CopyEngine::CopyEngineChannel::writeStatusComplete()
584 DPRINTF(DMACopyEngine
, "Writing completion status complete\n");
585 continueProcessing();
589 CopyEngine::CopyEngineChannel::fetchNextAddr(Addr address
)
591 anBegin("FetchNextAddr");
592 DPRINTF(DMACopyEngine
, "Fetching next address...\n");
594 cePort
->dmaAction(MemCmd::ReadReq
, ce
->platform
->pciToDma(address
+
595 offsetof(DmaDesc
, next
)), sizeof(Addr
), &addrCompleteEvent
,
596 (uint8_t*)curDmaDesc
+ offsetof(DmaDesc
, next
), 0);
600 CopyEngine::CopyEngineChannel::fetchAddrComplete()
602 DPRINTF(DMACopyEngine
, "Fetching next address complete: %#x\n",
604 if (!curDmaDesc
->next
) {
605 DPRINTF(DMACopyEngine
, "Got NULL descriptor, nothing more to do\n");
613 nextState
= DescriptorFetch
;
614 fetchAddress
= curDmaDesc
->next
;
615 if (inDrain()) return;
616 fetchDescriptor(curDmaDesc
->next
);
620 CopyEngine::CopyEngineChannel::inDrain()
622 if (ce
->getState() == SimObject::Draining
) {
623 DPRINTF(DMACopyEngine
, "processing drain\n");
625 drainEvent
->process();
629 return ce
->getState() != SimObject::Running
;
633 CopyEngine::CopyEngineChannel::drain(Event
*de
)
635 if (nextState
== Idle
|| ce
->getState() != SimObject::Running
)
637 unsigned int count
= 1;
638 count
+= cePort
->drain(de
);
640 DPRINTF(DMACopyEngine
, "unable to drain, returning %d\n", count
);
646 CopyEngine::drain(Event
*de
)
649 count
= pioPort
->drain(de
) + dmaPort
->drain(de
) + configPort
->drain(de
);
650 for (int x
= 0;x
< chan
.size(); x
++)
651 count
+= chan
[x
]->drain(de
);
654 changeState(Draining
);
656 changeState(Drained
);
658 DPRINTF(DMACopyEngine
, "call to CopyEngine::drain() returning %d\n", count
);
663 CopyEngine::serialize(std::ostream
&os
)
665 PciDev::serialize(os
);
667 for (int x
=0; x
< chan
.size(); x
++) {
668 nameOut(os
, csprintf("%s.channel%d", name(), x
));
669 chan
[x
]->serialize(os
);
674 CopyEngine::unserialize(Checkpoint
*cp
, const std::string
§ion
)
676 PciDev::unserialize(cp
, section
);
677 regs
.unserialize(cp
, section
);
678 for (int x
= 0; x
< chan
.size(); x
++)
679 chan
[x
]->unserialize(cp
, csprintf("%s.channel%d", section
, x
));
683 CopyEngine::CopyEngineChannel::serialize(std::ostream
&os
)
685 SERIALIZE_SCALAR(channelId
);
686 SERIALIZE_SCALAR(busy
);
687 SERIALIZE_SCALAR(underReset
);
688 SERIALIZE_SCALAR(refreshNext
);
689 SERIALIZE_SCALAR(lastDescriptorAddr
);
690 SERIALIZE_SCALAR(completionDataReg
);
691 SERIALIZE_SCALAR(fetchAddress
);
692 int nextState
= this->nextState
;
693 SERIALIZE_SCALAR(nextState
);
694 arrayParamOut(os
, "curDmaDesc", (uint8_t*)curDmaDesc
, sizeof(DmaDesc
));
695 SERIALIZE_ARRAY(copyBuffer
, ce
->params()->XferCap
);
700 CopyEngine::CopyEngineChannel::unserialize(Checkpoint
*cp
, const std::string
§ion
)
702 UNSERIALIZE_SCALAR(channelId
);
703 UNSERIALIZE_SCALAR(busy
);
704 UNSERIALIZE_SCALAR(underReset
);
705 UNSERIALIZE_SCALAR(refreshNext
);
706 UNSERIALIZE_SCALAR(lastDescriptorAddr
);
707 UNSERIALIZE_SCALAR(completionDataReg
);
708 UNSERIALIZE_SCALAR(fetchAddress
);
710 UNSERIALIZE_SCALAR(nextState
);
711 this->nextState
= (ChannelState
)nextState
;
712 arrayParamIn(cp
, section
, "curDmaDesc", (uint8_t*)curDmaDesc
, sizeof(DmaDesc
));
713 UNSERIALIZE_ARRAY(copyBuffer
, ce
->params()->XferCap
);
714 cr
.unserialize(cp
, section
);
719 CopyEngine::CopyEngineChannel::restartStateMachine()
723 fetchNextAddr(lastDescriptorAddr
);
725 case DescriptorFetch
:
726 fetchDescriptor(fetchAddress
);
734 case CompletionWrite
:
735 writeCompletionStatus();
740 panic("Unknown state for CopyEngineChannel\n");
748 for (int x
= 0;x
< chan
.size(); x
++)
754 CopyEngine::CopyEngineChannel::resume()
756 DPRINTF(DMACopyEngine
, "Restarting state machine at state %d\n", nextState
);
757 restartStateMachine();
761 CopyEngineParams::create()
763 return new CopyEngine(this);