2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2008 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 * Device model for Intel's I/O AT DMA copy engine.
49 #include "base/cp_annotate.hh"
50 #include "base/trace.hh"
51 #include "debug/DMACopyEngine.hh"
52 #include "debug/Drain.hh"
53 #include "dev/copy_engine.hh"
54 #include "mem/packet.hh"
55 #include "mem/packet_access.hh"
56 #include "params/CopyEngine.hh"
57 #include "sim/stats.hh"
58 #include "sim/system.hh"
60 using namespace CopyEngineReg
;
62 CopyEngine::CopyEngine(const Params
*p
)
65 // All Reg regs are initialized to 0 by default
66 regs
.chanCount
= p
->ChanCnt
;
67 regs
.xferCap
= findMsbSet(p
->XferCap
);
70 if (regs
.chanCount
> 64)
71 fatal("CopyEngine interface doesn't support more than 64 DMA engines\n");
73 for (int x
= 0; x
< regs
.chanCount
; x
++) {
74 CopyEngineChannel
*ch
= new CopyEngineChannel(this, x
);
80 CopyEngine::CopyEngineChannel::CopyEngineChannel(CopyEngine
*_ce
, int cid
)
81 : cePort(_ce
, _ce
->sys
),
82 ce(_ce
), channelId(cid
), busy(false), underReset(false),
83 refreshNext(false), latBeforeBegin(ce
->params()->latBeforeBegin
),
84 latAfterCompletion(ce
->params()->latAfterCompletion
),
85 completionDataReg(0), nextState(Idle
), drainEvent(NULL
),
86 fetchCompleteEvent(this), addrCompleteEvent(this),
87 readCompleteEvent(this), writeCompleteEvent(this),
88 statusCompleteEvent(this)
91 cr
.status
.dma_transfer_status(3);
93 cr
.completionAddr
= 0;
95 curDmaDesc
= new DmaDesc
;
96 memset(curDmaDesc
, 0, sizeof(DmaDesc
));
97 copyBuffer
= new uint8_t[ce
->params()->XferCap
];
100 CopyEngine::~CopyEngine()
102 for (int x
= 0; x
< chan
.size(); x
++) {
107 CopyEngine::CopyEngineChannel::~CopyEngineChannel()
110 delete [] copyBuffer
;
114 CopyEngine::getMasterPort(const std::string
&if_name
, PortID idx
)
116 if (if_name
!= "dma") {
117 // pass it along to our super class
118 return PciDev::getMasterPort(if_name
, idx
);
120 if (idx
>= static_cast<int>(chan
.size())) {
121 panic("CopyEngine::getMasterPort: unknown index %d\n", idx
);
124 return chan
[idx
]->getMasterPort();
130 CopyEngine::CopyEngineChannel::getMasterPort()
136 CopyEngine::CopyEngineChannel::recvCommand()
138 if (cr
.command
.start_dma()) {
140 cr
.status
.dma_transfer_status(0);
141 nextState
= DescriptorFetch
;
142 fetchAddress
= cr
.descChainAddr
;
143 if (ce
->getState() == SimObject::Running
)
144 fetchDescriptor(cr
.descChainAddr
);
145 } else if (cr
.command
.append_dma()) {
147 nextState
= AddressFetch
;
148 if (ce
->getState() == SimObject::Running
)
149 fetchNextAddr(lastDescriptorAddr
);
152 } else if (cr
.command
.reset_dma()) {
156 cr
.status
.dma_transfer_status(3);
159 } else if (cr
.command
.resume_dma() || cr
.command
.abort_dma() ||
160 cr
.command
.suspend_dma())
161 panic("Resume, Abort, and Suspend are not supported\n");
166 CopyEngine::read(PacketPtr pkt
)
171 if (!getBAR(pkt
->getAddr(), bar
, daddr
))
172 panic("Invalid PCI memory access to unmapped memory.\n");
174 // Only Memory register BAR is allowed
177 int size
= pkt
->getSize();
178 if (size
!= sizeof(uint64_t) && size
!= sizeof(uint32_t) &&
179 size
!= sizeof(uint16_t) && size
!= sizeof(uint8_t)) {
180 panic("Unknown size for MMIO access: %d\n", pkt
->getSize());
183 DPRINTF(DMACopyEngine
, "Read device register %#X size: %d\n", daddr
, size
);
188 /// Handle read of register here
194 assert(size
== sizeof(regs
.chanCount
));
195 pkt
->set
<uint8_t>(regs
.chanCount
);
198 assert(size
== sizeof(regs
.xferCap
));
199 pkt
->set
<uint8_t>(regs
.xferCap
);
202 assert(size
== sizeof(uint8_t));
203 pkt
->set
<uint8_t>(regs
.intrctrl());
204 regs
.intrctrl
.master_int_enable(0);
207 assert(size
== sizeof(regs
.attnStatus
));
208 pkt
->set
<uint32_t>(regs
.attnStatus
);
212 panic("Read request to unknown register number: %#x\n", daddr
);
214 pkt
->makeAtomicResponse();
219 // Find which channel we're accessing
222 while (daddr
>= 0x80) {
227 if (chanid
>= regs
.chanCount
)
228 panic("Access to channel %d (device only configured for %d channels)",
229 chanid
, regs
.chanCount
);
232 /// Channel registers are handled here
234 chan
[chanid
]->channelRead(pkt
, daddr
, size
);
236 pkt
->makeAtomicResponse();
241 CopyEngine::CopyEngineChannel::channelRead(Packet
*pkt
, Addr daddr
, int size
)
245 assert(size
== sizeof(uint16_t));
246 pkt
->set
<uint16_t>(cr
.ctrl());
250 assert(size
== sizeof(uint64_t));
251 pkt
->set
<uint64_t>(cr
.status() | ~busy
);
254 assert(size
== sizeof(uint64_t) || size
== sizeof(uint32_t));
255 if (size
== sizeof(uint64_t))
256 pkt
->set
<uint64_t>(cr
.descChainAddr
);
258 pkt
->set
<uint32_t>(bits(cr
.descChainAddr
,0,31));
260 case CHAN_CHAINADDR_HIGH
:
261 assert(size
== sizeof(uint32_t));
262 pkt
->set
<uint32_t>(bits(cr
.descChainAddr
,32,63));
265 assert(size
== sizeof(uint8_t));
266 pkt
->set
<uint32_t>(cr
.command());
269 assert(size
== sizeof(uint64_t) || size
== sizeof(uint32_t));
270 if (size
== sizeof(uint64_t))
271 pkt
->set
<uint64_t>(cr
.completionAddr
);
273 pkt
->set
<uint32_t>(bits(cr
.completionAddr
,0,31));
275 case CHAN_CMPLNADDR_HIGH
:
276 assert(size
== sizeof(uint32_t));
277 pkt
->set
<uint32_t>(bits(cr
.completionAddr
,32,63));
280 assert(size
== sizeof(uint32_t));
281 pkt
->set
<uint32_t>(cr
.error());
284 panic("Read request to unknown channel register number: (%d)%#x\n",
291 CopyEngine::write(PacketPtr pkt
)
297 if (!getBAR(pkt
->getAddr(), bar
, daddr
))
298 panic("Invalid PCI memory access to unmapped memory.\n");
300 // Only Memory register BAR is allowed
303 int size
= pkt
->getSize();
306 /// Handle write of register here
309 if (size
== sizeof(uint64_t)) {
310 uint64_t val M5_VAR_USED
= pkt
->get
<uint64_t>();
311 DPRINTF(DMACopyEngine
, "Wrote device register %#X value %#X\n", daddr
, val
);
312 } else if (size
== sizeof(uint32_t)) {
313 uint32_t val M5_VAR_USED
= pkt
->get
<uint32_t>();
314 DPRINTF(DMACopyEngine
, "Wrote device register %#X value %#X\n", daddr
, val
);
315 } else if (size
== sizeof(uint16_t)) {
316 uint16_t val M5_VAR_USED
= pkt
->get
<uint16_t>();
317 DPRINTF(DMACopyEngine
, "Wrote device register %#X value %#X\n", daddr
, val
);
318 } else if (size
== sizeof(uint8_t)) {
319 uint8_t val M5_VAR_USED
= pkt
->get
<uint8_t>();
320 DPRINTF(DMACopyEngine
, "Wrote device register %#X value %#X\n", daddr
, val
);
322 panic("Unknown size for MMIO access: %d\n", size
);
330 DPRINTF(DMACopyEngine
, "Warning, ignorning write to register %x\n",
334 regs
.intrctrl
.master_int_enable(bits(pkt
->get
<uint8_t>(),0,1));
337 panic("Read request to unknown register number: %#x\n", daddr
);
339 pkt
->makeAtomicResponse();
343 // Find which channel we're accessing
346 while (daddr
>= 0x80) {
351 if (chanid
>= regs
.chanCount
)
352 panic("Access to channel %d (device only configured for %d channels)",
353 chanid
, regs
.chanCount
);
356 /// Channel registers are handled here
358 chan
[chanid
]->channelWrite(pkt
, daddr
, size
);
360 pkt
->makeAtomicResponse();
365 CopyEngine::CopyEngineChannel::channelWrite(Packet
*pkt
, Addr daddr
, int size
)
369 assert(size
== sizeof(uint16_t));
371 old_int_disable
= cr
.ctrl
.interrupt_disable();
372 cr
.ctrl(pkt
->get
<uint16_t>());
373 if (cr
.ctrl
.interrupt_disable())
374 cr
.ctrl
.interrupt_disable(0);
376 cr
.ctrl
.interrupt_disable(old_int_disable
);
379 assert(size
== sizeof(uint64_t));
380 DPRINTF(DMACopyEngine
, "Warning, ignorning write to register %x\n",
384 assert(size
== sizeof(uint64_t) || size
== sizeof(uint32_t));
385 if (size
== sizeof(uint64_t))
386 cr
.descChainAddr
= pkt
->get
<uint64_t>();
388 cr
.descChainAddr
= (uint64_t)pkt
->get
<uint32_t>() |
389 (cr
.descChainAddr
& ~mask(32));
390 DPRINTF(DMACopyEngine
, "Chain Address %x\n", cr
.descChainAddr
);
392 case CHAN_CHAINADDR_HIGH
:
393 assert(size
== sizeof(uint32_t));
394 cr
.descChainAddr
= ((uint64_t)pkt
->get
<uint32_t>() <<32) |
395 (cr
.descChainAddr
& mask(32));
396 DPRINTF(DMACopyEngine
, "Chain Address %x\n", cr
.descChainAddr
);
399 assert(size
== sizeof(uint8_t));
400 cr
.command(pkt
->get
<uint8_t>());
404 assert(size
== sizeof(uint64_t) || size
== sizeof(uint32_t));
405 if (size
== sizeof(uint64_t))
406 cr
.completionAddr
= pkt
->get
<uint64_t>();
408 cr
.completionAddr
= pkt
->get
<uint32_t>() |
409 (cr
.completionAddr
& ~mask(32));
411 case CHAN_CMPLNADDR_HIGH
:
412 assert(size
== sizeof(uint32_t));
413 cr
.completionAddr
= ((uint64_t)pkt
->get
<uint32_t>() <<32) |
414 (cr
.completionAddr
& mask(32));
417 assert(size
== sizeof(uint32_t));
418 cr
.error(~pkt
->get
<uint32_t>() & cr
.error());
421 panic("Read request to unknown channel register number: (%d)%#x\n",
427 CopyEngine::regStats()
429 using namespace Stats
;
431 .init(regs
.chanCount
)
432 .name(name() + ".bytes_copied")
433 .desc("Number of bytes copied by each engine")
437 .init(regs
.chanCount
)
438 .name(name() + ".copies_processed")
439 .desc("Number of copies processed by each engine")
445 CopyEngine::CopyEngineChannel::fetchDescriptor(Addr address
)
448 anBegin("FetchDescriptor");
449 DPRINTF(DMACopyEngine
, "Reading descriptor from at memory location %#x(%#x)\n",
450 address
, ce
->platform
->pciToDma(address
));
454 DPRINTF(DMACopyEngine
, "dmaAction: %#x, %d bytes, to addr %#x\n",
455 ce
->platform
->pciToDma(address
), sizeof(DmaDesc
), curDmaDesc
);
457 cePort
.dmaAction(MemCmd::ReadReq
, ce
->platform
->pciToDma(address
),
458 sizeof(DmaDesc
), &fetchCompleteEvent
,
459 (uint8_t*)curDmaDesc
, latBeforeBegin
);
460 lastDescriptorAddr
= address
;
464 CopyEngine::CopyEngineChannel::fetchDescComplete()
466 DPRINTF(DMACopyEngine
, "Read of descriptor complete\n");
468 if ((curDmaDesc
->command
& DESC_CTRL_NULL
)) {
469 DPRINTF(DMACopyEngine
, "Got NULL descriptor, skipping\n");
470 assert(!(curDmaDesc
->command
& DESC_CTRL_CP_STS
));
471 if (curDmaDesc
->command
& DESC_CTRL_CP_STS
) {
472 panic("Shouldn't be able to get here\n");
473 nextState
= CompletionWrite
;
474 if (inDrain()) return;
475 writeCompletionStatus();
486 if (curDmaDesc
->command
& ~DESC_CTRL_CP_STS
)
487 panic("Descriptor has flag other that completion status set\n");
490 if (inDrain()) return;
495 CopyEngine::CopyEngineChannel::readCopyBytes()
497 anBegin("ReadCopyBytes");
498 DPRINTF(DMACopyEngine
, "Reading %d bytes from buffer to memory location %#x(%#x)\n",
499 curDmaDesc
->len
, curDmaDesc
->dest
,
500 ce
->platform
->pciToDma(curDmaDesc
->src
));
501 cePort
.dmaAction(MemCmd::ReadReq
, ce
->platform
->pciToDma(curDmaDesc
->src
),
502 curDmaDesc
->len
, &readCompleteEvent
, copyBuffer
, 0);
506 CopyEngine::CopyEngineChannel::readCopyBytesComplete()
508 DPRINTF(DMACopyEngine
, "Read of bytes to copy complete\n");
510 nextState
= DMAWrite
;
511 if (inDrain()) return;
516 CopyEngine::CopyEngineChannel::writeCopyBytes()
518 anBegin("WriteCopyBytes");
519 DPRINTF(DMACopyEngine
, "Writing %d bytes from buffer to memory location %#x(%#x)\n",
520 curDmaDesc
->len
, curDmaDesc
->dest
,
521 ce
->platform
->pciToDma(curDmaDesc
->dest
));
523 cePort
.dmaAction(MemCmd::WriteReq
, ce
->platform
->pciToDma(curDmaDesc
->dest
),
524 curDmaDesc
->len
, &writeCompleteEvent
, copyBuffer
, 0);
526 ce
->bytesCopied
[channelId
] += curDmaDesc
->len
;
527 ce
->copiesProcessed
[channelId
]++;
531 CopyEngine::CopyEngineChannel::writeCopyBytesComplete()
533 DPRINTF(DMACopyEngine
, "Write of bytes to copy complete user1: %#x\n",
536 cr
.status
.compl_desc_addr(lastDescriptorAddr
>> 6);
537 completionDataReg
= cr
.status() | 1;
539 anQ("DMAUsedDescQ", channelId
, 1);
540 anQ("AppRecvQ", curDmaDesc
->user1
, curDmaDesc
->len
);
541 if (curDmaDesc
->command
& DESC_CTRL_CP_STS
) {
542 nextState
= CompletionWrite
;
543 if (inDrain()) return;
544 writeCompletionStatus();
548 continueProcessing();
552 CopyEngine::CopyEngineChannel::continueProcessing()
566 if (curDmaDesc
->next
) {
567 nextState
= DescriptorFetch
;
568 fetchAddress
= curDmaDesc
->next
;
569 if (inDrain()) return;
570 fetchDescriptor(curDmaDesc
->next
);
571 } else if (refreshNext
) {
572 nextState
= AddressFetch
;
574 if (inDrain()) return;
575 fetchNextAddr(lastDescriptorAddr
);
585 CopyEngine::CopyEngineChannel::writeCompletionStatus()
587 anBegin("WriteCompletionStatus");
588 DPRINTF(DMACopyEngine
, "Writing completion status %#x to address %#x(%#x)\n",
589 completionDataReg
, cr
.completionAddr
,
590 ce
->platform
->pciToDma(cr
.completionAddr
));
592 cePort
.dmaAction(MemCmd::WriteReq
,
593 ce
->platform
->pciToDma(cr
.completionAddr
),
594 sizeof(completionDataReg
), &statusCompleteEvent
,
595 (uint8_t*)&completionDataReg
, latAfterCompletion
);
599 CopyEngine::CopyEngineChannel::writeStatusComplete()
601 DPRINTF(DMACopyEngine
, "Writing completion status complete\n");
602 continueProcessing();
606 CopyEngine::CopyEngineChannel::fetchNextAddr(Addr address
)
608 anBegin("FetchNextAddr");
609 DPRINTF(DMACopyEngine
, "Fetching next address...\n");
611 cePort
.dmaAction(MemCmd::ReadReq
,
612 ce
->platform
->pciToDma(address
+ offsetof(DmaDesc
, next
)),
613 sizeof(Addr
), &addrCompleteEvent
,
614 (uint8_t*)curDmaDesc
+ offsetof(DmaDesc
, next
), 0);
618 CopyEngine::CopyEngineChannel::fetchAddrComplete()
620 DPRINTF(DMACopyEngine
, "Fetching next address complete: %#x\n",
622 if (!curDmaDesc
->next
) {
623 DPRINTF(DMACopyEngine
, "Got NULL descriptor, nothing more to do\n");
631 nextState
= DescriptorFetch
;
632 fetchAddress
= curDmaDesc
->next
;
633 if (inDrain()) return;
634 fetchDescriptor(curDmaDesc
->next
);
638 CopyEngine::CopyEngineChannel::inDrain()
640 if (ce
->getState() == SimObject::Draining
) {
641 DPRINTF(Drain
, "CopyEngine done draining, processing drain event\n");
643 drainEvent
->process();
647 return ce
->getState() != SimObject::Running
;
651 CopyEngine::CopyEngineChannel::drain(Event
*de
)
653 if (nextState
== Idle
|| ce
->getState() != SimObject::Running
)
655 unsigned int count
= 1;
656 count
+= cePort
.drain(de
);
658 DPRINTF(Drain
, "CopyEngineChannel not drained\n");
664 CopyEngine::drain(Event
*de
)
667 count
= pioPort
.drain(de
) + dmaPort
.drain(de
) + configPort
.drain(de
);
668 for (int x
= 0;x
< chan
.size(); x
++)
669 count
+= chan
[x
]->drain(de
);
672 changeState(Draining
);
674 changeState(Drained
);
676 DPRINTF(Drain
, "CopyEngine not drained\n");
681 CopyEngine::serialize(std::ostream
&os
)
683 PciDev::serialize(os
);
685 for (int x
=0; x
< chan
.size(); x
++) {
686 nameOut(os
, csprintf("%s.channel%d", name(), x
));
687 chan
[x
]->serialize(os
);
692 CopyEngine::unserialize(Checkpoint
*cp
, const std::string
§ion
)
694 PciDev::unserialize(cp
, section
);
695 regs
.unserialize(cp
, section
);
696 for (int x
= 0; x
< chan
.size(); x
++)
697 chan
[x
]->unserialize(cp
, csprintf("%s.channel%d", section
, x
));
701 CopyEngine::CopyEngineChannel::serialize(std::ostream
&os
)
703 SERIALIZE_SCALAR(channelId
);
704 SERIALIZE_SCALAR(busy
);
705 SERIALIZE_SCALAR(underReset
);
706 SERIALIZE_SCALAR(refreshNext
);
707 SERIALIZE_SCALAR(lastDescriptorAddr
);
708 SERIALIZE_SCALAR(completionDataReg
);
709 SERIALIZE_SCALAR(fetchAddress
);
710 int nextState
= this->nextState
;
711 SERIALIZE_SCALAR(nextState
);
712 arrayParamOut(os
, "curDmaDesc", (uint8_t*)curDmaDesc
, sizeof(DmaDesc
));
713 SERIALIZE_ARRAY(copyBuffer
, ce
->params()->XferCap
);
718 CopyEngine::CopyEngineChannel::unserialize(Checkpoint
*cp
, const std::string
§ion
)
720 UNSERIALIZE_SCALAR(channelId
);
721 UNSERIALIZE_SCALAR(busy
);
722 UNSERIALIZE_SCALAR(underReset
);
723 UNSERIALIZE_SCALAR(refreshNext
);
724 UNSERIALIZE_SCALAR(lastDescriptorAddr
);
725 UNSERIALIZE_SCALAR(completionDataReg
);
726 UNSERIALIZE_SCALAR(fetchAddress
);
728 UNSERIALIZE_SCALAR(nextState
);
729 this->nextState
= (ChannelState
)nextState
;
730 arrayParamIn(cp
, section
, "curDmaDesc", (uint8_t*)curDmaDesc
, sizeof(DmaDesc
));
731 UNSERIALIZE_ARRAY(copyBuffer
, ce
->params()->XferCap
);
732 cr
.unserialize(cp
, section
);
737 CopyEngine::CopyEngineChannel::restartStateMachine()
741 fetchNextAddr(lastDescriptorAddr
);
743 case DescriptorFetch
:
744 fetchDescriptor(fetchAddress
);
752 case CompletionWrite
:
753 writeCompletionStatus();
758 panic("Unknown state for CopyEngineChannel\n");
766 for (int x
= 0;x
< chan
.size(); x
++)
772 CopyEngine::CopyEngineChannel::resume()
774 DPRINTF(DMACopyEngine
, "Restarting state machine at state %d\n", nextState
);
775 restartStateMachine();
779 CopyEngineParams::create()
781 return new CopyEngine(this);