src/dev/copy_engine.hh

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /* @file
  32  * Device model for Intel's I/O Acceleration Technology (I/OAT).
  33  * A DMA asyncronous copy engine
  34  */
  35
  36 #ifndef __DEV_COPY_ENGINE_HH__
  37 #define __DEV_COPY_ENGINE_HH__
  38
  39 #include <vector>
  40
  41 #include "base/statistics.hh"
  42 #include "dev/copy_engine_defs.hh"
  43 #include "dev/pcidev.hh"
  44 #include "params/CopyEngine.hh"
  45 #include "sim/eventq.hh"
  46
  47 class CopyEngine : public PciDev
  48 {
  49     class CopyEngineChannel
  50     {
  51       private:
  52         DmaPort *cePort;
  53         CopyEngine *ce;
  54         CopyEngineReg::ChanRegs  cr;
  55         int channelId;
  56         CopyEngineReg::DmaDesc *curDmaDesc;
  57         uint8_t *copyBuffer;
  58
  59         bool busy;
  60         bool underReset;
  61         bool refreshNext;
  62         Addr lastDescriptorAddr;
  63         Addr fetchAddress;
  64
  65         Tick latBeforeBegin;
  66         Tick latAfterCompletion;
  67
  68         uint64_t completionDataReg;
  69
  70         enum ChannelState {
  71             Idle,
  72             AddressFetch,
  73             DescriptorFetch,
  74             DMARead,
  75             DMAWrite,
  76             CompletionWrite
  77         };
  78
  79         ChannelState nextState;
  80
  81         Event *drainEvent;
  82       public:
  83         CopyEngineChannel(CopyEngine *_ce, int cid);
  84         virtual ~CopyEngineChannel();
  85         void init();
  86
  87         std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); }
  88         virtual Tick read(PacketPtr pkt)
  89                         { panic("CopyEngineChannel has no I/O access\n");}
  90         virtual Tick write(PacketPtr pkt)
  91                         { panic("CopyEngineChannel has no I/O access\n"); }
  92
  93         void channelRead(PacketPtr pkt, Addr daddr, int size);
  94         void channelWrite(PacketPtr pkt, Addr daddr, int size);
  95
  96         unsigned int drain(Event *de);
  97         void resume();
  98         void serialize(std::ostream &os);
  99         void unserialize(Checkpoint *cp, const std::string &section);
 100
 101       private:
 102         void fetchDescriptor(Addr address);
 103         void fetchDescComplete();
 104         EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchDescComplete>
 105             fetchCompleteEvent;
 106
 107         void fetchNextAddr(Addr address);
 108         void fetchAddrComplete();
 109         EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchAddrComplete>
 110             addrCompleteEvent;
 111
 112         void readCopyBytes();
 113         void readCopyBytesComplete();
 114         EventWrapper<CopyEngineChannel, &CopyEngineChannel::readCopyBytesComplete>
 115             readCompleteEvent;
 116
 117         void writeCopyBytes();
 118         void writeCopyBytesComplete();
 119         EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeCopyBytesComplete>
 120             writeCompleteEvent;
 121
 122         void writeCompletionStatus();
 123         void writeStatusComplete();
 124         EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeStatusComplete>
 125             statusCompleteEvent;
 126
 127
 128         void continueProcessing();
 129         void recvCommand();
 130         bool inDrain();
 131         void restartStateMachine();
 132         inline void anBegin(const char *s)
 133         {
 134             CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys,
 135                          channelId, "CopyEngine", s);
 136         }
 137
 138         inline void anWait()
 139         {
 140             CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys,
 141                      channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
 142         }
 143
 144         inline void anDq()
 145         {
 146             CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
 147                       channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
 148         }
 149
 150         inline void anPq()
 151         {
 152             CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
 153                       channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
 154         }
 155
 156         inline void anQ(const char * s, uint64_t id, int size = 1)
 157         {
 158             CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId,
 159                     "CopyEngine", s, id, NULL, size);
 160         }
 161
 162     };
 163
 164   private:
 165
 166     Stats::Vector bytesCopied;
 167     Stats::Vector copiesProcessed;
 168
 169     // device registers
 170     CopyEngineReg::Regs regs;
 171
 172     // Array of channels each one with regs/dma port/etc
 173     std::vector<CopyEngineChannel*> chan;
 174
 175   public:
 176     typedef CopyEngineParams Params;
 177     const Params *
 178     params() const
 179     {
 180         return dynamic_cast<const Params *>(_params);
 181     }
 182     CopyEngine(const Params *params);
 183     ~CopyEngine();
 184
 185     void regStats();
 186     void init();
 187
 188     virtual Tick read(PacketPtr pkt);
 189     virtual Tick write(PacketPtr pkt);
 190
 191     virtual void serialize(std::ostream &os);
 192     virtual void unserialize(Checkpoint *cp, const std::string &section);
 193     virtual unsigned int drain(Event *de);
 194     virtual void resume();
 195 };
 196
 197 #endif //__DEV_COPY_ENGINE_HH__
 198