src/dev/copy_engine.hh

   1 /*
   2  * Copyright (c) 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /* @file
  32  * Device model for Intel's I/O Acceleration Technology (I/OAT).
  33  * A DMA asyncronous copy engine
  34  */
  35
  36 #ifndef __DEV_COPY_ENGINE_HH__
  37 #define __DEV_COPY_ENGINE_HH__
  38
  39 #include <vector>
  40
  41 #include "base/statistics.hh"
  42 #include "dev/copy_engine_defs.hh"
  43 #include "dev/pcidev.hh"
  44 #include "params/CopyEngine.hh"
  45 #include "sim/eventq.hh"
  46
  47 class CopyEngine : public PciDev
  48 {
  49     class CopyEngineChannel
  50     {
  51       private:
  52         DmaPort *cePort;
  53         CopyEngine *ce;
  54         CopyEngineReg::ChanRegs  cr;
  55         int channelId;
  56         CopyEngineReg::DmaDesc *curDmaDesc;
  57         uint8_t *copyBuffer;
  58
  59         bool busy;
  60         bool underReset;
  61         bool refreshNext;
  62         Addr lastDescriptorAddr;
  63         Addr fetchAddress;
  64
  65         Tick latBeforeBegin;
  66         Tick latAfterCompletion;
  67
  68         uint64_t completionDataReg;
  69
  70         enum ChannelState {
  71             Idle,
  72             AddressFetch,
  73             DescriptorFetch,
  74             DMARead,
  75             DMAWrite,
  76             CompletionWrite
  77         };
  78
  79         ChannelState nextState;
  80
  81         Event *drainEvent;
  82       public:
  83         CopyEngineChannel(CopyEngine *_ce, int cid);
  84         virtual ~CopyEngineChannel();
  85         void init();
  86
  87         std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); }
  88         virtual void addressRanges(AddrRangeList &range_list) { range_list.clear(); }
  89         virtual Tick read(PacketPtr pkt)
  90                         { panic("CopyEngineChannel has no I/O access\n");}
  91         virtual Tick write(PacketPtr pkt)
  92                         { panic("CopyEngineChannel has no I/O access\n"); }
  93
  94         void channelRead(PacketPtr pkt, Addr daddr, int size);
  95         void channelWrite(PacketPtr pkt, Addr daddr, int size);
  96
  97         unsigned int drain(Event *de);
  98         void resume();
  99         void serialize(std::ostream &os);
 100         void unserialize(Checkpoint *cp, const std::string &section);
 101
 102       private:
 103         void fetchDescriptor(Addr address);
 104         void fetchDescComplete();
 105         EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchDescComplete>
 106             fetchCompleteEvent;
 107
 108         void fetchNextAddr(Addr address);
 109         void fetchAddrComplete();
 110         EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchAddrComplete>
 111             addrCompleteEvent;
 112
 113         void readCopyBytes();
 114         void readCopyBytesComplete();
 115         EventWrapper<CopyEngineChannel, &CopyEngineChannel::readCopyBytesComplete>
 116             readCompleteEvent;
 117
 118         void writeCopyBytes();
 119         void writeCopyBytesComplete();
 120         EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeCopyBytesComplete>
 121             writeCompleteEvent;
 122
 123         void writeCompletionStatus();
 124         void writeStatusComplete();
 125         EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeStatusComplete>
 126             statusCompleteEvent;
 127
 128
 129         void continueProcessing();
 130         void recvCommand();
 131         bool inDrain();
 132         void restartStateMachine();
 133         inline void anBegin(const char *s)
 134         {
 135             CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys,
 136                          channelId, "CopyEngine", s);
 137         }
 138
 139         inline void anWait()
 140         {
 141             CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys,
 142                      channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
 143         }
 144
 145         inline void anDq()
 146         {
 147             CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
 148                       channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
 149         }
 150
 151         inline void anPq()
 152         {
 153             CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
 154                       channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
 155         }
 156
 157         inline void anQ(const char * s, uint64_t id, int size = 1)
 158         {
 159             CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId,
 160                     "CopyEngine", s, id, NULL, size);
 161         }
 162
 163     };
 164
 165   private:
 166
 167     Stats::Vector bytesCopied;
 168     Stats::Vector copiesProcessed;
 169
 170     // device registers
 171     CopyEngineReg::Regs regs;
 172
 173     // Array of channels each one with regs/dma port/etc
 174     std::vector<CopyEngineChannel*> chan;
 175
 176   public:
 177     typedef CopyEngineParams Params;
 178     const Params *
 179     params() const
 180     {
 181         return dynamic_cast<const Params *>(_params);
 182     }
 183     CopyEngine(const Params *params);
 184     ~CopyEngine();
 185
 186     void regStats();
 187     void init();
 188
 189     virtual Tick read(PacketPtr pkt);
 190     virtual Tick write(PacketPtr pkt);
 191
 192     virtual void serialize(std::ostream &os);
 193     virtual void unserialize(Checkpoint *cp, const std::string &section);
 194     virtual unsigned int drain(Event *de);
 195     virtual void resume();
 196 };
 197
 198 #endif //__DEV_COPY_ENGINE_HH__
 199