2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2008 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 * Device model for Intel's I/O Acceleration Technology (I/OAT).
45 * A DMA asyncronous copy engine
48 #ifndef __DEV_COPY_ENGINE_HH__
49 #define __DEV_COPY_ENGINE_HH__
53 #include "base/cp_annotate.hh"
54 #include "base/statistics.hh"
55 #include "dev/copy_engine_defs.hh"
56 #include "dev/pcidev.hh"
57 #include "params/CopyEngine.hh"
58 #include "sim/drain.hh"
59 #include "sim/eventq.hh"
61 class CopyEngine : public PciDevice
63 class CopyEngineChannel : public Drainable, public Serializable
68 CopyEngineReg::ChanRegs cr;
70 CopyEngineReg::DmaDesc *curDmaDesc;
76 Addr lastDescriptorAddr;
80 Tick latAfterCompletion;
82 uint64_t completionDataReg;
93 ChannelState nextState;
95 DrainManager *drainManager;
97 CopyEngineChannel(CopyEngine *_ce, int cid);
98 virtual ~CopyEngineChannel();
99 BaseMasterPort &getMasterPort();
101 std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); }
102 virtual Tick read(PacketPtr pkt)
103 { panic("CopyEngineChannel has no I/O access\n");}
104 virtual Tick write(PacketPtr pkt)
105 { panic("CopyEngineChannel has no I/O access\n"); }
107 void channelRead(PacketPtr pkt, Addr daddr, int size);
108 void channelWrite(PacketPtr pkt, Addr daddr, int size);
110 unsigned int drain(DrainManager *drainManger);
113 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
114 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
117 void fetchDescriptor(Addr address);
118 void fetchDescComplete();
119 EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchDescComplete>
122 void fetchNextAddr(Addr address);
123 void fetchAddrComplete();
124 EventWrapper<CopyEngineChannel, &CopyEngineChannel::fetchAddrComplete>
127 void readCopyBytes();
128 void readCopyBytesComplete();
129 EventWrapper<CopyEngineChannel, &CopyEngineChannel::readCopyBytesComplete>
132 void writeCopyBytes();
133 void writeCopyBytesComplete();
134 EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeCopyBytesComplete>
137 void writeCompletionStatus();
138 void writeStatusComplete();
139 EventWrapper <CopyEngineChannel, &CopyEngineChannel::writeStatusComplete>
143 void continueProcessing();
146 void restartStateMachine();
147 inline void anBegin(const char *s)
149 CPA::cpa()->hwBegin(CPA::FL_NONE, ce->sys,
150 channelId, "CopyEngine", s);
155 CPA::cpa()->hwWe(CPA::FL_NONE, ce->sys,
156 channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
161 CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
162 channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
167 CPA::cpa()->hwDq(CPA::FL_NONE, ce->sys,
168 channelId, "CopyEngine", "DMAUnusedDescQ", channelId);
171 inline void anQ(const char * s, uint64_t id, int size = 1)
173 CPA::cpa()->hwQ(CPA::FL_NONE, ce->sys, channelId,
174 "CopyEngine", s, id, NULL, size);
181 Stats::Vector bytesCopied;
182 Stats::Vector copiesProcessed;
185 CopyEngineReg::Regs regs;
187 // Array of channels each one with regs/dma port/etc
188 std::vector<CopyEngineChannel*> chan;
191 typedef CopyEngineParams Params;
195 return dynamic_cast<const Params *>(_params);
197 CopyEngine(const Params *params);
202 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
203 PortID idx = InvalidPortID);
205 virtual Tick read(PacketPtr pkt);
206 virtual Tick write(PacketPtr pkt);
208 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
209 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
212 #endif //__DEV_COPY_ENGINE_HH__