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46 #include "dev/dma_device.hh"
50 #include "base/chunk_generator.hh"
51 #include "debug/DMA.hh"
52 #include "debug/Drain.hh"
53 #include "mem/port_proxy.hh"
54 #include "sim/clocked_object.hh"
55 #include "sim/system.hh"
57 DmaPort::DmaPort(ClockedObject
*dev
, System
*s
,
58 uint32_t sid
, uint32_t ssid
)
59 : MasterPort(dev
->name() + ".dma", dev
),
60 device(dev
), sys(s
), masterId(s
->getMasterId(dev
)),
61 sendEvent([this]{ sendDma(); }, dev
->name()),
62 pendingCount(0), inRetry(false),
68 DmaPort::handleResp(PacketPtr pkt
, Tick delay
)
70 // should always see a response with a sender state
71 assert(pkt
->isResponse());
73 // get the DMA sender state
74 DmaReqState
*state
= dynamic_cast<DmaReqState
*>(pkt
->senderState
);
77 DPRINTF(DMA
, "Received response %s for addr: %#x size: %d nb: %d," \
78 " tot: %d sched %d\n",
79 pkt
->cmdString(), pkt
->getAddr(), pkt
->req
->getSize(),
80 state
->numBytes
, state
->totBytes
,
81 state
->completionEvent
?
82 state
->completionEvent
->scheduled() : 0);
84 assert(pendingCount
!= 0);
87 // update the number of bytes received based on the request rather
88 // than the packet as the latter could be rounded up to line sizes
89 state
->numBytes
+= pkt
->req
->getSize();
90 assert(state
->totBytes
>= state
->numBytes
);
92 // if we have reached the total number of bytes for this DMA
93 // request, then signal the completion and delete the sate
94 if (state
->totBytes
== state
->numBytes
) {
95 if (state
->completionEvent
) {
96 delay
+= state
->delay
;
97 device
->schedule(state
->completionEvent
, curTick() + delay
);
105 // we might be drained at this point, if so signal the drain event
106 if (pendingCount
== 0)
111 DmaPort::recvTimingResp(PacketPtr pkt
)
113 // We shouldn't ever get a cacheable block in Modified state
114 assert(pkt
->req
->isUncacheable() ||
115 !(pkt
->cacheResponding() && !pkt
->hasSharers()));
122 DmaDevice::DmaDevice(const Params
*p
)
123 : PioDevice(p
), dmaPort(this, sys
, p
->sid
, p
->ssid
)
129 if (!dmaPort
.isConnected())
130 panic("DMA port of %s not connected to anything!", name());
137 if (pendingCount
== 0) {
138 return DrainState::Drained
;
140 DPRINTF(Drain
, "DmaPort not drained\n");
141 return DrainState::Draining
;
146 DmaPort::recvReqRetry()
148 assert(transmitList
.size());
153 DmaPort::dmaAction(Packet::Command cmd
, Addr addr
, int size
, Event
*event
,
154 uint8_t *data
, uint32_t sid
, uint32_t ssid
, Tick delay
,
157 // one DMA request sender state for every action, that is then
158 // split into many requests and packets based on the block size,
159 // i.e. cache line size
160 DmaReqState
*reqState
= new DmaReqState(event
, size
, delay
);
162 // (functionality added for Table Walker statistics)
163 // We're only interested in this when there will only be one request.
164 // For simplicity, we return the last request, which would also be
165 // the only request in that case.
166 RequestPtr req
= NULL
;
168 DPRINTF(DMA
, "Starting DMA for addr: %#x size: %d sched: %d\n", addr
, size
,
169 event
? event
->scheduled() : -1);
170 for (ChunkGenerator
gen(addr
, size
, sys
->cacheLineSize());
171 !gen
.done(); gen
.next()) {
173 req
= std::make_shared
<Request
>(
174 gen
.addr(), gen
.size(), flag
, masterId
);
176 req
->setStreamId(sid
);
177 req
->setSubStreamId(ssid
);
179 req
->taskId(ContextSwitchTaskId::DMA
);
180 PacketPtr pkt
= new Packet(req
, cmd
);
182 // Increment the data pointer on a write
184 pkt
->dataStatic(data
+ gen
.complete());
186 pkt
->senderState
= reqState
;
188 DPRINTF(DMA
, "--Queuing DMA for addr: %#x size: %d\n", gen
.addr(),
193 // in zero time also initiate the sending of the packets we have
194 // just created, for atomic this involves actually completing all
202 DmaPort::dmaAction(Packet::Command cmd
, Addr addr
, int size
, Event
*event
,
203 uint8_t *data
, Tick delay
, Request::Flags flag
)
205 return dmaAction(cmd
, addr
, size
, event
, data
,
206 defaultSid
, defaultSSid
, delay
, flag
);
210 DmaPort::queueDma(PacketPtr pkt
)
212 transmitList
.push_back(pkt
);
214 // remember that we have another packet pending, this will only be
215 // decremented once a response comes back
220 DmaPort::trySendTimingReq()
222 // send the first packet on the transmit list and schedule the
223 // following send if it is successful
224 PacketPtr pkt
= transmitList
.front();
226 DPRINTF(DMA
, "Trying to send %s addr %#x\n", pkt
->cmdString(),
229 inRetry
= !sendTimingReq(pkt
);
231 transmitList
.pop_front();
232 DPRINTF(DMA
, "-- Done\n");
233 // if there is more to do, then do so
234 if (!transmitList
.empty())
235 // this should ultimately wait for as many cycles as the
236 // device needs to send the packet, but currently the port
237 // does not have any known width so simply wait a single
239 device
->schedule(sendEvent
, device
->clockEdge(Cycles(1)));
241 DPRINTF(DMA
, "-- Failed, waiting for retry\n");
244 DPRINTF(DMA
, "TransmitList: %d, inRetry: %d\n",
245 transmitList
.size(), inRetry
);
251 // some kind of selcetion between access methods
252 // more work is going to have to be done to make
253 // switching actually work
254 assert(transmitList
.size());
256 if (sys
->isTimingMode()) {
257 // if we are either waiting for a retry or are still waiting
258 // after sending the last packet, then do not proceed
259 if (inRetry
|| sendEvent
.scheduled()) {
260 DPRINTF(DMA
, "Can't send immediately, waiting to send\n");
265 } else if (sys
->isAtomicMode()) {
266 // send everything there is to send in zero time
267 while (!transmitList
.empty()) {
268 PacketPtr pkt
= transmitList
.front();
269 transmitList
.pop_front();
271 DPRINTF(DMA
, "Sending DMA for addr: %#x size: %d\n",
272 pkt
->req
->getPaddr(), pkt
->req
->getSize());
273 Tick lat
= sendAtomic(pkt
);
275 handleResp(pkt
, lat
);
278 panic("Unknown memory mode.");
282 DmaDevice::getPort(const std::string
&if_name
, PortID idx
)
284 if (if_name
== "dma") {
287 return PioDevice::getPort(if_name
, idx
);
290 DmaReadFifo::DmaReadFifo(DmaPort
&_port
, size_t size
,
291 unsigned max_req_size
,
292 unsigned max_pending
,
293 Request::Flags flags
)
294 : maxReqSize(max_req_size
), fifoSize(size
),
295 reqFlags(flags
), port(_port
),
297 nextAddr(0), endAddr(0)
299 freeRequests
.resize(max_pending
);
300 for (auto &e
: freeRequests
)
301 e
.reset(new DmaDoneEvent(this, max_req_size
));
305 DmaReadFifo::~DmaReadFifo()
307 for (auto &p
: pendingRequests
) {
308 DmaDoneEvent
*e(p
.release());
313 // We can't kill in-flight DMAs, so we'll just transfer
314 // ownership to the event queue so that they get freed
315 // when they are done.
322 DmaReadFifo::serialize(CheckpointOut
&cp
) const
324 assert(pendingRequests
.empty());
326 SERIALIZE_CONTAINER(buffer
);
327 SERIALIZE_SCALAR(endAddr
);
328 SERIALIZE_SCALAR(nextAddr
);
332 DmaReadFifo::unserialize(CheckpointIn
&cp
)
334 UNSERIALIZE_CONTAINER(buffer
);
335 UNSERIALIZE_SCALAR(endAddr
);
336 UNSERIALIZE_SCALAR(nextAddr
);
340 DmaReadFifo::tryGet(uint8_t *dst
, size_t len
)
342 if (buffer
.size() >= len
) {
343 buffer
.read(dst
, len
);
352 DmaReadFifo::get(uint8_t *dst
, size_t len
)
354 const bool success(tryGet(dst
, len
));
355 panic_if(!success
, "Buffer underrun in DmaReadFifo::get()\n");
359 DmaReadFifo::startFill(Addr start
, size_t size
)
361 assert(atEndOfBlock());
364 endAddr
= start
+ size
;
369 DmaReadFifo::stopFill()
371 // Prevent new DMA requests by setting the next address to the end
372 // address. Pending requests will still complete.
375 // Flag in-flight accesses as canceled. This prevents their data
376 // from being written to the FIFO.
377 for (auto &p
: pendingRequests
)
382 DmaReadFifo::resumeFill()
384 // Don't try to fetch more data if we are draining. This ensures
385 // that the DMA engine settles down before we checkpoint it.
386 if (drainState() == DrainState::Draining
)
389 const bool old_eob(atEndOfBlock());
391 if (port
.sys
->bypassCaches())
392 resumeFillFunctional();
396 if (!old_eob
&& atEndOfBlock())
401 DmaReadFifo::resumeFillFunctional()
403 const size_t fifo_space
= buffer
.capacity() - buffer
.size();
404 const size_t kvm_watermark
= port
.sys
->cacheLineSize();
405 if (fifo_space
>= kvm_watermark
|| buffer
.capacity() < kvm_watermark
) {
406 const size_t block_remaining
= endAddr
- nextAddr
;
407 const size_t xfer_size
= std::min(fifo_space
, block_remaining
);
408 std::vector
<uint8_t> tmp_buffer(xfer_size
);
410 assert(pendingRequests
.empty());
411 DPRINTF(DMA
, "KVM Bypassing startAddr=%#x xfer_size=%#x " \
412 "fifo_space=%#x block_remaining=%#x\n",
413 nextAddr
, xfer_size
, fifo_space
, block_remaining
);
415 port
.sys
->physProxy
.readBlob(nextAddr
, tmp_buffer
.data(), xfer_size
);
416 buffer
.write(tmp_buffer
.begin(), xfer_size
);
417 nextAddr
+= xfer_size
;
422 DmaReadFifo::resumeFillTiming()
424 size_t size_pending(0);
425 for (auto &e
: pendingRequests
)
426 size_pending
+= e
->requestSize();
428 while (!freeRequests
.empty() && !atEndOfBlock()) {
429 const size_t req_size(std::min(maxReqSize
, endAddr
- nextAddr
));
430 if (buffer
.size() + size_pending
+ req_size
> fifoSize
)
433 DmaDoneEventUPtr
event(std::move(freeRequests
.front()));
434 freeRequests
.pop_front();
437 event
->reset(req_size
);
438 port
.dmaAction(MemCmd::ReadReq
, nextAddr
, req_size
, event
.get(),
439 event
->data(), 0, reqFlags
);
440 nextAddr
+= req_size
;
441 size_pending
+= req_size
;
443 pendingRequests
.emplace_back(std::move(event
));
448 DmaReadFifo::dmaDone()
450 const bool old_active(isActive());
455 if (old_active
&& !isActive())
460 DmaReadFifo::handlePending()
462 while (!pendingRequests
.empty() && pendingRequests
.front()->done()) {
463 // Get the first finished pending request
464 DmaDoneEventUPtr
event(std::move(pendingRequests
.front()));
465 pendingRequests
.pop_front();
467 if (!event
->canceled())
468 buffer
.write(event
->data(), event
->requestSize());
470 // Move the event to the list of free requests
471 freeRequests
.emplace_back(std::move(event
));
474 if (pendingRequests
.empty())
481 return pendingRequests
.empty() ? DrainState::Drained
: DrainState::Draining
;
485 DmaReadFifo::DmaDoneEvent::DmaDoneEvent(DmaReadFifo
*_parent
,
487 : parent(_parent
), _done(false), _canceled(false), _data(max_size
, 0)
492 DmaReadFifo::DmaDoneEvent::kill()
495 setFlags(AutoDelete
);
499 DmaReadFifo::DmaDoneEvent::cancel()
505 DmaReadFifo::DmaDoneEvent::reset(size_t size
)
507 assert(size
<= _data
.size());
514 DmaReadFifo::DmaDoneEvent::process()