327c92436c95060d723d0b14a7303c870485fd92
2 * Copyright (c) 2012, 2015, 2017 ARM Limited
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14 * Copyright (c) 2006 The Regents of The University of Michigan
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46 #include "dev/dma_device.hh"
50 #include "base/chunk_generator.hh"
51 #include "debug/DMA.hh"
52 #include "debug/Drain.hh"
53 #include "mem/port_proxy.hh"
54 #include "sim/clocked_object.hh"
55 #include "sim/system.hh"
57 DmaPort::DmaPort(ClockedObject
*dev
, System
*s
)
58 : MasterPort(dev
->name() + ".dma", dev
),
59 device(dev
), sys(s
), masterId(s
->getMasterId(dev
)),
60 sendEvent([this]{ sendDma(); }, dev
->name()),
61 pendingCount(0), inRetry(false)
65 DmaPort::handleResp(PacketPtr pkt
, Tick delay
)
67 // should always see a response with a sender state
68 assert(pkt
->isResponse());
70 // get the DMA sender state
71 DmaReqState
*state
= dynamic_cast<DmaReqState
*>(pkt
->senderState
);
74 DPRINTF(DMA
, "Received response %s for addr: %#x size: %d nb: %d," \
75 " tot: %d sched %d\n",
76 pkt
->cmdString(), pkt
->getAddr(), pkt
->req
->getSize(),
77 state
->numBytes
, state
->totBytes
,
78 state
->completionEvent
?
79 state
->completionEvent
->scheduled() : 0);
81 assert(pendingCount
!= 0);
84 // update the number of bytes received based on the request rather
85 // than the packet as the latter could be rounded up to line sizes
86 state
->numBytes
+= pkt
->req
->getSize();
87 assert(state
->totBytes
>= state
->numBytes
);
89 // if we have reached the total number of bytes for this DMA
90 // request, then signal the completion and delete the sate
91 if (state
->totBytes
== state
->numBytes
) {
92 if (state
->completionEvent
) {
93 delay
+= state
->delay
;
94 device
->schedule(state
->completionEvent
, curTick() + delay
);
102 // we might be drained at this point, if so signal the drain event
103 if (pendingCount
== 0)
108 DmaPort::recvTimingResp(PacketPtr pkt
)
110 // We shouldn't ever get a cacheable block in Modified state
111 assert(pkt
->req
->isUncacheable() ||
112 !(pkt
->cacheResponding() && !pkt
->hasSharers()));
119 DmaDevice::DmaDevice(const Params
*p
)
120 : PioDevice(p
), dmaPort(this, sys
)
126 if (!dmaPort
.isConnected())
127 panic("DMA port of %s not connected to anything!", name());
134 if (pendingCount
== 0) {
135 return DrainState::Drained
;
137 DPRINTF(Drain
, "DmaPort not drained\n");
138 return DrainState::Draining
;
143 DmaPort::recvReqRetry()
145 assert(transmitList
.size());
150 DmaPort::dmaAction(Packet::Command cmd
, Addr addr
, int size
, Event
*event
,
151 uint8_t *data
, Tick delay
, Request::Flags flag
)
153 // one DMA request sender state for every action, that is then
154 // split into many requests and packets based on the block size,
155 // i.e. cache line size
156 DmaReqState
*reqState
= new DmaReqState(event
, size
, delay
);
158 // (functionality added for Table Walker statistics)
159 // We're only interested in this when there will only be one request.
160 // For simplicity, we return the last request, which would also be
161 // the only request in that case.
162 RequestPtr req
= NULL
;
164 DPRINTF(DMA
, "Starting DMA for addr: %#x size: %d sched: %d\n", addr
, size
,
165 event
? event
->scheduled() : -1);
166 for (ChunkGenerator
gen(addr
, size
, sys
->cacheLineSize());
167 !gen
.done(); gen
.next()) {
169 req
= std::make_shared
<Request
>(
170 gen
.addr(), gen
.size(), flag
, masterId
);
172 req
->taskId(ContextSwitchTaskId::DMA
);
173 PacketPtr pkt
= new Packet(req
, cmd
);
175 // Increment the data pointer on a write
177 pkt
->dataStatic(data
+ gen
.complete());
179 pkt
->senderState
= reqState
;
181 DPRINTF(DMA
, "--Queuing DMA for addr: %#x size: %d\n", gen
.addr(),
186 // in zero time also initiate the sending of the packets we have
187 // just created, for atomic this involves actually completing all
195 DmaPort::queueDma(PacketPtr pkt
)
197 transmitList
.push_back(pkt
);
199 // remember that we have another packet pending, this will only be
200 // decremented once a response comes back
205 DmaPort::trySendTimingReq()
207 // send the first packet on the transmit list and schedule the
208 // following send if it is successful
209 PacketPtr pkt
= transmitList
.front();
211 DPRINTF(DMA
, "Trying to send %s addr %#x\n", pkt
->cmdString(),
214 inRetry
= !sendTimingReq(pkt
);
216 transmitList
.pop_front();
217 DPRINTF(DMA
, "-- Done\n");
218 // if there is more to do, then do so
219 if (!transmitList
.empty())
220 // this should ultimately wait for as many cycles as the
221 // device needs to send the packet, but currently the port
222 // does not have any known width so simply wait a single
224 device
->schedule(sendEvent
, device
->clockEdge(Cycles(1)));
226 DPRINTF(DMA
, "-- Failed, waiting for retry\n");
229 DPRINTF(DMA
, "TransmitList: %d, inRetry: %d\n",
230 transmitList
.size(), inRetry
);
236 // some kind of selcetion between access methods
237 // more work is going to have to be done to make
238 // switching actually work
239 assert(transmitList
.size());
241 if (sys
->isTimingMode()) {
242 // if we are either waiting for a retry or are still waiting
243 // after sending the last packet, then do not proceed
244 if (inRetry
|| sendEvent
.scheduled()) {
245 DPRINTF(DMA
, "Can't send immediately, waiting to send\n");
250 } else if (sys
->isAtomicMode()) {
251 // send everything there is to send in zero time
252 while (!transmitList
.empty()) {
253 PacketPtr pkt
= transmitList
.front();
254 transmitList
.pop_front();
256 DPRINTF(DMA
, "Sending DMA for addr: %#x size: %d\n",
257 pkt
->req
->getPaddr(), pkt
->req
->getSize());
258 Tick lat
= sendAtomic(pkt
);
260 handleResp(pkt
, lat
);
263 panic("Unknown memory mode.");
267 DmaDevice::getPort(const std::string
&if_name
, PortID idx
)
269 if (if_name
== "dma") {
272 return PioDevice::getPort(if_name
, idx
);
279 DmaReadFifo::DmaReadFifo(DmaPort
&_port
, size_t size
,
280 unsigned max_req_size
,
281 unsigned max_pending
,
282 Request::Flags flags
)
283 : maxReqSize(max_req_size
), fifoSize(size
),
284 reqFlags(flags
), port(_port
),
286 nextAddr(0), endAddr(0)
288 freeRequests
.resize(max_pending
);
289 for (auto &e
: freeRequests
)
290 e
.reset(new DmaDoneEvent(this, max_req_size
));
294 DmaReadFifo::~DmaReadFifo()
296 for (auto &p
: pendingRequests
) {
297 DmaDoneEvent
*e(p
.release());
302 // We can't kill in-flight DMAs, so we'll just transfer
303 // ownership to the event queue so that they get freed
304 // when they are done.
311 DmaReadFifo::serialize(CheckpointOut
&cp
) const
313 assert(pendingRequests
.empty());
315 SERIALIZE_CONTAINER(buffer
);
316 SERIALIZE_SCALAR(endAddr
);
317 SERIALIZE_SCALAR(nextAddr
);
321 DmaReadFifo::unserialize(CheckpointIn
&cp
)
323 UNSERIALIZE_CONTAINER(buffer
);
324 UNSERIALIZE_SCALAR(endAddr
);
325 UNSERIALIZE_SCALAR(nextAddr
);
329 DmaReadFifo::tryGet(uint8_t *dst
, size_t len
)
331 if (buffer
.size() >= len
) {
332 buffer
.read(dst
, len
);
341 DmaReadFifo::get(uint8_t *dst
, size_t len
)
343 const bool success(tryGet(dst
, len
));
344 panic_if(!success
, "Buffer underrun in DmaReadFifo::get()\n");
348 DmaReadFifo::startFill(Addr start
, size_t size
)
350 assert(atEndOfBlock());
353 endAddr
= start
+ size
;
358 DmaReadFifo::stopFill()
360 // Prevent new DMA requests by setting the next address to the end
361 // address. Pending requests will still complete.
364 // Flag in-flight accesses as canceled. This prevents their data
365 // from being written to the FIFO.
366 for (auto &p
: pendingRequests
)
371 DmaReadFifo::resumeFill()
373 // Don't try to fetch more data if we are draining. This ensures
374 // that the DMA engine settles down before we checkpoint it.
375 if (drainState() == DrainState::Draining
)
378 const bool old_eob(atEndOfBlock());
380 if (port
.sys
->bypassCaches())
381 resumeFillFunctional();
385 if (!old_eob
&& atEndOfBlock())
390 DmaReadFifo::resumeFillFunctional()
392 const size_t fifo_space
= buffer
.capacity() - buffer
.size();
393 const size_t kvm_watermark
= port
.sys
->cacheLineSize();
394 if (fifo_space
>= kvm_watermark
|| buffer
.capacity() < kvm_watermark
) {
395 const size_t block_remaining
= endAddr
- nextAddr
;
396 const size_t xfer_size
= std::min(fifo_space
, block_remaining
);
397 std::vector
<uint8_t> tmp_buffer(xfer_size
);
399 assert(pendingRequests
.empty());
400 DPRINTF(DMA
, "KVM Bypassing startAddr=%#x xfer_size=%#x " \
401 "fifo_space=%#x block_remaining=%#x\n",
402 nextAddr
, xfer_size
, fifo_space
, block_remaining
);
404 port
.sys
->physProxy
.readBlob(nextAddr
, tmp_buffer
.data(), xfer_size
);
405 buffer
.write(tmp_buffer
.begin(), xfer_size
);
406 nextAddr
+= xfer_size
;
411 DmaReadFifo::resumeFillTiming()
413 size_t size_pending(0);
414 for (auto &e
: pendingRequests
)
415 size_pending
+= e
->requestSize();
417 while (!freeRequests
.empty() && !atEndOfBlock()) {
418 const size_t req_size(std::min(maxReqSize
, endAddr
- nextAddr
));
419 if (buffer
.size() + size_pending
+ req_size
> fifoSize
)
422 DmaDoneEventUPtr
event(std::move(freeRequests
.front()));
423 freeRequests
.pop_front();
426 event
->reset(req_size
);
427 port
.dmaAction(MemCmd::ReadReq
, nextAddr
, req_size
, event
.get(),
428 event
->data(), 0, reqFlags
);
429 nextAddr
+= req_size
;
430 size_pending
+= req_size
;
432 pendingRequests
.emplace_back(std::move(event
));
437 DmaReadFifo::dmaDone()
439 const bool old_active(isActive());
444 if (old_active
&& !isActive())
449 DmaReadFifo::handlePending()
451 while (!pendingRequests
.empty() && pendingRequests
.front()->done()) {
452 // Get the first finished pending request
453 DmaDoneEventUPtr
event(std::move(pendingRequests
.front()));
454 pendingRequests
.pop_front();
456 if (!event
->canceled())
457 buffer
.write(event
->data(), event
->requestSize());
459 // Move the event to the list of free requests
460 freeRequests
.emplace_back(std::move(event
));
463 if (pendingRequests
.empty())
470 return pendingRequests
.empty() ? DrainState::Drained
: DrainState::Draining
;
474 DmaReadFifo::DmaDoneEvent::DmaDoneEvent(DmaReadFifo
*_parent
,
476 : parent(_parent
), _done(false), _canceled(false), _data(max_size
, 0)
481 DmaReadFifo::DmaDoneEvent::kill()
484 setFlags(AutoDelete
);
488 DmaReadFifo::DmaDoneEvent::cancel()
494 DmaReadFifo::DmaDoneEvent::reset(size_t size
)
496 assert(size
<= _data
.size());
503 DmaReadFifo::DmaDoneEvent::process()