a78819a3e1870a45fce3133c5936dbd228079ab3
2 * Copyright (c) 2012, 2015, 2017 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
46 #include "dev/dma_device.hh"
50 #include "base/chunk_generator.hh"
51 #include "debug/DMA.hh"
52 #include "debug/Drain.hh"
53 #include "mem/port_proxy.hh"
54 #include "sim/system.hh"
56 DmaPort::DmaPort(MemObject
*dev
, System
*s
)
57 : MasterPort(dev
->name() + ".dma", dev
),
58 device(dev
), sys(s
), masterId(s
->getMasterId(dev
->name())),
59 sendEvent([this]{ sendDma(); }, dev
->name()),
60 pendingCount(0), inRetry(false)
64 DmaPort::handleResp(PacketPtr pkt
, Tick delay
)
66 // should always see a response with a sender state
67 assert(pkt
->isResponse());
69 // get the DMA sender state
70 DmaReqState
*state
= dynamic_cast<DmaReqState
*>(pkt
->senderState
);
73 DPRINTF(DMA
, "Received response %s for addr: %#x size: %d nb: %d," \
74 " tot: %d sched %d\n",
75 pkt
->cmdString(), pkt
->getAddr(), pkt
->req
->getSize(),
76 state
->numBytes
, state
->totBytes
,
77 state
->completionEvent
?
78 state
->completionEvent
->scheduled() : 0);
80 assert(pendingCount
!= 0);
83 // update the number of bytes received based on the request rather
84 // than the packet as the latter could be rounded up to line sizes
85 state
->numBytes
+= pkt
->req
->getSize();
86 assert(state
->totBytes
>= state
->numBytes
);
88 // if we have reached the total number of bytes for this DMA
89 // request, then signal the completion and delete the sate
90 if (state
->totBytes
== state
->numBytes
) {
91 if (state
->completionEvent
) {
92 delay
+= state
->delay
;
93 device
->schedule(state
->completionEvent
, curTick() + delay
);
98 // delete the request that we created and also the packet
102 // we might be drained at this point, if so signal the drain event
103 if (pendingCount
== 0)
108 DmaPort::recvTimingResp(PacketPtr pkt
)
110 // We shouldn't ever get a cacheable block in Modified state
111 assert(pkt
->req
->isUncacheable() ||
112 !(pkt
->cacheResponding() && !pkt
->hasSharers()));
119 DmaDevice::DmaDevice(const Params
*p
)
120 : PioDevice(p
), dmaPort(this, sys
)
126 if (!dmaPort
.isConnected())
127 panic("DMA port of %s not connected to anything!", name());
134 if (pendingCount
== 0) {
135 return DrainState::Drained
;
137 DPRINTF(Drain
, "DmaPort not drained\n");
138 return DrainState::Draining
;
143 DmaPort::recvReqRetry()
145 assert(transmitList
.size());
150 DmaPort::dmaAction(Packet::Command cmd
, Addr addr
, int size
, Event
*event
,
151 uint8_t *data
, Tick delay
, Request::Flags flag
)
153 // one DMA request sender state for every action, that is then
154 // split into many requests and packets based on the block size,
155 // i.e. cache line size
156 DmaReqState
*reqState
= new DmaReqState(event
, size
, delay
);
158 // (functionality added for Table Walker statistics)
159 // We're only interested in this when there will only be one request.
160 // For simplicity, we return the last request, which would also be
161 // the only request in that case.
162 RequestPtr req
= NULL
;
164 DPRINTF(DMA
, "Starting DMA for addr: %#x size: %d sched: %d\n", addr
, size
,
165 event
? event
->scheduled() : -1);
166 for (ChunkGenerator
gen(addr
, size
, sys
->cacheLineSize());
167 !gen
.done(); gen
.next()) {
168 req
= new Request(gen
.addr(), gen
.size(), flag
, masterId
);
169 req
->taskId(ContextSwitchTaskId::DMA
);
170 PacketPtr pkt
= new Packet(req
, cmd
);
172 // Increment the data pointer on a write
174 pkt
->dataStatic(data
+ gen
.complete());
176 pkt
->senderState
= reqState
;
178 DPRINTF(DMA
, "--Queuing DMA for addr: %#x size: %d\n", gen
.addr(),
183 // in zero time also initiate the sending of the packets we have
184 // just created, for atomic this involves actually completing all
192 DmaPort::queueDma(PacketPtr pkt
)
194 transmitList
.push_back(pkt
);
196 // remember that we have another packet pending, this will only be
197 // decremented once a response comes back
202 DmaPort::trySendTimingReq()
204 // send the first packet on the transmit list and schedule the
205 // following send if it is successful
206 PacketPtr pkt
= transmitList
.front();
208 DPRINTF(DMA
, "Trying to send %s addr %#x\n", pkt
->cmdString(),
211 inRetry
= !sendTimingReq(pkt
);
213 transmitList
.pop_front();
214 DPRINTF(DMA
, "-- Done\n");
215 // if there is more to do, then do so
216 if (!transmitList
.empty())
217 // this should ultimately wait for as many cycles as the
218 // device needs to send the packet, but currently the port
219 // does not have any known width so simply wait a single
221 device
->schedule(sendEvent
, device
->clockEdge(Cycles(1)));
223 DPRINTF(DMA
, "-- Failed, waiting for retry\n");
226 DPRINTF(DMA
, "TransmitList: %d, inRetry: %d\n",
227 transmitList
.size(), inRetry
);
233 // some kind of selcetion between access methods
234 // more work is going to have to be done to make
235 // switching actually work
236 assert(transmitList
.size());
238 if (sys
->isTimingMode()) {
239 // if we are either waiting for a retry or are still waiting
240 // after sending the last packet, then do not proceed
241 if (inRetry
|| sendEvent
.scheduled()) {
242 DPRINTF(DMA
, "Can't send immediately, waiting to send\n");
247 } else if (sys
->isAtomicMode()) {
248 // send everything there is to send in zero time
249 while (!transmitList
.empty()) {
250 PacketPtr pkt
= transmitList
.front();
251 transmitList
.pop_front();
253 DPRINTF(DMA
, "Sending DMA for addr: %#x size: %d\n",
254 pkt
->req
->getPaddr(), pkt
->req
->getSize());
255 Tick lat
= sendAtomic(pkt
);
257 handleResp(pkt
, lat
);
260 panic("Unknown memory mode.");
264 DmaDevice::getMasterPort(const std::string
&if_name
, PortID idx
)
266 if (if_name
== "dma") {
269 return PioDevice::getMasterPort(if_name
, idx
);
276 DmaReadFifo::DmaReadFifo(DmaPort
&_port
, size_t size
,
277 unsigned max_req_size
,
278 unsigned max_pending
,
279 Request::Flags flags
)
280 : maxReqSize(max_req_size
), fifoSize(size
),
281 reqFlags(flags
), port(_port
),
283 nextAddr(0), endAddr(0)
285 freeRequests
.resize(max_pending
);
286 for (auto &e
: freeRequests
)
287 e
.reset(new DmaDoneEvent(this, max_req_size
));
291 DmaReadFifo::~DmaReadFifo()
293 for (auto &p
: pendingRequests
) {
294 DmaDoneEvent
*e(p
.release());
299 // We can't kill in-flight DMAs, so we'll just transfer
300 // ownership to the event queue so that they get freed
301 // when they are done.
308 DmaReadFifo::serialize(CheckpointOut
&cp
) const
310 assert(pendingRequests
.empty());
312 SERIALIZE_CONTAINER(buffer
);
313 SERIALIZE_SCALAR(endAddr
);
314 SERIALIZE_SCALAR(nextAddr
);
318 DmaReadFifo::unserialize(CheckpointIn
&cp
)
320 UNSERIALIZE_CONTAINER(buffer
);
321 UNSERIALIZE_SCALAR(endAddr
);
322 UNSERIALIZE_SCALAR(nextAddr
);
326 DmaReadFifo::tryGet(uint8_t *dst
, size_t len
)
328 if (buffer
.size() >= len
) {
329 buffer
.read(dst
, len
);
338 DmaReadFifo::get(uint8_t *dst
, size_t len
)
340 const bool success(tryGet(dst
, len
));
341 panic_if(!success
, "Buffer underrun in DmaReadFifo::get()\n");
345 DmaReadFifo::startFill(Addr start
, size_t size
)
347 assert(atEndOfBlock());
350 endAddr
= start
+ size
;
355 DmaReadFifo::stopFill()
357 // Prevent new DMA requests by setting the next address to the end
358 // address. Pending requests will still complete.
361 // Flag in-flight accesses as canceled. This prevents their data
362 // from being written to the FIFO.
363 for (auto &p
: pendingRequests
)
368 DmaReadFifo::resumeFill()
370 // Don't try to fetch more data if we are draining. This ensures
371 // that the DMA engine settles down before we checkpoint it.
372 if (drainState() == DrainState::Draining
)
375 const bool old_eob(atEndOfBlock());
377 if (port
.sys
->bypassCaches())
378 resumeFillFunctional();
382 if (!old_eob
&& atEndOfBlock())
387 DmaReadFifo::resumeFillFunctional()
389 const size_t fifo_space
= buffer
.capacity() - buffer
.size();
390 const size_t kvm_watermark
= port
.sys
->cacheLineSize();
391 if (fifo_space
>= kvm_watermark
|| buffer
.capacity() < kvm_watermark
) {
392 const size_t block_remaining
= endAddr
- nextAddr
;
393 const size_t xfer_size
= std::min(fifo_space
, block_remaining
);
394 std::vector
<uint8_t> tmp_buffer(xfer_size
);
396 assert(pendingRequests
.empty());
397 DPRINTF(DMA
, "KVM Bypassing startAddr=%#x xfer_size=%#x " \
398 "fifo_space=%#x block_remaining=%#x\n",
399 nextAddr
, xfer_size
, fifo_space
, block_remaining
);
401 port
.sys
->physProxy
.readBlob(nextAddr
, tmp_buffer
.data(), xfer_size
);
402 buffer
.write(tmp_buffer
.begin(), xfer_size
);
403 nextAddr
+= xfer_size
;
408 DmaReadFifo::resumeFillTiming()
410 size_t size_pending(0);
411 for (auto &e
: pendingRequests
)
412 size_pending
+= e
->requestSize();
414 while (!freeRequests
.empty() && !atEndOfBlock()) {
415 const size_t req_size(std::min(maxReqSize
, endAddr
- nextAddr
));
416 if (buffer
.size() + size_pending
+ req_size
> fifoSize
)
419 DmaDoneEventUPtr
event(std::move(freeRequests
.front()));
420 freeRequests
.pop_front();
423 event
->reset(req_size
);
424 port
.dmaAction(MemCmd::ReadReq
, nextAddr
, req_size
, event
.get(),
425 event
->data(), 0, reqFlags
);
426 nextAddr
+= req_size
;
427 size_pending
+= req_size
;
429 pendingRequests
.emplace_back(std::move(event
));
434 DmaReadFifo::dmaDone()
436 const bool old_active(isActive());
441 if (!old_active
&& isActive())
446 DmaReadFifo::handlePending()
448 while (!pendingRequests
.empty() && pendingRequests
.front()->done()) {
449 // Get the first finished pending request
450 DmaDoneEventUPtr
event(std::move(pendingRequests
.front()));
451 pendingRequests
.pop_front();
453 if (!event
->canceled())
454 buffer
.write(event
->data(), event
->requestSize());
456 // Move the event to the list of free requests
457 freeRequests
.emplace_back(std::move(event
));
460 if (pendingRequests
.empty())
467 return pendingRequests
.empty() ? DrainState::Drained
: DrainState::Draining
;
471 DmaReadFifo::DmaDoneEvent::DmaDoneEvent(DmaReadFifo
*_parent
,
473 : parent(_parent
), _done(false), _canceled(false), _data(max_size
, 0)
478 DmaReadFifo::DmaDoneEvent::kill()
481 setFlags(AutoDelete
);
485 DmaReadFifo::DmaDoneEvent::cancel()
491 DmaReadFifo::DmaDoneEvent::reset(size_t size
)
493 assert(size
<= _data
.size());
500 DmaReadFifo::DmaDoneEvent::process()