c445fbc779758fc772bbe54058f806f4da07fc67
2 * Copyright (c) 2012, 2015, 2017 ARM Limited
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46 #include "dev/dma_device.hh"
50 #include "base/chunk_generator.hh"
51 #include "debug/DMA.hh"
52 #include "debug/Drain.hh"
53 #include "mem/port_proxy.hh"
54 #include "sim/system.hh"
56 DmaPort::DmaPort(MemObject
*dev
, System
*s
)
57 : MasterPort(dev
->name() + ".dma", dev
),
58 device(dev
), sys(s
), masterId(s
->getMasterId(dev
)),
59 sendEvent([this]{ sendDma(); }, dev
->name()),
60 pendingCount(0), inRetry(false)
64 DmaPort::handleResp(PacketPtr pkt
, Tick delay
)
66 // should always see a response with a sender state
67 assert(pkt
->isResponse());
69 // get the DMA sender state
70 DmaReqState
*state
= dynamic_cast<DmaReqState
*>(pkt
->senderState
);
73 DPRINTF(DMA
, "Received response %s for addr: %#x size: %d nb: %d," \
74 " tot: %d sched %d\n",
75 pkt
->cmdString(), pkt
->getAddr(), pkt
->req
->getSize(),
76 state
->numBytes
, state
->totBytes
,
77 state
->completionEvent
?
78 state
->completionEvent
->scheduled() : 0);
80 assert(pendingCount
!= 0);
83 // update the number of bytes received based on the request rather
84 // than the packet as the latter could be rounded up to line sizes
85 state
->numBytes
+= pkt
->req
->getSize();
86 assert(state
->totBytes
>= state
->numBytes
);
88 // if we have reached the total number of bytes for this DMA
89 // request, then signal the completion and delete the sate
90 if (state
->totBytes
== state
->numBytes
) {
91 if (state
->completionEvent
) {
92 delay
+= state
->delay
;
93 device
->schedule(state
->completionEvent
, curTick() + delay
);
101 // we might be drained at this point, if so signal the drain event
102 if (pendingCount
== 0)
107 DmaPort::recvTimingResp(PacketPtr pkt
)
109 // We shouldn't ever get a cacheable block in Modified state
110 assert(pkt
->req
->isUncacheable() ||
111 !(pkt
->cacheResponding() && !pkt
->hasSharers()));
118 DmaDevice::DmaDevice(const Params
*p
)
119 : PioDevice(p
), dmaPort(this, sys
)
125 if (!dmaPort
.isConnected())
126 panic("DMA port of %s not connected to anything!", name());
133 if (pendingCount
== 0) {
134 return DrainState::Drained
;
136 DPRINTF(Drain
, "DmaPort not drained\n");
137 return DrainState::Draining
;
142 DmaPort::recvReqRetry()
144 assert(transmitList
.size());
149 DmaPort::dmaAction(Packet::Command cmd
, Addr addr
, int size
, Event
*event
,
150 uint8_t *data
, Tick delay
, Request::Flags flag
)
152 // one DMA request sender state for every action, that is then
153 // split into many requests and packets based on the block size,
154 // i.e. cache line size
155 DmaReqState
*reqState
= new DmaReqState(event
, size
, delay
);
157 // (functionality added for Table Walker statistics)
158 // We're only interested in this when there will only be one request.
159 // For simplicity, we return the last request, which would also be
160 // the only request in that case.
161 RequestPtr req
= NULL
;
163 DPRINTF(DMA
, "Starting DMA for addr: %#x size: %d sched: %d\n", addr
, size
,
164 event
? event
->scheduled() : -1);
165 for (ChunkGenerator
gen(addr
, size
, sys
->cacheLineSize());
166 !gen
.done(); gen
.next()) {
168 req
= std::make_shared
<Request
>(
169 gen
.addr(), gen
.size(), flag
, masterId
);
171 req
->taskId(ContextSwitchTaskId::DMA
);
172 PacketPtr pkt
= new Packet(req
, cmd
);
174 // Increment the data pointer on a write
176 pkt
->dataStatic(data
+ gen
.complete());
178 pkt
->senderState
= reqState
;
180 DPRINTF(DMA
, "--Queuing DMA for addr: %#x size: %d\n", gen
.addr(),
185 // in zero time also initiate the sending of the packets we have
186 // just created, for atomic this involves actually completing all
194 DmaPort::queueDma(PacketPtr pkt
)
196 transmitList
.push_back(pkt
);
198 // remember that we have another packet pending, this will only be
199 // decremented once a response comes back
204 DmaPort::trySendTimingReq()
206 // send the first packet on the transmit list and schedule the
207 // following send if it is successful
208 PacketPtr pkt
= transmitList
.front();
210 DPRINTF(DMA
, "Trying to send %s addr %#x\n", pkt
->cmdString(),
213 inRetry
= !sendTimingReq(pkt
);
215 transmitList
.pop_front();
216 DPRINTF(DMA
, "-- Done\n");
217 // if there is more to do, then do so
218 if (!transmitList
.empty())
219 // this should ultimately wait for as many cycles as the
220 // device needs to send the packet, but currently the port
221 // does not have any known width so simply wait a single
223 device
->schedule(sendEvent
, device
->clockEdge(Cycles(1)));
225 DPRINTF(DMA
, "-- Failed, waiting for retry\n");
228 DPRINTF(DMA
, "TransmitList: %d, inRetry: %d\n",
229 transmitList
.size(), inRetry
);
235 // some kind of selcetion between access methods
236 // more work is going to have to be done to make
237 // switching actually work
238 assert(transmitList
.size());
240 if (sys
->isTimingMode()) {
241 // if we are either waiting for a retry or are still waiting
242 // after sending the last packet, then do not proceed
243 if (inRetry
|| sendEvent
.scheduled()) {
244 DPRINTF(DMA
, "Can't send immediately, waiting to send\n");
249 } else if (sys
->isAtomicMode()) {
250 // send everything there is to send in zero time
251 while (!transmitList
.empty()) {
252 PacketPtr pkt
= transmitList
.front();
253 transmitList
.pop_front();
255 DPRINTF(DMA
, "Sending DMA for addr: %#x size: %d\n",
256 pkt
->req
->getPaddr(), pkt
->req
->getSize());
257 Tick lat
= sendAtomic(pkt
);
259 handleResp(pkt
, lat
);
262 panic("Unknown memory mode.");
266 DmaDevice::getMasterPort(const std::string
&if_name
, PortID idx
)
268 if (if_name
== "dma") {
271 return PioDevice::getMasterPort(if_name
, idx
);
278 DmaReadFifo::DmaReadFifo(DmaPort
&_port
, size_t size
,
279 unsigned max_req_size
,
280 unsigned max_pending
,
281 Request::Flags flags
)
282 : maxReqSize(max_req_size
), fifoSize(size
),
283 reqFlags(flags
), port(_port
),
285 nextAddr(0), endAddr(0)
287 freeRequests
.resize(max_pending
);
288 for (auto &e
: freeRequests
)
289 e
.reset(new DmaDoneEvent(this, max_req_size
));
293 DmaReadFifo::~DmaReadFifo()
295 for (auto &p
: pendingRequests
) {
296 DmaDoneEvent
*e(p
.release());
301 // We can't kill in-flight DMAs, so we'll just transfer
302 // ownership to the event queue so that they get freed
303 // when they are done.
310 DmaReadFifo::serialize(CheckpointOut
&cp
) const
312 assert(pendingRequests
.empty());
314 SERIALIZE_CONTAINER(buffer
);
315 SERIALIZE_SCALAR(endAddr
);
316 SERIALIZE_SCALAR(nextAddr
);
320 DmaReadFifo::unserialize(CheckpointIn
&cp
)
322 UNSERIALIZE_CONTAINER(buffer
);
323 UNSERIALIZE_SCALAR(endAddr
);
324 UNSERIALIZE_SCALAR(nextAddr
);
328 DmaReadFifo::tryGet(uint8_t *dst
, size_t len
)
330 if (buffer
.size() >= len
) {
331 buffer
.read(dst
, len
);
340 DmaReadFifo::get(uint8_t *dst
, size_t len
)
342 const bool success(tryGet(dst
, len
));
343 panic_if(!success
, "Buffer underrun in DmaReadFifo::get()\n");
347 DmaReadFifo::startFill(Addr start
, size_t size
)
349 assert(atEndOfBlock());
352 endAddr
= start
+ size
;
357 DmaReadFifo::stopFill()
359 // Prevent new DMA requests by setting the next address to the end
360 // address. Pending requests will still complete.
363 // Flag in-flight accesses as canceled. This prevents their data
364 // from being written to the FIFO.
365 for (auto &p
: pendingRequests
)
370 DmaReadFifo::resumeFill()
372 // Don't try to fetch more data if we are draining. This ensures
373 // that the DMA engine settles down before we checkpoint it.
374 if (drainState() == DrainState::Draining
)
377 const bool old_eob(atEndOfBlock());
379 if (port
.sys
->bypassCaches())
380 resumeFillFunctional();
384 if (!old_eob
&& atEndOfBlock())
389 DmaReadFifo::resumeFillFunctional()
391 const size_t fifo_space
= buffer
.capacity() - buffer
.size();
392 const size_t kvm_watermark
= port
.sys
->cacheLineSize();
393 if (fifo_space
>= kvm_watermark
|| buffer
.capacity() < kvm_watermark
) {
394 const size_t block_remaining
= endAddr
- nextAddr
;
395 const size_t xfer_size
= std::min(fifo_space
, block_remaining
);
396 std::vector
<uint8_t> tmp_buffer(xfer_size
);
398 assert(pendingRequests
.empty());
399 DPRINTF(DMA
, "KVM Bypassing startAddr=%#x xfer_size=%#x " \
400 "fifo_space=%#x block_remaining=%#x\n",
401 nextAddr
, xfer_size
, fifo_space
, block_remaining
);
403 port
.sys
->physProxy
.readBlob(nextAddr
, tmp_buffer
.data(), xfer_size
);
404 buffer
.write(tmp_buffer
.begin(), xfer_size
);
405 nextAddr
+= xfer_size
;
410 DmaReadFifo::resumeFillTiming()
412 size_t size_pending(0);
413 for (auto &e
: pendingRequests
)
414 size_pending
+= e
->requestSize();
416 while (!freeRequests
.empty() && !atEndOfBlock()) {
417 const size_t req_size(std::min(maxReqSize
, endAddr
- nextAddr
));
418 if (buffer
.size() + size_pending
+ req_size
> fifoSize
)
421 DmaDoneEventUPtr
event(std::move(freeRequests
.front()));
422 freeRequests
.pop_front();
425 event
->reset(req_size
);
426 port
.dmaAction(MemCmd::ReadReq
, nextAddr
, req_size
, event
.get(),
427 event
->data(), 0, reqFlags
);
428 nextAddr
+= req_size
;
429 size_pending
+= req_size
;
431 pendingRequests
.emplace_back(std::move(event
));
436 DmaReadFifo::dmaDone()
438 const bool old_active(isActive());
443 if (old_active
&& !isActive())
448 DmaReadFifo::handlePending()
450 while (!pendingRequests
.empty() && pendingRequests
.front()->done()) {
451 // Get the first finished pending request
452 DmaDoneEventUPtr
event(std::move(pendingRequests
.front()));
453 pendingRequests
.pop_front();
455 if (!event
->canceled())
456 buffer
.write(event
->data(), event
->requestSize());
458 // Move the event to the list of free requests
459 freeRequests
.emplace_back(std::move(event
));
462 if (pendingRequests
.empty())
469 return pendingRequests
.empty() ? DrainState::Drained
: DrainState::Draining
;
473 DmaReadFifo::DmaDoneEvent::DmaDoneEvent(DmaReadFifo
*_parent
,
475 : parent(_parent
), _done(false), _canceled(false), _data(max_size
, 0)
480 DmaReadFifo::DmaDoneEvent::kill()
483 setFlags(AutoDelete
);
487 DmaReadFifo::DmaDoneEvent::cancel()
493 DmaReadFifo::DmaDoneEvent::reset(size_t size
)
495 assert(size
<= _data
.size());
502 DmaReadFifo::DmaDoneEvent::process()