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44 #ifndef __DEV_DMA_DEVICE_HH__
45 #define __DEV_DMA_DEVICE_HH__
49 #include "dev/io_device.hh"
50 #include "params/DmaDevice.hh"
51 #include "sim/drain.hh"
53 class DmaPort : public MasterPort
58 * Take the first packet of the transmit list and attempt to send
59 * it as a timing request. If it is successful, schedule the
60 * sending of the next packet, otherwise remember that we are
61 * waiting for a retry.
63 void trySendTimingReq();
66 * For timing, attempt to send the first item on the transmit
67 * list, and if it is successful and there are more packets
68 * waiting, then schedule the sending of the next packet. For
69 * atomic, simply send and process everything on the transmit
75 * Handle a response packet by updating the corresponding DMA
76 * request state to reflect the bytes received, and also update
77 * the pending request counter. If the DMA request that this
78 * packet is part of is complete, then signal the completion event
79 * if present, potentially with a delay added to it.
81 * @param pkt Response packet to handler
82 * @param delay Additional delay for scheduling the completion event
84 void handleResp(PacketPtr pkt, Tick delay = 0);
86 struct DmaReqState : public Packet::SenderState
88 /** Event to call on the device when this transaction (all packets)
90 Event *completionEvent;
92 /** Total number of bytes that this transaction involves. */
95 /** Number of bytes that have been acked for this transaction. */
98 /** Amount to delay completion of dma by */
101 DmaReqState(Event *ce, Addr tb, Tick _delay)
102 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
106 /** The device that owns this port. */
109 /** Use a deque as we never do any insertion or removal in the middle */
110 std::deque<PacketPtr> transmitList;
112 /** Event used to schedule a future sending from the transmit list. */
113 EventWrapper<DmaPort, &DmaPort::sendDma> sendEvent;
115 /** The system that device/port are in. This is used to select which mode
116 * we are currently operating in. */
119 /** Id for all requests */
120 const MasterID masterId;
122 /** Number of outstanding packets the dma port has. */
123 uint32_t pendingCount;
125 /** If we need to drain, keep the drain event around until we're done
127 DrainManager *drainManager;
129 /** If the port is currently waiting for a retry before it can
130 * send whatever it is that it's sending. */
135 bool recvTimingResp(PacketPtr pkt);
138 void queueDma(PacketPtr pkt);
142 DmaPort(MemObject *dev, System *s);
144 void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
145 uint8_t *data, Tick delay, Request::Flags flag = 0);
147 bool dmaPending() const { return pendingCount > 0; }
149 unsigned cacheBlockSize() const { return peerBlockSize(); }
150 unsigned int drain(DrainManager *drainManger);
153 class DmaDevice : public PioDevice
159 typedef DmaDeviceParams Params;
160 DmaDevice(const Params *p);
161 virtual ~DmaDevice() { }
163 void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
166 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
169 void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
172 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
175 bool dmaPending() const { return dmaPort.dmaPending(); }
179 unsigned int drain(DrainManager *drainManger);
181 unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); }
183 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
184 PortID idx = InvalidPortID);
188 #endif // __DEV_DMA_DEVICE_HH__