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45 #ifndef __DEV_DMA_DEVICE_HH__
46 #define __DEV_DMA_DEVICE_HH__
51 #include "base/circlebuf.hh"
52 #include "dev/io_device.hh"
53 #include "params/DmaDevice.hh"
54 #include "sim/drain.hh"
55 #include "sim/system.hh"
57 class DmaPort : public MasterPort, public Drainable
62 * Take the first packet of the transmit list and attempt to send
63 * it as a timing request. If it is successful, schedule the
64 * sending of the next packet, otherwise remember that we are
65 * waiting for a retry.
67 void trySendTimingReq();
70 * For timing, attempt to send the first item on the transmit
71 * list, and if it is successful and there are more packets
72 * waiting, then schedule the sending of the next packet. For
73 * atomic, simply send and process everything on the transmit
79 * Handle a response packet by updating the corresponding DMA
80 * request state to reflect the bytes received, and also update
81 * the pending request counter. If the DMA request that this
82 * packet is part of is complete, then signal the completion event
83 * if present, potentially with a delay added to it.
85 * @param pkt Response packet to handler
86 * @param delay Additional delay for scheduling the completion event
88 void handleResp(PacketPtr pkt, Tick delay = 0);
90 struct DmaReqState : public Packet::SenderState
92 /** Event to call on the device when this transaction (all packets)
94 Event *completionEvent;
96 /** Total number of bytes that this transaction involves. */
99 /** Number of bytes that have been acked for this transaction. */
102 /** Amount to delay completion of dma by */
105 DmaReqState(Event *ce, Addr tb, Tick _delay)
106 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
111 /** The device that owns this port. */
112 MemObject *const device;
114 /** The system that device/port are in. This is used to select which mode
115 * we are currently operating in. */
118 /** Id for all requests */
119 const MasterID masterId;
122 /** Use a deque as we never do any insertion or removal in the middle */
123 std::deque<PacketPtr> transmitList;
125 /** Event used to schedule a future sending from the transmit list. */
126 EventWrapper<DmaPort, &DmaPort::sendDma> sendEvent;
128 /** Number of outstanding packets the dma port has. */
129 uint32_t pendingCount;
131 /** If the port is currently waiting for a retry before it can
132 * send whatever it is that it's sending. */
137 bool recvTimingResp(PacketPtr pkt) override;
138 void recvReqRetry() override;
140 void queueDma(PacketPtr pkt);
144 DmaPort(MemObject *dev, System *s);
146 RequestPtr dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
147 uint8_t *data, Tick delay, Request::Flags flag = 0);
149 bool dmaPending() const { return pendingCount > 0; }
151 DrainState drain() override;
154 class DmaDevice : public PioDevice
160 typedef DmaDeviceParams Params;
161 DmaDevice(const Params *p);
162 virtual ~DmaDevice() { }
164 void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
167 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
170 void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
173 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
176 bool dmaPending() const { return dmaPort.dmaPending(); }
178 void init() override;
180 unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
182 BaseMasterPort &getMasterPort(const std::string &if_name,
183 PortID idx = InvalidPortID) override;
188 * DMA callback class.
190 * Allows one to register for a callback event after a sequence of (potentially
191 * non-contiguous) DMA transfers on a DmaPort completes. Derived classes must
192 * implement the process() method and use getChunkEvent() to allocate a
193 * callback event for each participating DMA.
195 class DmaCallback : public Drainable
198 virtual const std::string name() const { return "DmaCallback"; }
201 * DmaPort ensures that all oustanding DMA accesses have completed before
202 * it finishes draining. However, DmaChunkEvents scheduled with a delay
203 * might still be sitting on the event queue. Therefore, draining is not
204 * complete until count is 0, which ensures that all outstanding
205 * DmaChunkEvents associated with this DmaCallback have fired.
207 DrainState drain() override
209 return count ? DrainState::Draining : DrainState::Drained;
219 virtual ~DmaCallback() { }
222 * Callback function invoked on completion of all chunks.
224 virtual void process() = 0;
228 * Called by DMA engine completion event on each chunk completion.
229 * Since the object may delete itself here, callers should not use
230 * the object pointer after calling this function.
236 // Need to notify DrainManager that this object is finished
237 // draining, even though it is immediately deleted.
244 * Event invoked by DmaDevice on completion of each chunk.
246 class DmaChunkEvent : public Event
249 DmaCallback *callback;
252 DmaChunkEvent(DmaCallback *cb)
253 : Event(Default_Pri, AutoDelete), callback(cb)
256 void process() { callback->chunkComplete(); }
262 * Request a chunk event. Chunks events should be provided to each DMA
263 * request that wishes to participate in this DmaCallback.
265 Event *getChunkEvent()
268 return new DmaChunkEvent(this);
273 * Buffered DMA engine helper class
275 * This class implements a simple DMA engine that feeds a FIFO
276 * buffer. The size of the buffer, the maximum number of pending
277 * requests and the maximum request size are all set when the engine
280 * An <i>asynchronous</i> transfer of a <i>block</i> of data
281 * (designated by a start address and a size) is started by calling
282 * the startFill() method. The DMA engine will aggressively try to
283 * keep the internal FIFO full. As soon as there is room in the FIFO
284 * for more data <i>and</i> there are free request slots, a new fill
287 * Data in the FIFO can be read back using the get() and tryGet()
288 * methods. Both request a block of data from the FIFO. However, get()
289 * panics if the block cannot be satisfied, while tryGet() simply
290 * returns false. The latter call makes it possible to implement
291 * custom buffer underrun handling.
293 * A simple use case would be something like this:
295 * // Create a DMA engine with a 1KiB buffer. Issue up to 8 concurrent
296 * // uncacheable 64 byte (maximum) requests.
297 * DmaReadFifo *dma = new DmaReadFifo(port, 1024, 64, 8,
298 * Request::UNCACHEABLE);
300 * // Start copying 4KiB data from 0xFF000000
301 * dma->startFill(0xFF000000, 0x1000);
303 * // Some time later when there is data in the FIFO.
305 * dma->get(data, sizeof(data))
309 * The DMA engine allows new blocks to be requested as soon as the
310 * last request for a block has been sent (i.e., there is no need to
311 * wait for pending requests to complete). This can be queried with
312 * the atEndOfBlock() method and more advanced implementations may
313 * override the onEndOfBlock() callback.
315 class DmaReadFifo : public Drainable, public Serializable
318 DmaReadFifo(DmaPort &port, size_t size,
319 unsigned max_req_size,
320 unsigned max_pending,
321 Request::Flags flags = 0);
325 public: // Serializable
326 void serialize(CheckpointOut &cp) const override;
327 void unserialize(CheckpointIn &cp) override;
330 DrainState drain() override;
332 public: // FIFO access
338 * Try to read data from the FIFO.
340 * This method reads len bytes of data from the FIFO and stores
341 * them in the memory location pointed to by dst. The method
342 * fails, and no data is written to the buffer, if the FIFO
343 * doesn't contain enough data to satisfy the request.
345 * @param dst Pointer to a destination buffer
346 * @param len Amount of data to read.
347 * @return true on success, false otherwise.
349 bool tryGet(uint8_t *dst, size_t len);
352 bool tryGet(T &value) {
353 return tryGet(static_cast<T *>(&value), sizeof(T));
357 * Read data from the FIFO and panic on failure.
361 * @param dst Pointer to a destination buffer
362 * @param len Amount of data to read.
364 void get(uint8_t *dst, size_t len);
369 get(static_cast<uint8_t *>(&value), sizeof(T));
373 /** Get the amount of data stored in the FIFO */
374 size_t size() const { return buffer.size(); }
375 /** Flush the FIFO */
376 void flush() { buffer.flush(); }
379 public: // FIFO fill control
382 * @name FIFO fill control
385 * Start filling the FIFO.
387 * @warn It's considered an error to call start on an active DMA
388 * engine unless the last request from the active block has been
389 * sent (i.e., atEndOfBlock() is true).
391 * @param start Physical address to copy from.
392 * @param size Size of the block to copy.
394 void startFill(Addr start, size_t size);
397 * Stop the DMA engine.
399 * Stop filling the FIFO and ignore incoming responses for pending
400 * requests. The onEndOfBlock() callback will not be called after
401 * this method has been invoked. However, once the last response
402 * has been received, the onIdle() callback will still be called.
407 * Has the DMA engine sent out the last request for the active
410 bool atEndOfBlock() const {
411 return nextAddr == endAddr;
415 * Is the DMA engine active (i.e., are there still in-flight
418 bool isActive() const {
419 return !(pendingRequests.empty() && atEndOfBlock());
423 protected: // Callbacks
429 * End of block callback
431 * This callback is called <i>once</i> after the last access in a
432 * block has been sent. It is legal for a derived class to call
433 * startFill() from this method to initiate a transfer.
435 virtual void onEndOfBlock() {};
438 * Last response received callback
440 * This callback is called when the DMA engine becomes idle (i.e.,
441 * there are no pending requests).
443 * It is possible for a DMA engine to reach the end of block and
444 * become idle at the same tick. In such a case, the
445 * onEndOfBlock() callback will be called first. This callback
446 * will <i>NOT</i> be called if that callback initiates a new DMA transfer.
448 virtual void onIdle() {};
451 private: // Configuration
452 /** Maximum request size in bytes */
453 const Addr maxReqSize;
454 /** Maximum FIFO size in bytes */
455 const size_t fifoSize;
457 const Request::Flags reqFlags;
462 class DmaDoneEvent : public Event
465 DmaDoneEvent(DmaReadFifo *_parent, size_t max_size);
469 bool canceled() const { return _canceled; }
470 void reset(size_t size);
473 bool done() const { return _done; }
474 size_t requestSize() const { return _requestSize; }
475 const uint8_t *data() const { return _data.data(); }
476 uint8_t *data() { return _data.data(); }
483 std::vector<uint8_t> _data;
486 typedef std::unique_ptr<DmaDoneEvent> DmaDoneEventUPtr;
489 * DMA request done, handle incoming data and issue new
494 /** Handle pending requests that have been flagged as done. */
495 void handlePending();
497 /** Try to issue new DMA requests or bypass DMA requests*/
500 /** Try to issue new DMA requests during normal execution*/
501 void resumeFillTiming();
503 /** Try to bypass DMA requests in KVM execution mode */
504 void resumeFillFunctional();
506 private: // Internal state
507 Fifo<uint8_t> buffer;
512 std::deque<DmaDoneEventUPtr> pendingRequests;
513 std::deque<DmaDoneEventUPtr> freeRequests;
516 #endif // __DEV_DMA_DEVICE_HH__