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45 #ifndef __DEV_DMA_DEVICE_HH__
46 #define __DEV_DMA_DEVICE_HH__
51 #include "base/circlebuf.hh"
52 #include "dev/io_device.hh"
53 #include "params/DmaDevice.hh"
54 #include "sim/drain.hh"
55 #include "sim/system.hh"
57 class DmaPort : public MasterPort, public Drainable
62 * Take the first packet of the transmit list and attempt to send
63 * it as a timing request. If it is successful, schedule the
64 * sending of the next packet, otherwise remember that we are
65 * waiting for a retry.
67 void trySendTimingReq();
70 * For timing, attempt to send the first item on the transmit
71 * list, and if it is successful and there are more packets
72 * waiting, then schedule the sending of the next packet. For
73 * atomic, simply send and process everything on the transmit
79 * Handle a response packet by updating the corresponding DMA
80 * request state to reflect the bytes received, and also update
81 * the pending request counter. If the DMA request that this
82 * packet is part of is complete, then signal the completion event
83 * if present, potentially with a delay added to it.
85 * @param pkt Response packet to handler
86 * @param delay Additional delay for scheduling the completion event
88 void handleResp(PacketPtr pkt, Tick delay = 0);
90 struct DmaReqState : public Packet::SenderState
92 /** Event to call on the device when this transaction (all packets)
94 Event *completionEvent;
96 /** Total number of bytes that this transaction involves. */
99 /** Number of bytes that have been acked for this transaction. */
102 /** Amount to delay completion of dma by */
105 DmaReqState(Event *ce, Addr tb, Tick _delay)
106 : completionEvent(ce), totBytes(tb), numBytes(0), delay(_delay)
111 /** The device that owns this port. */
112 MemObject *const device;
114 /** The system that device/port are in. This is used to select which mode
115 * we are currently operating in. */
118 /** Id for all requests */
119 const MasterID masterId;
122 /** Use a deque as we never do any insertion or removal in the middle */
123 std::deque<PacketPtr> transmitList;
125 /** Event used to schedule a future sending from the transmit list. */
126 EventWrapper<DmaPort, &DmaPort::sendDma> sendEvent;
128 /** Number of outstanding packets the dma port has. */
129 uint32_t pendingCount;
131 /** If the port is currently waiting for a retry before it can
132 * send whatever it is that it's sending. */
137 bool recvTimingResp(PacketPtr pkt) override;
138 void recvReqRetry() override;
140 void queueDma(PacketPtr pkt);
144 DmaPort(MemObject *dev, System *s);
146 RequestPtr dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
147 uint8_t *data, Tick delay, Request::Flags flag = 0);
149 bool dmaPending() const { return pendingCount > 0; }
151 DrainState drain() override;
154 class DmaDevice : public PioDevice
160 typedef DmaDeviceParams Params;
161 DmaDevice(const Params *p);
162 virtual ~DmaDevice() { }
164 void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
167 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
170 void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
173 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
176 bool dmaPending() const { return dmaPort.dmaPending(); }
178 void init() override;
180 unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
182 BaseMasterPort &getMasterPort(const std::string &if_name,
183 PortID idx = InvalidPortID) override;
188 * Buffered DMA engine helper class
190 * This class implements a simple DMA engine that feeds a FIFO
191 * buffer. The size of the buffer, the maximum number of pending
192 * requests and the maximum request size are all set when the engine
195 * An <i>asynchronous</i> transfer of a <i>block</i> of data
196 * (designated by a start address and a size) is started by calling
197 * the startFill() method. The DMA engine will aggressively try to
198 * keep the internal FIFO full. As soon as there is room in the FIFO
199 * for more data <i>and</i> there are free request slots, a new fill
202 * Data in the FIFO can be read back using the get() and tryGet()
203 * methods. Both request a block of data from the FIFO. However, get()
204 * panics if the block cannot be satisfied, while tryGet() simply
205 * returns false. The latter call makes it possible to implement
206 * custom buffer underrun handling.
208 * A simple use case would be something like this:
210 * // Create a DMA engine with a 1KiB buffer. Issue up to 8 concurrent
211 * // uncacheable 64 byte (maximum) requests.
212 * DmaReadFifo *dma = new DmaReadFifo(port, 1024, 64, 8,
213 * Request::UNCACHEABLE);
215 * // Start copying 4KiB data from 0xFF000000
216 * dma->startFill(0xFF000000, 0x1000);
218 * // Some time later when there is data in the FIFO.
220 * dma->get(data, sizeof(data))
224 * The DMA engine allows new blocks to be requested as soon as the
225 * last request for a block has been sent (i.e., there is no need to
226 * wait for pending requests to complete). This can be queried with
227 * the atEndOfBlock() method and more advanced implementations may
228 * override the onEndOfBlock() callback.
230 class DmaReadFifo : public Drainable, public Serializable
233 DmaReadFifo(DmaPort &port, size_t size,
234 unsigned max_req_size,
235 unsigned max_pending,
236 Request::Flags flags = 0);
240 public: // Serializable
241 void serialize(CheckpointOut &cp) const override;
242 void unserialize(CheckpointIn &cp) override;
245 DrainState drain() override;
247 public: // FIFO access
253 * Try to read data from the FIFO.
255 * This method reads len bytes of data from the FIFO and stores
256 * them in the memory location pointed to by dst. The method
257 * fails, and no data is written to the buffer, if the FIFO
258 * doesn't contain enough data to satisfy the request.
260 * @param dst Pointer to a destination buffer
261 * @param len Amount of data to read.
262 * @return true on success, false otherwise.
264 bool tryGet(uint8_t *dst, size_t len);
267 bool tryGet(T &value) {
268 return tryGet(static_cast<T *>(&value), sizeof(T));
272 * Read data from the FIFO and panic on failure.
276 * @param dst Pointer to a destination buffer
277 * @param len Amount of data to read.
279 void get(uint8_t *dst, size_t len);
284 get(static_cast<uint8_t *>(&value), sizeof(T));
288 /** Get the amount of data stored in the FIFO */
289 size_t size() const { return buffer.size(); }
290 /** Flush the FIFO */
291 void flush() { buffer.flush(); }
294 public: // FIFO fill control
297 * @name FIFO fill control
300 * Start filling the FIFO.
302 * @warn It's considered an error to call start on an active DMA
303 * engine unless the last request from the active block has been
304 * sent (i.e., atEndOfBlock() is true).
306 * @param start Physical address to copy from.
307 * @param size Size of the block to copy.
309 void startFill(Addr start, size_t size);
312 * Stop the DMA engine.
314 * Stop filling the FIFO and ignore incoming responses for pending
315 * requests. The onEndOfBlock() callback will not be called after
316 * this method has been invoked. However, once the last response
317 * has been received, the onIdle() callback will still be called.
322 * Has the DMA engine sent out the last request for the active
325 bool atEndOfBlock() const {
326 return nextAddr == endAddr;
330 * Is the DMA engine active (i.e., are there still in-flight
333 bool isActive() const {
334 return !(pendingRequests.empty() && atEndOfBlock());
338 protected: // Callbacks
344 * End of block callback
346 * This callback is called <i>once</i> after the last access in a
347 * block has been sent. It is legal for a derived class to call
348 * startFill() from this method to initiate a transfer.
350 virtual void onEndOfBlock() {};
353 * Last response received callback
355 * This callback is called when the DMA engine becomes idle (i.e.,
356 * there are no pending requests).
358 * It is possible for a DMA engine to reach the end of block and
359 * become idle at the same tick. In such a case, the
360 * onEndOfBlock() callback will be called first. This callback
361 * will <i>NOT</i> be called if that callback initiates a new DMA transfer.
363 virtual void onIdle() {};
366 private: // Configuration
367 /** Maximum request size in bytes */
368 const Addr maxReqSize;
369 /** Maximum FIFO size in bytes */
370 const size_t fifoSize;
372 const Request::Flags reqFlags;
377 class DmaDoneEvent : public Event
380 DmaDoneEvent(DmaReadFifo *_parent, size_t max_size);
384 bool canceled() const { return _canceled; }
385 void reset(size_t size);
388 bool done() const { return _done; }
389 size_t requestSize() const { return _requestSize; }
390 const uint8_t *data() const { return _data.data(); }
391 uint8_t *data() { return _data.data(); }
398 std::vector<uint8_t> _data;
401 typedef std::unique_ptr<DmaDoneEvent> DmaDoneEventUPtr;
404 * DMA request done, handle incoming data and issue new
409 /** Handle pending requests that have been flagged as done. */
410 void handlePending();
412 /** Try to issue new DMA requests */
415 private: // Internal state
416 Fifo<uint8_t> buffer;
421 std::deque<DmaDoneEventUPtr> pendingRequests;
422 std::deque<DmaDoneEventUPtr> freeRequests;
425 #endif // __DEV_DMA_DEVICE_HH__