943e6881fd30487121045cf4a38ec43492d86592
2 * Copyright (c) 2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
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11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * Device model for Intel's 8254x line of gigabit ethernet controllers.
35 #include "base/inet.hh"
36 #include "dev/i8254xGBe.hh"
37 #include "mem/packet.hh"
38 #include "sim/builder.hh"
39 #include "sim/stats.hh"
40 #include "sim/system.hh"
43 : PciDev(p
), etherInt(NULL
)
50 IGbE::writeConfig(PacketPtr pkt
)
52 int offset
= pkt
->getAddr() & PCI_CONFIG_SIZE
;
53 if (offset
< PCI_DEVICE_SPECIFIC
)
54 PciDev::writeConfig(pkt
);
56 panic("Device specific PCI config space not implemented.\n");
59 /// Some work may need to be done here based for the pci COMMAND bits.
66 IGbE::read(PacketPtr pkt
)
71 if (!getBAR(pkt
->getAddr(), bar
, daddr
))
72 panic("Invalid PCI memory access to unmapped memory.\n");
74 // Only Memory register BAR is allowed
77 DPRINTF(Ethernet
, "Accessed devie register %#X\n", daddr
);
83 /// Handle read of register here
86 pkt
->result
= Packet::Success
;
91 IGbE::write(PacketPtr pkt
)
96 if (!getBAR(pkt
->getAddr(), bar
, daddr
))
97 panic("Invalid PCI memory access to unmapped memory.\n");
99 // Only Memory register BAR is allowed
102 DPRINTF(Ethernet
, "Accessed devie register %#X\n", daddr
);
105 /// Handle write of register here
108 pkt
->result
= Packet::Success
;
114 IGbE::ethRxPkt(EthPacketPtr packet
)
116 panic("Need to implemenet\n");
123 panic("Need to implemenet\n");
127 IGbE::serialize(std::ostream
&os
)
129 panic("Need to implemenet\n");
133 IGbE::unserialize(Checkpoint
*cp
, const std::string
§ion
)
135 panic("Need to implemenet\n");
139 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbEInt
)
141 SimObjectParam
<EtherInt
*> peer
;
142 SimObjectParam
<IGbE
*> device
;
144 END_DECLARE_SIM_OBJECT_PARAMS(IGbEInt
)
146 BEGIN_INIT_SIM_OBJECT_PARAMS(IGbEInt
)
148 INIT_PARAM_DFLT(peer
, "peer interface", NULL
),
149 INIT_PARAM(device
, "Ethernet device of this interface")
151 END_INIT_SIM_OBJECT_PARAMS(IGbEInt
)
153 CREATE_SIM_OBJECT(IGbEInt
)
155 IGbEInt
*dev_int
= new IGbEInt(getInstanceName(), device
);
157 EtherInt
*p
= (EtherInt
*)peer
;
166 REGISTER_SIM_OBJECT("IGbEInt", IGbEInt
)
169 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE
)
171 SimObjectParam
<System
*> system
;
172 SimObjectParam
<Platform
*> platform
;
173 SimObjectParam
<PciConfigData
*> configdata
;
174 Param
<uint32_t> pci_bus
;
175 Param
<uint32_t> pci_dev
;
176 Param
<uint32_t> pci_func
;
177 Param
<Tick
> pio_latency
;
178 Param
<Tick
> config_latency
;
180 END_DECLARE_SIM_OBJECT_PARAMS(IGbE
)
182 BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE
)
184 INIT_PARAM(system
, "System pointer"),
185 INIT_PARAM(platform
, "Platform pointer"),
186 INIT_PARAM(configdata
, "PCI Config data"),
187 INIT_PARAM(pci_bus
, "PCI bus ID"),
188 INIT_PARAM(pci_dev
, "PCI device number"),
189 INIT_PARAM(pci_func
, "PCI function code"),
190 INIT_PARAM_DFLT(pio_latency
, "Programmed IO latency in bus cycles", 1),
191 INIT_PARAM(config_latency
, "Number of cycles for a config read or write")
193 END_INIT_SIM_OBJECT_PARAMS(IGbE
)
196 CREATE_SIM_OBJECT(IGbE
)
198 IGbE::Params
*params
= new IGbE::Params
;
200 params
->name
= getInstanceName();
201 params
->platform
= platform
;
202 params
->system
= system
;
203 params
->configData
= configdata
;
204 params
->busNum
= pci_bus
;
205 params
->deviceNum
= pci_dev
;
206 params
->functionNum
= pci_func
;
207 params
->pio_delay
= pio_latency
;
208 params
->config_delay
= config_latency
;
210 return new IGbE(params
);
213 REGISTER_SIM_OBJECT("IGbE", IGbE
)