2 * Copyright (c) 2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * Device model for Intel's 8254x line of gigabit ethernet controllers.
33 * In particular an 82547 revision 2 (82547GI) MAC because it seems to have the
34 * fewest workarounds in the driver. It will probably work with most of the
35 * other MACs with slight modifications.
40 * @todo really there are multiple dma engines.. we should implement them.
45 #include "base/inet.hh"
46 #include "base/trace.hh"
47 #include "dev/i8254xGBe.hh"
48 #include "mem/packet.hh"
49 #include "mem/packet_access.hh"
50 #include "params/IGbE.hh"
51 #include "sim/stats.hh"
52 #include "sim/system.hh"
54 using namespace iGbReg
;
57 IGbE::IGbE(const Params
*p
)
58 : EtherDevice(p
), etherInt(NULL
), drainEvent(NULL
),
59 useFlowControl(p
->use_flow_control
),
60 rxFifo(p
->rx_fifo_size
), txFifo(p
->tx_fifo_size
), rxTick(false),
61 txTick(false), txFifoTick(false), rxDmaPacket(false), pktOffset(0),
62 fetchDelay(p
->fetch_delay
), wbDelay(p
->wb_delay
),
63 fetchCompDelay(p
->fetch_comp_delay
), wbCompDelay(p
->wb_comp_delay
),
64 rxWriteDelay(p
->rx_write_delay
), txReadDelay(p
->tx_read_delay
),
65 rdtrEvent(this), radvEvent(this),
66 tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
67 rxDescCache(this, name()+".RxDesc", p
->rx_desc_cache_size
),
68 txDescCache(this, name()+".TxDesc", p
->tx_desc_cache_size
),
69 clock(p
->clock
), lastInterrupt(0)
71 etherInt
= new IGbEInt(name() + ".int", this);
73 // Initialized internal registers per Intel documentation
74 // All registers intialized to 0 by per register constructor
79 regs
.sts
.speed(3); // Say we're 1000Mbps
80 regs
.sts
.fd(1); // full duplex
81 regs
.sts
.lu(1); // link up
87 regs
.rxdctl
.wthresh(1);
101 // clear all 64 16 bit words of the eeprom
102 memset(&flash
, 0, EEPROM_SIZE
*2);
104 // Set the MAC address
105 memcpy(flash
, p
->hardware_address
.bytes(), ETH_ADDR_LEN
);
106 for (int x
= 0; x
< ETH_ADDR_LEN
/2; x
++)
107 flash
[x
] = htobe(flash
[x
]);
110 for (int x
= 0; x
< EEPROM_SIZE
; x
++)
111 csum
+= htobe(flash
[x
]);
114 // Magic happy checksum value
115 flash
[EEPROM_SIZE
-1] = htobe((uint16_t)(EEPROM_CSUM
- csum
));
117 // Store the MAC address as queue ID
118 macAddr
= p
->hardware_address
;
132 IGbE::getEthPort(const std::string
&if_name
, int idx
)
135 if (if_name
== "interface") {
136 if (etherInt
->getPeer())
137 panic("Port already connected to\n");
144 IGbE::writeConfig(PacketPtr pkt
)
146 int offset
= pkt
->getAddr() & PCI_CONFIG_SIZE
;
147 if (offset
< PCI_DEVICE_SPECIFIC
)
148 PciDev::writeConfig(pkt
);
150 panic("Device specific PCI config space not implemented.\n");
153 // Some work may need to be done here based for the pci COMMAND bits.
159 // Handy macro for range-testing register access addresses
160 #define IN_RANGE(val, base, len) (val >= base && val < (base + len))
163 IGbE::read(PacketPtr pkt
)
168 if (!getBAR(pkt
->getAddr(), bar
, daddr
))
169 panic("Invalid PCI memory access to unmapped memory.\n");
171 // Only Memory register BAR is allowed
174 // Only 32bit accesses allowed
175 assert(pkt
->getSize() == 4);
177 DPRINTF(Ethernet
, "Read device register %#X\n", daddr
);
182 // Handle read of register here
188 pkt
->set
<uint32_t>(regs
.ctrl());
191 pkt
->set
<uint32_t>(regs
.sts());
194 pkt
->set
<uint32_t>(regs
.eecd());
197 pkt
->set
<uint32_t>(regs
.eerd());
200 pkt
->set
<uint32_t>(regs
.ctrl_ext());
203 pkt
->set
<uint32_t>(regs
.mdic());
206 DPRINTF(Ethernet
, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n",
207 regs
.icr(), regs
.imr
, regs
.iam
, regs
.ctrl_ext
.iame());
208 pkt
->set
<uint32_t>(regs
.icr());
209 if (regs
.icr
.int_assert() || regs
.imr
== 0) {
210 regs
.icr
= regs
.icr() & ~mask(30);
211 DPRINTF(Ethernet
, "Cleared ICR. ICR=%#x\n", regs
.icr());
213 if (regs
.ctrl_ext
.iame() && regs
.icr
.int_assert())
214 regs
.imr
&= ~regs
.iam
;
218 // This is only useful for MSI, but the driver reads it every time
219 // Just don't do anything
220 pkt
->set
<uint32_t>(0);
223 pkt
->set
<uint32_t>(regs
.itr());
226 pkt
->set
<uint32_t>(regs
.rctl());
229 pkt
->set
<uint32_t>(regs
.fcttv());
232 pkt
->set
<uint32_t>(regs
.tctl());
235 pkt
->set
<uint32_t>(regs
.pba());
239 pkt
->set
<uint32_t>(0); // We don't care, so just return 0
242 pkt
->set
<uint32_t>(regs
.fcrtl());
245 pkt
->set
<uint32_t>(regs
.fcrth());
248 pkt
->set
<uint32_t>(regs
.rdba
.rdbal());
251 pkt
->set
<uint32_t>(regs
.rdba
.rdbah());
254 pkt
->set
<uint32_t>(regs
.rdlen());
257 pkt
->set
<uint32_t>(regs
.srrctl());
260 pkt
->set
<uint32_t>(regs
.rdh());
263 pkt
->set
<uint32_t>(regs
.rdt());
266 pkt
->set
<uint32_t>(regs
.rdtr());
267 if (regs
.rdtr
.fpd()) {
268 rxDescCache
.writeback(0);
269 DPRINTF(EthernetIntr
,
270 "Posting interrupt because of RDTR.FPD write\n");
271 postInterrupt(IT_RXT
);
276 pkt
->set
<uint32_t>(regs
.rxdctl());
279 pkt
->set
<uint32_t>(regs
.radv());
282 pkt
->set
<uint32_t>(regs
.tdba
.tdbal());
285 pkt
->set
<uint32_t>(regs
.tdba
.tdbah());
288 pkt
->set
<uint32_t>(regs
.tdlen());
291 pkt
->set
<uint32_t>(regs
.tdh());
294 pkt
->set
<uint32_t>(regs
.txdca_ctl());
297 pkt
->set
<uint32_t>(regs
.tdt());
300 pkt
->set
<uint32_t>(regs
.tidv());
303 pkt
->set
<uint32_t>(regs
.txdctl());
306 pkt
->set
<uint32_t>(regs
.tadv());
309 pkt
->set
<uint32_t>(regs
.tdwba
& mask(32));
312 pkt
->set
<uint32_t>(regs
.tdwba
>> 32);
315 pkt
->set
<uint32_t>(regs
.rxcsum());
318 pkt
->set
<uint32_t>(regs
.rlpml
);
321 pkt
->set
<uint32_t>(regs
.rfctl());
324 pkt
->set
<uint32_t>(regs
.manc());
327 pkt
->set
<uint32_t>(regs
.swsm());
331 pkt
->set
<uint32_t>(regs
.fwsm());
334 pkt
->set
<uint32_t>(regs
.sw_fw_sync
);
337 if (!IN_RANGE(daddr
, REG_VFTA
, VLAN_FILTER_TABLE_SIZE
*4) &&
338 !IN_RANGE(daddr
, REG_RAL
, RCV_ADDRESS_TABLE_SIZE
*8) &&
339 !IN_RANGE(daddr
, REG_MTA
, MULTICAST_TABLE_SIZE
*4) &&
340 !IN_RANGE(daddr
, REG_CRCERRS
, STATS_REGS_SIZE
))
341 panic("Read request to unknown register number: %#x\n", daddr
);
343 pkt
->set
<uint32_t>(0);
346 pkt
->makeAtomicResponse();
351 IGbE::write(PacketPtr pkt
)
357 if (!getBAR(pkt
->getAddr(), bar
, daddr
))
358 panic("Invalid PCI memory access to unmapped memory.\n");
360 // Only Memory register BAR is allowed
363 // Only 32bit accesses allowed
364 assert(pkt
->getSize() == sizeof(uint32_t));
366 DPRINTF(Ethernet
, "Wrote device register %#X value %#X\n",
367 daddr
, pkt
->get
<uint32_t>());
370 // Handle write of register here
372 uint32_t val
= pkt
->get
<uint32_t>();
380 if (regs
.ctrl
.tfce())
381 warn("TX Flow control enabled, should implement\n");
382 if (regs
.ctrl
.rfce())
383 warn("RX Flow control enabled, should implement\n");
393 oldClk
= regs
.eecd
.sk();
395 // See if this is a eeprom access and emulate accordingly
396 if (!oldClk
&& regs
.eecd
.sk()) {
398 eeOpcode
= eeOpcode
<< 1 | regs
.eecd
.din();
400 } else if (eeAddrBits
< 8 && eeOpcode
== EEPROM_READ_OPCODE_SPI
) {
401 eeAddr
= eeAddr
<< 1 | regs
.eecd
.din();
403 } else if (eeDataBits
< 16 && eeOpcode
== EEPROM_READ_OPCODE_SPI
) {
404 assert(eeAddr
>>1 < EEPROM_SIZE
);
405 DPRINTF(EthernetEEPROM
, "EEPROM bit read: %d word: %#X\n",
406 flash
[eeAddr
>>1] >> eeDataBits
& 0x1,
408 regs
.eecd
.dout((flash
[eeAddr
>>1] >> (15-eeDataBits
)) & 0x1);
410 } else if (eeDataBits
< 8 && eeOpcode
== EEPROM_RDSR_OPCODE_SPI
) {
414 panic("What's going on with eeprom interface? opcode:"
415 " %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode
,
416 (uint32_t)eeOpBits
, (uint32_t)eeAddr
,
417 (uint32_t)eeAddrBits
, (uint32_t)eeDataBits
);
419 // Reset everything for the next command
420 if ((eeDataBits
== 16 && eeOpcode
== EEPROM_READ_OPCODE_SPI
) ||
421 (eeDataBits
== 8 && eeOpcode
== EEPROM_RDSR_OPCODE_SPI
)) {
429 DPRINTF(EthernetEEPROM
, "EEPROM: opcode: %#X:%d addr: %#X:%d\n",
430 (uint32_t)eeOpcode
, (uint32_t) eeOpBits
,
431 (uint32_t)eeAddr
>>1, (uint32_t)eeAddrBits
);
432 if (eeOpBits
== 8 && !(eeOpcode
== EEPROM_READ_OPCODE_SPI
||
433 eeOpcode
== EEPROM_RDSR_OPCODE_SPI
))
434 panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode
,
439 // If driver requests eeprom access, immediately give it to it
440 regs
.eecd
.ee_gnt(regs
.eecd
.ee_req());
444 if (regs
.eerd
.start()) {
446 assert(regs
.eerd
.addr() < EEPROM_SIZE
);
447 regs
.eerd
.data(flash
[regs
.eerd
.addr()]);
449 DPRINTF(EthernetEEPROM
, "EEPROM: read addr: %#X data %#x\n",
450 regs
.eerd
.addr(), regs
.eerd
.data());
456 panic("No support for interrupt on mdic complete\n");
457 if (regs
.mdic
.phyadd() != 1)
458 panic("No support for reading anything but phy\n");
459 DPRINTF(Ethernet
, "%s phy address %x\n",
460 regs
.mdic
.op() == 1 ? "Writing" : "Reading",
462 switch (regs
.mdic
.regadd()) {
464 regs
.mdic
.data(0x796D); // link up
467 regs
.mdic
.data(params()->phy_pid
);
470 regs
.mdic
.data(params()->phy_epid
);
473 regs
.mdic
.data(0x7C00);
476 regs
.mdic
.data(0x3000);
479 regs
.mdic
.data(0x180); // some random length
487 DPRINTF(Ethernet
, "Writing ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n",
488 regs
.icr(), regs
.imr
, regs
.iam
, regs
.ctrl_ext
.iame());
489 if (regs
.ctrl_ext
.iame())
490 regs
.imr
&= ~regs
.iam
;
491 regs
.icr
= ~bits(val
,30,0) & regs
.icr();
498 DPRINTF(EthernetIntr
, "Posting interrupt because of ICS write\n");
499 postInterrupt((IntTypes
)val
);
515 if (regs
.rctl
.rst()) {
517 DPRINTF(EthernetSM
, "RXS: Got RESET!\n");
535 if (regs
.tctl
.en() && !oldtctl
.en()) {
541 regs
.pba
.txa(64 - regs
.pba
.rxa());
551 ; // We don't care, so don't store anything
554 warn("Writing to IVAR0, ignoring...\n");
563 regs
.rdba
.rdbal( val
& ~mask(4));
564 rxDescCache
.areaChanged();
567 regs
.rdba
.rdbah(val
);
568 rxDescCache
.areaChanged();
571 regs
.rdlen
= val
& ~mask(7);
572 rxDescCache
.areaChanged();
579 rxDescCache
.areaChanged();
583 DPRINTF(EthernetSM
, "RXS: RDT Updated.\n");
584 if (getState() == SimObject::Running
) {
585 DPRINTF(EthernetSM
, "RXS: RDT Fetching Descriptors!\n");
586 rxDescCache
.fetchDescriptors();
588 DPRINTF(EthernetSM
, "RXS: RDT NOT Fetching Desc b/c draining!\n");
601 regs
.tdba
.tdbal( val
& ~mask(4));
602 txDescCache
.areaChanged();
605 regs
.tdba
.tdbah(val
);
606 txDescCache
.areaChanged();
609 regs
.tdlen
= val
& ~mask(7);
610 txDescCache
.areaChanged();
614 txDescCache
.areaChanged();
617 regs
.txdca_ctl
= val
;
618 if (regs
.txdca_ctl
.enabled())
619 panic("No support for DCA\n");
623 DPRINTF(EthernetSM
, "TXS: TX Tail pointer updated\n");
624 if (getState() == SimObject::Running
) {
625 DPRINTF(EthernetSM
, "TXS: TDT Fetching Descriptors!\n");
626 txDescCache
.fetchDescriptors();
628 DPRINTF(EthernetSM
, "TXS: TDT NOT Fetching Desc b/c draining!\n");
641 regs
.tdwba
&= ~mask(32);
643 txDescCache
.completionWriteback(regs
.tdwba
& ~mask(1),
644 regs
.tdwba
& mask(1));
647 regs
.tdwba
&= mask(32);
648 regs
.tdwba
|= (uint64_t)val
<< 32;
649 txDescCache
.completionWriteback(regs
.tdwba
& ~mask(1),
650 regs
.tdwba
& mask(1));
660 if (regs
.rfctl
.exsten())
661 panic("Extended RX descriptors not implemented\n");
668 if (regs
.fwsm
.eep_fw_semaphore())
669 regs
.swsm
.swesmbi(0);
672 regs
.sw_fw_sync
= val
;
675 if (!IN_RANGE(daddr
, REG_VFTA
, VLAN_FILTER_TABLE_SIZE
*4) &&
676 !IN_RANGE(daddr
, REG_RAL
, RCV_ADDRESS_TABLE_SIZE
*8) &&
677 !IN_RANGE(daddr
, REG_MTA
, MULTICAST_TABLE_SIZE
*4))
678 panic("Write request to unknown register number: %#x\n", daddr
);
681 pkt
->makeAtomicResponse();
686 IGbE::postInterrupt(IntTypes t
, bool now
)
690 // Interrupt is already pending
691 if (t
& regs
.icr() && !now
)
694 regs
.icr
= regs
.icr() | t
;
696 Tick itr_interval
= Clock::Int::ns
* 256 * regs
.itr
.interval();
697 DPRINTF(EthernetIntr
,
698 "EINT: postInterrupt() curTick: %d itr: %d interval: %d\n",
699 curTick
, regs
.itr
.interval(), itr_interval
);
701 if (regs
.itr
.interval() == 0 || now
||
702 lastInterrupt
+ itr_interval
<= curTick
) {
703 if (interEvent
.scheduled()) {
704 deschedule(interEvent
);
708 Tick int_time
= lastInterrupt
+ itr_interval
;
709 assert(int_time
> 0);
710 DPRINTF(EthernetIntr
, "EINT: Scheduling timer interrupt for tick %d\n",
712 if (!interEvent
.scheduled()) {
713 schedule(interEvent
, int_time
);
719 IGbE::delayIntEvent()
731 if (!(regs
.icr() & regs
.imr
)) {
732 DPRINTF(Ethernet
, "Interrupt Masked. Not Posting\n");
736 DPRINTF(Ethernet
, "Posting Interrupt\n");
739 if (interEvent
.scheduled()) {
740 deschedule(interEvent
);
743 if (rdtrEvent
.scheduled()) {
745 deschedule(rdtrEvent
);
747 if (radvEvent
.scheduled()) {
749 deschedule(radvEvent
);
751 if (tadvEvent
.scheduled()) {
753 deschedule(tadvEvent
);
755 if (tidvEvent
.scheduled()) {
757 deschedule(tidvEvent
);
760 regs
.icr
.int_assert(1);
761 DPRINTF(EthernetIntr
, "EINT: Posting interrupt to CPU now. Vector %#x\n",
766 lastInterrupt
= curTick
;
772 if (regs
.icr
.int_assert()) {
773 regs
.icr
.int_assert(0);
774 DPRINTF(EthernetIntr
,
775 "EINT: Clearing interrupt to CPU now. Vector %#x\n",
784 DPRINTF(Ethernet
, "Checking interrupts icr: %#x imr: %#x\n", regs
.icr(),
786 // Check if we need to clear the cpu interrupt
787 if (!(regs
.icr() & regs
.imr
)) {
788 DPRINTF(Ethernet
, "Mask cleaned all interrupts\n");
789 if (interEvent
.scheduled())
790 deschedule(interEvent
);
791 if (regs
.icr
.int_assert())
794 DPRINTF(Ethernet
, "ITR = %#X itr.interval = %#X\n",
795 regs
.itr(), regs
.itr
.interval());
797 if (regs
.icr() & regs
.imr
) {
798 if (regs
.itr
.interval() == 0) {
802 "Possibly scheduling interrupt because of imr write\n");
803 if (!interEvent
.scheduled()) {
804 Tick t
= curTick
+ Clock::Int::ns
* 256 * regs
.itr
.interval();
805 DPRINTF(Ethernet
, "Scheduling for %d\n", t
);
806 schedule(interEvent
, t
);
813 ///////////////////////////// IGbE::DescCache //////////////////////////////
816 IGbE::DescCache
<T
>::DescCache(IGbE
*i
, const std::string n
, int s
)
817 : igbe(i
), _name(n
), cachePnt(0), size(s
), curFetching(0),
818 wbOut(0), pktPtr(NULL
), wbDelayEvent(this),
819 fetchDelayEvent(this), fetchEvent(this), wbEvent(this)
821 fetchBuf
= new T
[size
];
826 IGbE::DescCache
<T
>::~DescCache()
833 IGbE::DescCache
<T
>::areaChanged()
835 if (usedCache
.size() > 0 || curFetching
|| wbOut
)
836 panic("Descriptor Address, Length or Head changed. Bad\n");
843 IGbE::DescCache
<T
>::writeback(Addr aMask
)
845 int curHead
= descHead();
846 int max_to_wb
= usedCache
.size();
848 // Check if this writeback is less restrictive that the previous
849 // and if so setup another one immediately following it
851 if (aMask
< wbAlignment
) {
855 DPRINTF(EthernetDesc
,
856 "Writing back already in process, returning\n");
864 DPRINTF(EthernetDesc
, "Writing back descriptors head: %d tail: "
865 "%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n",
866 curHead
, descTail(), descLen(), cachePnt
, max_to_wb
,
869 if (max_to_wb
+ curHead
>= descLen()) {
870 max_to_wb
= descLen() - curHead
;
872 // this is by definition aligned correctly
873 } else if (wbAlignment
!= 0) {
874 // align the wb point to the mask
875 max_to_wb
= max_to_wb
& ~wbAlignment
;
878 DPRINTF(EthernetDesc
, "Writing back %d descriptors\n", max_to_wb
);
880 if (max_to_wb
<= 0) {
881 if (usedCache
.size())
882 igbe
->anBegin(annSmWb
, "Wait Alignment", CPA::FL_WAIT
);
884 igbe
->anWe(annSmWb
, annUsedCacheQ
);
890 assert(!wbDelayEvent
.scheduled());
891 igbe
->schedule(wbDelayEvent
, curTick
+ igbe
->wbDelay
);
892 igbe
->anBegin(annSmWb
, "Prepare Writeback Desc");
897 IGbE::DescCache
<T
>::writeback1()
899 // If we're draining delay issuing this DMA
900 if (igbe
->getState() != SimObject::Running
) {
901 igbe
->schedule(wbDelayEvent
, curTick
+ igbe
->wbDelay
);
905 DPRINTF(EthernetDesc
, "Begining DMA of %d descriptors\n", wbOut
);
907 for (int x
= 0; x
< wbOut
; x
++) {
908 assert(usedCache
.size());
909 memcpy(&wbBuf
[x
], usedCache
[x
], sizeof(T
));
910 igbe
->anPq(annSmWb
, annUsedCacheQ
);
911 igbe
->anPq(annSmWb
, annDescQ
);
912 igbe
->anQ(annSmWb
, annUsedDescQ
);
916 igbe
->anBegin(annSmWb
, "Writeback Desc DMA");
919 igbe
->dmaWrite(pciToDma(descBase() + descHead() * sizeof(T
)),
920 wbOut
* sizeof(T
), &wbEvent
, (uint8_t*)wbBuf
,
926 IGbE::DescCache
<T
>::fetchDescriptors()
931 DPRINTF(EthernetDesc
,
932 "Currently fetching %d descriptors, returning\n",
937 if (descTail() >= cachePnt
)
938 max_to_fetch
= descTail() - cachePnt
;
940 max_to_fetch
= descLen() - cachePnt
;
942 size_t free_cache
= size
- usedCache
.size() - unusedCache
.size();
945 igbe
->anWe(annSmFetch
, annUnusedDescQ
);
947 igbe
->anPq(annSmFetch
, annUnusedDescQ
, max_to_fetch
);
951 igbe
->anWf(annSmFetch
, annDescQ
);
953 igbe
->anRq(annSmFetch
, annDescQ
, free_cache
);
956 max_to_fetch
= std::min(max_to_fetch
, free_cache
);
959 DPRINTF(EthernetDesc
, "Fetching descriptors head: %d tail: "
960 "%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n",
961 descHead(), descTail(), descLen(), cachePnt
,
962 max_to_fetch
, descLeft());
965 if (max_to_fetch
== 0)
968 // So we don't have two descriptor fetches going on at once
969 curFetching
= max_to_fetch
;
971 assert(!fetchDelayEvent
.scheduled());
972 igbe
->schedule(fetchDelayEvent
, curTick
+ igbe
->fetchDelay
);
973 igbe
->anBegin(annSmFetch
, "Prepare Fetch Desc");
978 IGbE::DescCache
<T
>::fetchDescriptors1()
980 // If we're draining delay issuing this DMA
981 if (igbe
->getState() != SimObject::Running
) {
982 igbe
->schedule(fetchDelayEvent
, curTick
+ igbe
->fetchDelay
);
986 igbe
->anBegin(annSmFetch
, "Fetch Desc");
988 DPRINTF(EthernetDesc
, "Fetching descriptors at %#x (%#x), size: %#x\n",
989 descBase() + cachePnt
* sizeof(T
),
990 pciToDma(descBase() + cachePnt
* sizeof(T
)),
991 curFetching
* sizeof(T
));
993 igbe
->dmaRead(pciToDma(descBase() + cachePnt
* sizeof(T
)),
994 curFetching
* sizeof(T
), &fetchEvent
, (uint8_t*)fetchBuf
,
995 igbe
->fetchCompDelay
);
1000 IGbE::DescCache
<T
>::fetchComplete()
1003 igbe
->anBegin(annSmFetch
, "Fetch Complete");
1004 for (int x
= 0; x
< curFetching
; x
++) {
1006 memcpy(newDesc
, &fetchBuf
[x
], sizeof(T
));
1007 unusedCache
.push_back(newDesc
);
1008 igbe
->anDq(annSmFetch
, annUnusedDescQ
);
1009 igbe
->anQ(annSmFetch
, annUnusedCacheQ
);
1010 igbe
->anQ(annSmFetch
, annDescQ
);
1015 int oldCp
= cachePnt
;
1018 cachePnt
+= curFetching
;
1019 assert(cachePnt
<= descLen());
1020 if (cachePnt
== descLen())
1025 DPRINTF(EthernetDesc
, "Fetching complete cachePnt %d -> %d\n",
1028 if ((descTail() >= cachePnt
? (descTail() - cachePnt
) : (descLen() -
1031 igbe
->anWe(annSmFetch
, annUnusedDescQ
);
1032 } else if (!(size
- usedCache
.size() - unusedCache
.size())) {
1033 igbe
->anWf(annSmFetch
, annDescQ
);
1035 igbe
->anBegin(annSmFetch
, "Wait", CPA::FL_WAIT
);
1044 IGbE::DescCache
<T
>::wbComplete()
1047 igbe
->anBegin(annSmWb
, "Finish Writeback");
1049 long curHead
= descHead();
1051 long oldHead
= curHead
;
1054 for (int x
= 0; x
< wbOut
; x
++) {
1055 assert(usedCache
.size());
1056 delete usedCache
[0];
1057 usedCache
.pop_front();
1059 igbe
->anDq(annSmWb
, annUsedCacheQ
);
1060 igbe
->anDq(annSmWb
, annDescQ
);
1066 if (curHead
>= descLen())
1067 curHead
-= descLen();
1070 updateHead(curHead
);
1072 DPRINTF(EthernetDesc
, "Writeback complete curHead %d -> %d\n",
1075 // If we still have more to wb, call wb now
1079 DPRINTF(EthernetDesc
, "Writeback has more todo\n");
1080 writeback(wbAlignment
);
1085 if (usedCache
.size())
1086 igbe
->anBegin(annSmWb
, "Wait", CPA::FL_WAIT
);
1088 igbe
->anWe(annSmWb
, annUsedCacheQ
);
1095 IGbE::DescCache
<T
>::reset()
1097 DPRINTF(EthernetDesc
, "Reseting descriptor cache\n");
1098 for (typename
CacheType::size_type x
= 0; x
< usedCache
.size(); x
++)
1099 delete usedCache
[x
];
1100 for (typename
CacheType::size_type x
= 0; x
< unusedCache
.size(); x
++)
1101 delete unusedCache
[x
];
1104 unusedCache
.clear();
1112 IGbE::DescCache
<T
>::serialize(std::ostream
&os
)
1114 SERIALIZE_SCALAR(cachePnt
);
1115 SERIALIZE_SCALAR(curFetching
);
1116 SERIALIZE_SCALAR(wbOut
);
1117 SERIALIZE_SCALAR(moreToWb
);
1118 SERIALIZE_SCALAR(wbAlignment
);
1120 typename
CacheType::size_type usedCacheSize
= usedCache
.size();
1121 SERIALIZE_SCALAR(usedCacheSize
);
1122 for (typename
CacheType::size_type x
= 0; x
< usedCacheSize
; x
++) {
1123 arrayParamOut(os
, csprintf("usedCache_%d", x
),
1124 (uint8_t*)usedCache
[x
],sizeof(T
));
1127 typename
CacheType::size_type unusedCacheSize
= unusedCache
.size();
1128 SERIALIZE_SCALAR(unusedCacheSize
);
1129 for (typename
CacheType::size_type x
= 0; x
< unusedCacheSize
; x
++) {
1130 arrayParamOut(os
, csprintf("unusedCache_%d", x
),
1131 (uint8_t*)unusedCache
[x
],sizeof(T
));
1134 Tick fetch_delay
= 0, wb_delay
= 0;
1135 if (fetchDelayEvent
.scheduled())
1136 fetch_delay
= fetchDelayEvent
.when();
1137 SERIALIZE_SCALAR(fetch_delay
);
1138 if (wbDelayEvent
.scheduled())
1139 wb_delay
= wbDelayEvent
.when();
1140 SERIALIZE_SCALAR(wb_delay
);
1147 IGbE::DescCache
<T
>::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1149 UNSERIALIZE_SCALAR(cachePnt
);
1150 UNSERIALIZE_SCALAR(curFetching
);
1151 UNSERIALIZE_SCALAR(wbOut
);
1152 UNSERIALIZE_SCALAR(moreToWb
);
1153 UNSERIALIZE_SCALAR(wbAlignment
);
1155 typename
CacheType::size_type usedCacheSize
;
1156 UNSERIALIZE_SCALAR(usedCacheSize
);
1158 for (typename
CacheType::size_type x
= 0; x
< usedCacheSize
; x
++) {
1160 arrayParamIn(cp
, section
, csprintf("usedCache_%d", x
),
1161 (uint8_t*)temp
,sizeof(T
));
1162 usedCache
.push_back(temp
);
1165 typename
CacheType::size_type unusedCacheSize
;
1166 UNSERIALIZE_SCALAR(unusedCacheSize
);
1167 for (typename
CacheType::size_type x
= 0; x
< unusedCacheSize
; x
++) {
1169 arrayParamIn(cp
, section
, csprintf("unusedCache_%d", x
),
1170 (uint8_t*)temp
,sizeof(T
));
1171 unusedCache
.push_back(temp
);
1173 Tick fetch_delay
= 0, wb_delay
= 0;
1174 UNSERIALIZE_SCALAR(fetch_delay
);
1175 UNSERIALIZE_SCALAR(wb_delay
);
1177 igbe
->schedule(fetchDelayEvent
, fetch_delay
);
1179 igbe
->schedule(wbDelayEvent
, wb_delay
);
1184 ///////////////////////////// IGbE::RxDescCache //////////////////////////////
1186 IGbE::RxDescCache::RxDescCache(IGbE
*i
, const std::string n
, int s
)
1187 : DescCache
<RxDesc
>(i
, n
, s
), pktDone(false), splitCount(0),
1188 pktEvent(this), pktHdrEvent(this), pktDataEvent(this)
1191 annSmFetch
= "RX Desc Fetch";
1192 annSmWb
= "RX Desc Writeback";
1193 annUnusedDescQ
= "RX Unused Descriptors";
1194 annUnusedCacheQ
= "RX Unused Descriptor Cache";
1195 annUsedCacheQ
= "RX Used Descriptor Cache";
1196 annUsedDescQ
= "RX Used Descriptors";
1197 annDescQ
= "RX Descriptors";
1201 IGbE::RxDescCache::pktSplitDone()
1204 DPRINTF(EthernetDesc
,
1205 "Part of split packet done: splitcount now %d\n", splitCount
);
1206 assert(splitCount
<= 2);
1207 if (splitCount
!= 2)
1210 DPRINTF(EthernetDesc
,
1211 "Part of split packet done: calling pktComplete()\n");
1216 IGbE::RxDescCache::writePacket(EthPacketPtr packet
, int pkt_offset
)
1218 assert(unusedCache
.size());
1219 //if (!unusedCache.size())
1224 unsigned buf_len
, hdr_len
;
1226 RxDesc
*desc
= unusedCache
.front();
1227 switch (igbe
->regs
.srrctl
.desctype()) {
1229 assert(pkt_offset
== 0);
1230 bytesCopied
= packet
->length
;
1231 DPRINTF(EthernetDesc
, "Packet Length: %d Desc Size: %d\n",
1232 packet
->length
, igbe
->regs
.rctl
.descSize());
1233 assert(packet
->length
< igbe
->regs
.rctl
.descSize());
1234 igbe
->dmaWrite(pciToDma(desc
->legacy
.buf
),
1235 packet
->length
, &pktEvent
, packet
->data
,
1236 igbe
->rxWriteDelay
);
1238 case RXDT_ADV_ONEBUF
:
1239 assert(pkt_offset
== 0);
1240 bytesCopied
= packet
->length
;
1241 buf_len
= igbe
->regs
.rctl
.lpe() ? igbe
->regs
.srrctl
.bufLen() :
1242 igbe
->regs
.rctl
.descSize();
1243 DPRINTF(EthernetDesc
, "Packet Length: %d srrctl: %#x Desc Size: %d\n",
1244 packet
->length
, igbe
->regs
.srrctl(), buf_len
);
1245 assert(packet
->length
< buf_len
);
1246 igbe
->dmaWrite(pciToDma(desc
->adv_read
.pkt
),
1247 packet
->length
, &pktEvent
, packet
->data
,
1248 igbe
->rxWriteDelay
);
1249 desc
->adv_wb
.header_len
= htole(0);
1250 desc
->adv_wb
.sph
= htole(0);
1251 desc
->adv_wb
.pkt_len
= htole((uint16_t)(pktPtr
->length
));
1253 case RXDT_ADV_SPLIT_A
:
1256 buf_len
= igbe
->regs
.rctl
.lpe() ? igbe
->regs
.srrctl
.bufLen() :
1257 igbe
->regs
.rctl
.descSize();
1258 hdr_len
= igbe
->regs
.rctl
.lpe() ? igbe
->regs
.srrctl
.hdrLen() : 0;
1259 DPRINTF(EthernetDesc
,
1260 "lpe: %d Packet Length: %d offset: %d srrctl: %#x "
1261 "hdr addr: %#x Hdr Size: %d desc addr: %#x Desc Size: %d\n",
1262 igbe
->regs
.rctl
.lpe(), packet
->length
, pkt_offset
,
1263 igbe
->regs
.srrctl(), desc
->adv_read
.hdr
, hdr_len
,
1264 desc
->adv_read
.pkt
, buf_len
);
1266 split_point
= hsplit(pktPtr
);
1268 if (packet
->length
<= hdr_len
) {
1269 bytesCopied
= packet
->length
;
1270 assert(pkt_offset
== 0);
1271 DPRINTF(EthernetDesc
, "Hdr split: Entire packet in header\n");
1272 igbe
->dmaWrite(pciToDma(desc
->adv_read
.hdr
),
1273 packet
->length
, &pktEvent
, packet
->data
,
1274 igbe
->rxWriteDelay
);
1275 desc
->adv_wb
.header_len
= htole((uint16_t)packet
->length
);
1276 desc
->adv_wb
.sph
= htole(0);
1277 desc
->adv_wb
.pkt_len
= htole(0);
1278 } else if (split_point
) {
1280 // we are only copying some data, header/data has already been
1283 std::min(packet
->length
- pkt_offset
, buf_len
);
1284 bytesCopied
+= max_to_copy
;
1285 DPRINTF(EthernetDesc
,
1286 "Hdr split: Continuing data buffer copy\n");
1287 igbe
->dmaWrite(pciToDma(desc
->adv_read
.pkt
),
1288 max_to_copy
, &pktEvent
,
1289 packet
->data
+ pkt_offset
, igbe
->rxWriteDelay
);
1290 desc
->adv_wb
.header_len
= htole(0);
1291 desc
->adv_wb
.pkt_len
= htole((uint16_t)max_to_copy
);
1292 desc
->adv_wb
.sph
= htole(0);
1295 std::min(packet
->length
- split_point
, buf_len
);
1296 bytesCopied
+= max_to_copy
+ split_point
;
1298 DPRINTF(EthernetDesc
, "Hdr split: splitting at %d\n",
1300 igbe
->dmaWrite(pciToDma(desc
->adv_read
.hdr
),
1301 split_point
, &pktHdrEvent
,
1302 packet
->data
, igbe
->rxWriteDelay
);
1303 igbe
->dmaWrite(pciToDma(desc
->adv_read
.pkt
),
1304 max_to_copy
, &pktDataEvent
,
1305 packet
->data
+ split_point
, igbe
->rxWriteDelay
);
1306 desc
->adv_wb
.header_len
= htole(split_point
);
1307 desc
->adv_wb
.sph
= 1;
1308 desc
->adv_wb
.pkt_len
= htole((uint16_t)(max_to_copy
));
1311 panic("Header split not fitting within header buffer or "
1312 "undecodable packet not fitting in header unsupported\n");
1316 panic("Unimplemnted RX receive buffer type: %d\n",
1317 igbe
->regs
.srrctl
.desctype());
1324 IGbE::RxDescCache::pktComplete()
1326 assert(unusedCache
.size());
1328 desc
= unusedCache
.front();
1330 igbe
->anBegin("RXS", "Update Desc");
1332 uint16_t crcfixup
= igbe
->regs
.rctl
.secrc() ? 0 : 4 ;
1333 DPRINTF(EthernetDesc
, "pktPtr->length: %d bytesCopied: %d "
1334 "stripcrc offset: %d value written: %d %d\n",
1335 pktPtr
->length
, bytesCopied
, crcfixup
,
1336 htole((uint16_t)(pktPtr
->length
+ crcfixup
)),
1337 (uint16_t)(pktPtr
->length
+ crcfixup
));
1339 // no support for anything but starting at 0
1340 assert(igbe
->regs
.rxcsum
.pcss() == 0);
1342 DPRINTF(EthernetDesc
, "Packet written to memory updating Descriptor\n");
1344 uint16_t status
= RXDS_DD
;
1346 uint16_t ext_err
= 0;
1351 assert(bytesCopied
<= pktPtr
->length
);
1352 if (bytesCopied
== pktPtr
->length
)
1358 DPRINTF(EthernetDesc
, "Proccesing Ip packet with Id=%d\n", ip
->id());
1362 if (igbe
->regs
.rxcsum
.ipofld()) {
1363 DPRINTF(EthernetDesc
, "Checking IP checksum\n");
1364 status
|= RXDS_IPCS
;
1365 csum
= htole(cksum(ip
));
1366 igbe
->rxIpChecksums
++;
1367 if (cksum(ip
) != 0) {
1369 ext_err
|= RXDEE_IPE
;
1370 DPRINTF(EthernetDesc
, "Checksum is bad!!\n");
1374 if (tcp
&& igbe
->regs
.rxcsum
.tuofld()) {
1375 DPRINTF(EthernetDesc
, "Checking TCP checksum\n");
1376 status
|= RXDS_TCPCS
;
1378 csum
= htole(cksum(tcp
));
1379 igbe
->rxTcpChecksums
++;
1380 if (cksum(tcp
) != 0) {
1381 DPRINTF(EthernetDesc
, "Checksum is bad!!\n");
1383 ext_err
|= RXDEE_TCPE
;
1388 if (udp
&& igbe
->regs
.rxcsum
.tuofld()) {
1389 DPRINTF(EthernetDesc
, "Checking UDP checksum\n");
1390 status
|= RXDS_UDPCS
;
1392 csum
= htole(cksum(udp
));
1393 igbe
->rxUdpChecksums
++;
1394 if (cksum(udp
) != 0) {
1395 DPRINTF(EthernetDesc
, "Checksum is bad!!\n");
1396 ext_err
|= RXDEE_TCPE
;
1401 DPRINTF(EthernetSM
, "Proccesing Non-Ip packet\n");
1404 switch (igbe
->regs
.srrctl
.desctype()) {
1406 desc
->legacy
.len
= htole((uint16_t)(pktPtr
->length
+ crcfixup
));
1407 desc
->legacy
.status
= htole(status
);
1408 desc
->legacy
.errors
= htole(err
);
1409 // No vlan support at this point... just set it to 0
1410 desc
->legacy
.vlan
= 0;
1412 case RXDT_ADV_SPLIT_A
:
1413 case RXDT_ADV_ONEBUF
:
1414 desc
->adv_wb
.rss_type
= htole(0);
1415 desc
->adv_wb
.pkt_type
= htole(ptype
);
1416 if (igbe
->regs
.rxcsum
.pcsd()) {
1417 // no rss support right now
1418 desc
->adv_wb
.rss_hash
= htole(0);
1420 desc
->adv_wb
.id
= htole(ip_id
);
1421 desc
->adv_wb
.csum
= htole(csum
);
1423 desc
->adv_wb
.status
= htole(status
);
1424 desc
->adv_wb
.errors
= htole(ext_err
);
1426 desc
->adv_wb
.vlan_tag
= htole(0);
1429 panic("Unimplemnted RX receive buffer type %d\n",
1430 igbe
->regs
.srrctl
.desctype());
1433 DPRINTF(EthernetDesc
, "Descriptor complete w0: %#x w1: %#x\n",
1434 desc
->adv_read
.pkt
, desc
->adv_read
.hdr
);
1436 if (bytesCopied
== pktPtr
->length
) {
1437 DPRINTF(EthernetDesc
,
1438 "Packet completely written to descriptor buffers\n");
1439 // Deal with the rx timer interrupts
1440 if (igbe
->regs
.rdtr
.delay()) {
1441 Tick delay
= igbe
->regs
.rdtr
.delay() * igbe
->intClock();
1442 DPRINTF(EthernetSM
, "RXS: Scheduling DTR for %d\n", delay
);
1443 igbe
->reschedule(igbe
->rdtrEvent
, curTick
+ delay
);
1446 if (igbe
->regs
.radv
.idv()) {
1447 Tick delay
= igbe
->regs
.radv
.idv() * igbe
->intClock();
1448 DPRINTF(EthernetSM
, "RXS: Scheduling ADV for %d\n", delay
);
1449 if (!igbe
->radvEvent
.scheduled()) {
1450 igbe
->schedule(igbe
->radvEvent
, curTick
+ delay
);
1454 // if neither radv or rdtr, maybe itr is set...
1455 if (!igbe
->regs
.rdtr
.delay() && !igbe
->regs
.radv
.idv()) {
1457 "RXS: Receive interrupt delay disabled, posting IT_RXT\n");
1458 igbe
->postInterrupt(IT_RXT
);
1461 // If the packet is small enough, interrupt appropriately
1462 // I wonder if this is delayed or not?!
1463 if (pktPtr
->length
<= igbe
->regs
.rsrpd
.idv()) {
1465 "RXS: Posting IT_SRPD beacuse small packet received\n");
1466 igbe
->postInterrupt(IT_SRPD
);
1476 igbe
->anBegin("RXS", "Done Updating Desc");
1477 DPRINTF(EthernetDesc
, "Processing of this descriptor complete\n");
1478 igbe
->anDq("RXS", annUnusedCacheQ
);
1479 unusedCache
.pop_front();
1480 igbe
->anQ("RXS", annUsedCacheQ
);
1481 usedCache
.push_back(desc
);
1485 IGbE::RxDescCache::enableSm()
1487 if (!igbe
->drainEvent
) {
1488 igbe
->rxTick
= true;
1489 igbe
->restartClock();
1494 IGbE::RxDescCache::packetDone()
1504 IGbE::RxDescCache::hasOutstandingEvents()
1506 return pktEvent
.scheduled() || wbEvent
.scheduled() ||
1507 fetchEvent
.scheduled() || pktHdrEvent
.scheduled() ||
1508 pktDataEvent
.scheduled();
1513 IGbE::RxDescCache::serialize(std::ostream
&os
)
1515 DescCache
<RxDesc
>::serialize(os
);
1516 SERIALIZE_SCALAR(pktDone
);
1517 SERIALIZE_SCALAR(splitCount
);
1518 SERIALIZE_SCALAR(bytesCopied
);
1522 IGbE::RxDescCache::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1524 DescCache
<RxDesc
>::unserialize(cp
, section
);
1525 UNSERIALIZE_SCALAR(pktDone
);
1526 UNSERIALIZE_SCALAR(splitCount
);
1527 UNSERIALIZE_SCALAR(bytesCopied
);
1531 ///////////////////////////// IGbE::TxDescCache //////////////////////////////
1533 IGbE::TxDescCache::TxDescCache(IGbE
*i
, const std::string n
, int s
)
1534 : DescCache
<TxDesc
>(i
,n
, s
), pktDone(false), isTcp(false),
1535 pktWaiting(false), completionAddress(0), completionEnabled(false),
1536 useTso(false), pktEvent(this), headerEvent(this), nullEvent(this)
1538 annSmFetch
= "TX Desc Fetch";
1539 annSmWb
= "TX Desc Writeback";
1540 annUnusedDescQ
= "TX Unused Descriptors";
1541 annUnusedCacheQ
= "TX Unused Descriptor Cache";
1542 annUsedCacheQ
= "TX Used Descriptor Cache";
1543 annUsedDescQ
= "TX Used Descriptors";
1544 annDescQ
= "TX Descriptors";
1548 IGbE::TxDescCache::processContextDesc()
1550 assert(unusedCache
.size());
1553 DPRINTF(EthernetDesc
, "Checking and processing context descriptors\n");
1555 while (!useTso
&& unusedCache
.size() &&
1556 TxdOp::isContext(unusedCache
.front())) {
1557 DPRINTF(EthernetDesc
, "Got context descriptor type...\n");
1559 desc
= unusedCache
.front();
1560 DPRINTF(EthernetDesc
, "Descriptor upper: %#x lower: %#X\n",
1561 desc
->d1
, desc
->d2
);
1564 // is this going to be a tcp or udp packet?
1565 isTcp
= TxdOp::tcp(desc
) ? true : false;
1567 // setup all the TSO variables, they'll be ignored if we don't use
1568 // tso for this connection
1569 tsoHeaderLen
= TxdOp::hdrlen(desc
);
1570 tsoMss
= TxdOp::mss(desc
);
1572 if (TxdOp::isType(desc
, TxdOp::TXD_CNXT
) && TxdOp::tse(desc
)) {
1573 DPRINTF(EthernetDesc
, "TCP offload enabled for packet hdrlen: "
1574 "%d mss: %d paylen %d\n", TxdOp::hdrlen(desc
),
1575 TxdOp::mss(desc
), TxdOp::getLen(desc
));
1577 tsoTotalLen
= TxdOp::getLen(desc
);
1578 tsoLoadedHeader
= false;
1579 tsoDescBytesUsed
= 0;
1582 tsoPktHasHeader
= false;
1588 unusedCache
.pop_front();
1589 igbe
->anDq("TXS", annUnusedCacheQ
);
1590 usedCache
.push_back(desc
);
1591 igbe
->anQ("TXS", annUsedCacheQ
);
1594 if (!unusedCache
.size())
1597 desc
= unusedCache
.front();
1598 if (!useTso
&& TxdOp::isType(desc
, TxdOp::TXD_ADVDATA
) &&
1600 DPRINTF(EthernetDesc
, "TCP offload(adv) enabled for packet "
1601 "hdrlen: %d mss: %d paylen %d\n",
1602 tsoHeaderLen
, tsoMss
, TxdOp::getTsoLen(desc
));
1604 tsoTotalLen
= TxdOp::getTsoLen(desc
);
1605 tsoLoadedHeader
= false;
1606 tsoDescBytesUsed
= 0;
1609 tsoPktHasHeader
= false;
1613 if (useTso
&& !tsoLoadedHeader
) {
1614 // we need to fetch a header
1615 DPRINTF(EthernetDesc
, "Starting DMA of TSO header\n");
1616 assert(TxdOp::isData(desc
) && TxdOp::getLen(desc
) >= tsoHeaderLen
);
1618 assert(tsoHeaderLen
<= 256);
1619 igbe
->dmaRead(pciToDma(TxdOp::getBuf(desc
)),
1620 tsoHeaderLen
, &headerEvent
, tsoHeader
, 0);
1625 IGbE::TxDescCache::headerComplete()
1627 DPRINTF(EthernetDesc
, "TSO: Fetching TSO header complete\n");
1630 assert(unusedCache
.size());
1631 TxDesc
*desc
= unusedCache
.front();
1632 DPRINTF(EthernetDesc
, "TSO: len: %d tsoHeaderLen: %d\n",
1633 TxdOp::getLen(desc
), tsoHeaderLen
);
1635 if (TxdOp::getLen(desc
) == tsoHeaderLen
) {
1636 tsoDescBytesUsed
= 0;
1637 tsoLoadedHeader
= true;
1638 unusedCache
.pop_front();
1639 usedCache
.push_back(desc
);
1641 // I don't think this case happens, I think the headrer is always
1642 // it's own packet, if it wasn't it might be as simple as just
1643 // incrementing descBytesUsed by the header length, but I'm not
1645 panic("TSO header part of bigger packet, not implemented\n");
1652 IGbE::TxDescCache::getPacketSize(EthPacketPtr p
)
1654 if (!unusedCache
.size())
1657 DPRINTF(EthernetDesc
, "Starting processing of descriptor\n");
1659 assert(!useTso
|| tsoLoadedHeader
);
1660 TxDesc
*desc
= unusedCache
.front();
1663 DPRINTF(EthernetDesc
, "getPacket(): TxDescriptor data "
1664 "d1: %#llx d2: %#llx\n", desc
->d1
, desc
->d2
);
1665 DPRINTF(EthernetDesc
, "TSO: use: %d hdrlen: %d mss: %d total: %d "
1666 "used: %d loaded hdr: %d\n", useTso
, tsoHeaderLen
, tsoMss
,
1667 tsoTotalLen
, tsoUsedLen
, tsoLoadedHeader
);
1668 DPRINTF(EthernetDesc
, "TSO: descBytesUsed: %d copyBytes: %d "
1669 "this descLen: %d\n",
1670 tsoDescBytesUsed
, tsoCopyBytes
, TxdOp::getLen(desc
));
1671 DPRINTF(EthernetDesc
, "TSO: pktHasHeader: %d\n", tsoPktHasHeader
);
1673 if (tsoPktHasHeader
)
1674 tsoCopyBytes
= std::min((tsoMss
+ tsoHeaderLen
) - p
->length
,
1675 TxdOp::getLen(desc
) - tsoDescBytesUsed
);
1677 tsoCopyBytes
= std::min(tsoMss
,
1678 TxdOp::getLen(desc
) - tsoDescBytesUsed
);
1680 tsoCopyBytes
+ (tsoPktHasHeader
? 0 : tsoHeaderLen
);
1681 DPRINTF(EthernetDesc
, "TSO: Next packet is %d bytes\n", pkt_size
);
1685 DPRINTF(EthernetDesc
, "Next TX packet is %d bytes\n",
1686 TxdOp::getLen(unusedCache
.front()));
1687 return TxdOp::getLen(desc
);
1691 IGbE::TxDescCache::getPacketData(EthPacketPtr p
)
1693 assert(unusedCache
.size());
1696 desc
= unusedCache
.front();
1698 DPRINTF(EthernetDesc
, "getPacketData(): TxDescriptor data "
1699 "d1: %#llx d2: %#llx\n", desc
->d1
, desc
->d2
);
1700 assert((TxdOp::isLegacy(desc
) || TxdOp::isData(desc
)) &&
1701 TxdOp::getLen(desc
));
1707 DPRINTF(EthernetDesc
, "Starting DMA of packet at offset %d\n", p
->length
);
1710 assert(tsoLoadedHeader
);
1711 if (!tsoPktHasHeader
) {
1712 DPRINTF(EthernetDesc
,
1713 "Loading TSO header (%d bytes) into start of packet\n",
1715 memcpy(p
->data
, &tsoHeader
,tsoHeaderLen
);
1716 p
->length
+=tsoHeaderLen
;
1717 tsoPktHasHeader
= true;
1722 tsoDescBytesUsed
+= tsoCopyBytes
;
1723 assert(tsoDescBytesUsed
<= TxdOp::getLen(desc
));
1724 DPRINTF(EthernetDesc
,
1725 "Starting DMA of packet at offset %d length: %d\n",
1726 p
->length
, tsoCopyBytes
);
1727 igbe
->dmaRead(pciToDma(TxdOp::getBuf(desc
))
1729 tsoCopyBytes
, &pktEvent
, p
->data
+ p
->length
,
1732 igbe
->dmaRead(pciToDma(TxdOp::getBuf(desc
)),
1733 TxdOp::getLen(desc
), &pktEvent
, p
->data
+ p
->length
,
1739 IGbE::TxDescCache::pktComplete()
1743 assert(unusedCache
.size());
1746 igbe
->anBegin("TXS", "Update Desc");
1748 DPRINTF(EthernetDesc
, "DMA of packet complete\n");
1751 desc
= unusedCache
.front();
1752 assert((TxdOp::isLegacy(desc
) || TxdOp::isData(desc
)) &&
1753 TxdOp::getLen(desc
));
1755 DPRINTF(EthernetDesc
, "TxDescriptor data d1: %#llx d2: %#llx\n",
1756 desc
->d1
, desc
->d2
);
1757 DPRINTF(EthernetDesc
, "TSO: use: %d hdrlen: %d mss: %d total: %d "
1758 "used: %d loaded hdr: %d\n", useTso
, tsoHeaderLen
, tsoMss
,
1759 tsoTotalLen
, tsoUsedLen
, tsoLoadedHeader
);
1761 // Set the length of the data in the EtherPacket
1763 pktPtr
->length
+= tsoCopyBytes
;
1764 tsoUsedLen
+= tsoCopyBytes
;
1766 pktPtr
->length
+= TxdOp::getLen(desc
);
1768 DPRINTF(EthernetDesc
, "TSO: descBytesUsed: %d copyBytes: %d\n",
1769 tsoDescBytesUsed
, tsoCopyBytes
);
1772 if ((!TxdOp::eop(desc
) && !useTso
) ||
1773 (pktPtr
->length
< ( tsoMss
+ tsoHeaderLen
) &&
1774 tsoTotalLen
!= tsoUsedLen
&& useTso
)) {
1775 assert(!useTso
|| (tsoDescBytesUsed
== TxdOp::getLen(desc
)));
1776 igbe
->anDq("TXS", annUnusedCacheQ
);
1777 unusedCache
.pop_front();
1778 igbe
->anQ("TXS", annUsedCacheQ
);
1779 usedCache
.push_back(desc
);
1781 tsoDescBytesUsed
= 0;
1784 pktMultiDesc
= true;
1786 DPRINTF(EthernetDesc
, "Partial Packet Descriptor of %d bytes Done\n",
1796 pktMultiDesc
= false;
1797 // no support for vlans
1798 assert(!TxdOp::vle(desc
));
1800 // we only support single packet descriptors at this point
1802 assert(TxdOp::eop(desc
));
1804 // set that this packet is done
1805 if (TxdOp::rs(desc
))
1808 DPRINTF(EthernetDesc
, "TxDescriptor data d1: %#llx d2: %#llx\n",
1809 desc
->d1
, desc
->d2
);
1814 DPRINTF(EthernetDesc
, "TSO: Modifying IP header. Id + %d\n",
1816 ip
->id(ip
->id() + tsoPkts
++);
1817 ip
->len(pktPtr
->length
- EthPtr(pktPtr
)->size());
1821 DPRINTF(EthernetDesc
,
1822 "TSO: Modifying TCP header. old seq %d + %d\n",
1823 tcp
->seq(), tsoPrevSeq
);
1824 tcp
->seq(tcp
->seq() + tsoPrevSeq
);
1825 if (tsoUsedLen
!= tsoTotalLen
)
1826 tcp
->flags(tcp
->flags() & ~9); // clear fin & psh
1830 DPRINTF(EthernetDesc
, "TSO: Modifying UDP header.\n");
1831 udp
->len(pktPtr
->length
- EthPtr(pktPtr
)->size());
1834 tsoPrevSeq
= tsoUsedLen
;
1837 if (DTRACE(EthernetDesc
)) {
1840 DPRINTF(EthernetDesc
, "Proccesing Ip packet with Id=%d\n",
1843 DPRINTF(EthernetSM
, "Proccesing Non-Ip packet\n");
1846 // Checksums are only ofloaded for new descriptor types
1847 if (TxdOp::isData(desc
) && ( TxdOp::ixsm(desc
) || TxdOp::txsm(desc
)) ) {
1848 DPRINTF(EthernetDesc
, "Calculating checksums for packet\n");
1851 if (TxdOp::ixsm(desc
)) {
1854 igbe
->txIpChecksums
++;
1855 DPRINTF(EthernetDesc
, "Calculated IP checksum\n");
1857 if (TxdOp::txsm(desc
)) {
1862 tcp
->sum(cksum(tcp
));
1863 igbe
->txTcpChecksums
++;
1864 DPRINTF(EthernetDesc
, "Calculated TCP checksum\n");
1868 udp
->sum(cksum(udp
));
1869 igbe
->txUdpChecksums
++;
1870 DPRINTF(EthernetDesc
, "Calculated UDP checksum\n");
1872 panic("Told to checksum, but don't know how\n");
1877 if (TxdOp::ide(desc
)) {
1878 // Deal with the rx timer interrupts
1879 DPRINTF(EthernetDesc
, "Descriptor had IDE set\n");
1880 if (igbe
->regs
.tidv
.idv()) {
1881 Tick delay
= igbe
->regs
.tidv
.idv() * igbe
->intClock();
1882 DPRINTF(EthernetDesc
, "setting tidv\n");
1883 igbe
->reschedule(igbe
->tidvEvent
, curTick
+ delay
, true);
1886 if (igbe
->regs
.tadv
.idv() && igbe
->regs
.tidv
.idv()) {
1887 Tick delay
= igbe
->regs
.tadv
.idv() * igbe
->intClock();
1888 DPRINTF(EthernetDesc
, "setting tadv\n");
1889 if (!igbe
->tadvEvent
.scheduled()) {
1890 igbe
->schedule(igbe
->tadvEvent
, curTick
+ delay
);
1896 if (!useTso
|| TxdOp::getLen(desc
) == tsoDescBytesUsed
) {
1897 DPRINTF(EthernetDesc
, "Descriptor Done\n");
1898 igbe
->anDq("TXS", annUnusedCacheQ
);
1899 unusedCache
.pop_front();
1900 igbe
->anQ("TXS", annUsedCacheQ
);
1901 usedCache
.push_back(desc
);
1902 tsoDescBytesUsed
= 0;
1905 if (useTso
&& tsoUsedLen
== tsoTotalLen
)
1909 DPRINTF(EthernetDesc
,
1910 "------Packet of %d bytes ready for transmission-------\n",
1915 tsoPktHasHeader
= false;
1917 if (igbe
->regs
.txdctl
.wthresh() == 0) {
1918 igbe
->anBegin("TXS", "Desc Writeback");
1919 DPRINTF(EthernetDesc
, "WTHRESH == 0, writing back descriptor\n");
1921 } else if (igbe
->regs
.txdctl
.gran() && igbe
->regs
.txdctl
.wthresh() >=
1922 descInBlock(usedCache
.size())) {
1923 DPRINTF(EthernetDesc
, "used > WTHRESH, writing back descriptor\n");
1924 igbe
->anBegin("TXS", "Desc Writeback");
1925 writeback((igbe
->cacheBlockSize()-1)>>4);
1926 } else if (igbe
->regs
.txdctl
.wthresh() >= usedCache
.size()) {
1927 DPRINTF(EthernetDesc
, "used > WTHRESH, writing back descriptor\n");
1928 igbe
->anBegin("TXS", "Desc Writeback");
1929 writeback((igbe
->cacheBlockSize()-1)>>4);
1937 IGbE::TxDescCache::actionAfterWb()
1939 DPRINTF(EthernetDesc
, "actionAfterWb() completionEnabled: %d\n",
1941 igbe
->postInterrupt(iGbReg::IT_TXDW
);
1942 if (completionEnabled
) {
1943 descEnd
= igbe
->regs
.tdh();
1944 DPRINTF(EthernetDesc
,
1945 "Completion writing back value: %d to addr: %#x\n", descEnd
,
1947 igbe
->dmaWrite(pciToDma(mbits(completionAddress
, 63, 2)),
1948 sizeof(descEnd
), &nullEvent
, (uint8_t*)&descEnd
, 0);
1953 IGbE::TxDescCache::serialize(std::ostream
&os
)
1955 DescCache
<TxDesc
>::serialize(os
);
1956 SERIALIZE_SCALAR(pktDone
);
1957 SERIALIZE_SCALAR(isTcp
);
1958 SERIALIZE_SCALAR(pktWaiting
);
1959 SERIALIZE_SCALAR(pktMultiDesc
);
1961 SERIALIZE_SCALAR(useTso
);
1962 SERIALIZE_SCALAR(tsoHeaderLen
);
1963 SERIALIZE_SCALAR(tsoMss
);
1964 SERIALIZE_SCALAR(tsoTotalLen
);
1965 SERIALIZE_SCALAR(tsoUsedLen
);
1966 SERIALIZE_SCALAR(tsoPrevSeq
);;
1967 SERIALIZE_SCALAR(tsoPktPayloadBytes
);
1968 SERIALIZE_SCALAR(tsoLoadedHeader
);
1969 SERIALIZE_SCALAR(tsoPktHasHeader
);
1970 SERIALIZE_ARRAY(tsoHeader
, 256);
1971 SERIALIZE_SCALAR(tsoDescBytesUsed
);
1972 SERIALIZE_SCALAR(tsoCopyBytes
);
1973 SERIALIZE_SCALAR(tsoPkts
);
1975 SERIALIZE_SCALAR(completionAddress
);
1976 SERIALIZE_SCALAR(completionEnabled
);
1977 SERIALIZE_SCALAR(descEnd
);
1981 IGbE::TxDescCache::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1983 DescCache
<TxDesc
>::unserialize(cp
, section
);
1984 UNSERIALIZE_SCALAR(pktDone
);
1985 UNSERIALIZE_SCALAR(isTcp
);
1986 UNSERIALIZE_SCALAR(pktWaiting
);
1987 UNSERIALIZE_SCALAR(pktMultiDesc
);
1989 UNSERIALIZE_SCALAR(useTso
);
1990 UNSERIALIZE_SCALAR(tsoHeaderLen
);
1991 UNSERIALIZE_SCALAR(tsoMss
);
1992 UNSERIALIZE_SCALAR(tsoTotalLen
);
1993 UNSERIALIZE_SCALAR(tsoUsedLen
);
1994 UNSERIALIZE_SCALAR(tsoPrevSeq
);;
1995 UNSERIALIZE_SCALAR(tsoPktPayloadBytes
);
1996 UNSERIALIZE_SCALAR(tsoLoadedHeader
);
1997 UNSERIALIZE_SCALAR(tsoPktHasHeader
);
1998 UNSERIALIZE_ARRAY(tsoHeader
, 256);
1999 UNSERIALIZE_SCALAR(tsoDescBytesUsed
);
2000 UNSERIALIZE_SCALAR(tsoCopyBytes
);
2001 UNSERIALIZE_SCALAR(tsoPkts
);
2003 UNSERIALIZE_SCALAR(completionAddress
);
2004 UNSERIALIZE_SCALAR(completionEnabled
);
2005 UNSERIALIZE_SCALAR(descEnd
);
2009 IGbE::TxDescCache::packetAvailable()
2019 IGbE::TxDescCache::enableSm()
2021 if (!igbe
->drainEvent
) {
2022 igbe
->txTick
= true;
2023 igbe
->restartClock();
2028 IGbE::TxDescCache::hasOutstandingEvents()
2030 return pktEvent
.scheduled() || wbEvent
.scheduled() ||
2031 fetchEvent
.scheduled();
2035 ///////////////////////////////////// IGbE /////////////////////////////////
2038 IGbE::restartClock()
2040 if (!tickEvent
.scheduled() && (rxTick
|| txTick
|| txFifoTick
) &&
2041 getState() == SimObject::Running
)
2042 schedule(tickEvent
, (curTick
/ ticks(1)) * ticks(1) + ticks(1));
2046 IGbE::drain(Event
*de
)
2049 count
= pioPort
->drain(de
) + dmaPort
->drain(de
);
2050 if (rxDescCache
.hasOutstandingEvents() ||
2051 txDescCache
.hasOutstandingEvents()) {
2060 if (tickEvent
.scheduled())
2061 deschedule(tickEvent
);
2064 changeState(Draining
);
2066 changeState(Drained
);
2068 DPRINTF(EthernetSM
, "got drain() returning %d", count
);
2075 SimObject::resume();
2082 DPRINTF(EthernetSM
, "resuming from drain");
2091 DPRINTF(EthernetSM
, "checkDrain() in drain\n");
2095 if (!rxDescCache
.hasOutstandingEvents() &&
2096 !txDescCache
.hasOutstandingEvents()) {
2097 drainEvent
->process();
2103 IGbE::txStateMachine()
2105 if (!regs
.tctl
.en()) {
2107 DPRINTF(EthernetSM
, "TXS: TX disabled, stopping ticking\n");
2111 // If we have a packet available and it's length is not 0 (meaning it's not
2112 // a multidescriptor packet) put it in the fifo, otherwise an the next
2113 // iteration we'll get the rest of the data
2114 if (txPacket
&& txDescCache
.packetAvailable()
2115 && !txDescCache
.packetMultiDesc() && txPacket
->length
) {
2118 anQ("TXS", "TX FIFO Q");
2119 DPRINTF(EthernetSM
, "TXS: packet placed in TX FIFO\n");
2120 success
= txFifo
.push(txPacket
);
2121 txFifoTick
= true && !drainEvent
;
2124 anBegin("TXS", "Desc Writeback");
2125 txDescCache
.writeback((cacheBlockSize()-1)>>4);
2129 // Only support descriptor granularity
2130 if (regs
.txdctl
.lwthresh() &&
2131 txDescCache
.descLeft() < (regs
.txdctl
.lwthresh() * 8)) {
2132 DPRINTF(EthernetSM
, "TXS: LWTHRESH caused posting of TXDLOW\n");
2133 postInterrupt(IT_TXDLOW
);
2137 txPacket
= new EthPacketData(16384);
2140 if (!txDescCache
.packetWaiting()) {
2141 if (txDescCache
.descLeft() == 0) {
2142 postInterrupt(IT_TXQE
);
2143 anBegin("TXS", "Desc Writeback");
2144 txDescCache
.writeback(0);
2145 anBegin("TXS", "Desc Fetch");
2146 anWe("TXS", txDescCache
.annUnusedCacheQ
);
2147 txDescCache
.fetchDescriptors();
2148 DPRINTF(EthernetSM
, "TXS: No descriptors left in ring, forcing "
2149 "writeback stopping ticking and posting TXQE\n");
2155 if (!(txDescCache
.descUnused())) {
2156 anBegin("TXS", "Desc Fetch");
2157 txDescCache
.fetchDescriptors();
2158 anWe("TXS", txDescCache
.annUnusedCacheQ
);
2159 DPRINTF(EthernetSM
, "TXS: No descriptors available in cache, "
2160 "fetching and stopping ticking\n");
2164 anPq("TXS", txDescCache
.annUnusedCacheQ
);
2167 txDescCache
.processContextDesc();
2168 if (txDescCache
.packetWaiting()) {
2170 "TXS: Fetching TSO header, stopping ticking\n");
2175 unsigned size
= txDescCache
.getPacketSize(txPacket
);
2176 if (size
> 0 && txFifo
.avail() > size
) {
2177 anRq("TXS", "TX FIFO Q");
2178 anBegin("TXS", "DMA Packet");
2179 DPRINTF(EthernetSM
, "TXS: Reserving %d bytes in FIFO and "
2180 "beginning DMA of next packet\n", size
);
2181 txFifo
.reserve(size
);
2182 txDescCache
.getPacketData(txPacket
);
2183 } else if (size
== 0) {
2184 DPRINTF(EthernetSM
, "TXS: getPacketSize returned: %d\n", size
);
2186 "TXS: No packets to get, writing back used descriptors\n");
2187 anBegin("TXS", "Desc Writeback");
2188 txDescCache
.writeback(0);
2190 anWf("TXS", "TX FIFO Q");
2191 DPRINTF(EthernetSM
, "TXS: FIFO full, stopping ticking until space "
2192 "available in FIFO\n");
2199 DPRINTF(EthernetSM
, "TXS: Nothing to do, stopping ticking\n");
2204 IGbE::ethRxPkt(EthPacketPtr pkt
)
2206 rxBytes
+= pkt
->length
;
2209 DPRINTF(Ethernet
, "RxFIFO: Receiving pcakte from wire\n");
2210 anBegin("RXQ", "Wire Recv");
2213 if (!regs
.rctl
.en()) {
2214 DPRINTF(Ethernet
, "RxFIFO: RX not enabled, dropping\n");
2215 anBegin("RXQ", "FIFO Drop", CPA::FL_BAD
);
2219 // restart the state machines if they are stopped
2220 rxTick
= true && !drainEvent
;
2221 if ((rxTick
|| txTick
) && !tickEvent
.scheduled()) {
2223 "RXS: received packet into fifo, starting ticking\n");
2227 if (!rxFifo
.push(pkt
)) {
2228 DPRINTF(Ethernet
, "RxFIFO: Packet won't fit in fifo... dropped\n");
2229 postInterrupt(IT_RXO
, true);
2230 anBegin("RXQ", "FIFO Drop", CPA::FL_BAD
);
2234 if (CPA::available() && cpa
->enabled()) {
2235 assert(sys
->numSystemsRunning
<= 2);
2237 if (sys
->systemList
[0] == sys
)
2238 other_sys
= sys
->systemList
[1];
2240 other_sys
= sys
->systemList
[0];
2242 cpa
->hwDq(CPA::FL_NONE
, sys
, macAddr
, "RXQ", "WireQ", 0, other_sys
);
2243 anQ("RXQ", "RX FIFO Q");
2244 cpa
->hwWe(CPA::FL_NONE
, sys
, macAddr
, "RXQ", "WireQ", 0, other_sys
);
2252 IGbE::rxStateMachine()
2254 if (!regs
.rctl
.en()) {
2256 DPRINTF(EthernetSM
, "RXS: RX disabled, stopping ticking\n");
2260 // If the packet is done check for interrupts/descriptors/etc
2261 if (rxDescCache
.packetDone()) {
2262 rxDmaPacket
= false;
2263 DPRINTF(EthernetSM
, "RXS: Packet completed DMA to memory\n");
2264 int descLeft
= rxDescCache
.descLeft();
2265 DPRINTF(EthernetSM
, "RXS: descLeft: %d rdmts: %d rdlen: %d\n",
2266 descLeft
, regs
.rctl
.rdmts(), regs
.rdlen());
2267 switch (regs
.rctl
.rdmts()) {
2268 case 2: if (descLeft
> .125 * regs
.rdlen()) break;
2269 case 1: if (descLeft
> .250 * regs
.rdlen()) break;
2270 case 0: if (descLeft
> .500 * regs
.rdlen()) break;
2271 DPRINTF(Ethernet
, "RXS: Interrupting (RXDMT) "
2272 "because of descriptors left\n");
2273 postInterrupt(IT_RXDMT
);
2278 rxDescCache
.writeback(0);
2280 if (descLeft
== 0) {
2281 anBegin("RXS", "Writeback Descriptors");
2282 rxDescCache
.writeback(0);
2283 DPRINTF(EthernetSM
, "RXS: No descriptors left in ring, forcing"
2284 " writeback and stopping ticking\n");
2288 // only support descriptor granulaties
2289 assert(regs
.rxdctl
.gran());
2291 if (regs
.rxdctl
.wthresh() >= rxDescCache
.descUsed()) {
2293 "RXS: Writing back because WTHRESH >= descUsed\n");
2294 anBegin("RXS", "Writeback Descriptors");
2295 if (regs
.rxdctl
.wthresh() < (cacheBlockSize()>>4))
2296 rxDescCache
.writeback(regs
.rxdctl
.wthresh()-1);
2298 rxDescCache
.writeback((cacheBlockSize()-1)>>4);
2301 if ((rxDescCache
.descUnused() < regs
.rxdctl
.pthresh()) &&
2302 ((rxDescCache
.descLeft() - rxDescCache
.descUnused()) >
2303 regs
.rxdctl
.hthresh())) {
2304 DPRINTF(EthernetSM
, "RXS: Fetching descriptors because "
2305 "descUnused < PTHRESH\n");
2306 anBegin("RXS", "Fetch Descriptors");
2307 rxDescCache
.fetchDescriptors();
2310 if (rxDescCache
.descUnused() == 0) {
2311 anBegin("RXS", "Fetch Descriptors");
2312 rxDescCache
.fetchDescriptors();
2313 anWe("RXS", rxDescCache
.annUnusedCacheQ
);
2314 DPRINTF(EthernetSM
, "RXS: No descriptors available in cache, "
2315 "fetching descriptors and stopping ticking\n");
2323 "RXS: stopping ticking until packet DMA completes\n");
2328 if (!rxDescCache
.descUnused()) {
2329 anBegin("RXS", "Fetch Descriptors");
2330 rxDescCache
.fetchDescriptors();
2331 anWe("RXS", rxDescCache
.annUnusedCacheQ
);
2332 DPRINTF(EthernetSM
, "RXS: No descriptors available in cache, "
2333 "stopping ticking\n");
2335 DPRINTF(EthernetSM
, "RXS: No descriptors available, fetching\n");
2338 anPq("RXS", rxDescCache
.annUnusedCacheQ
);
2340 if (rxFifo
.empty()) {
2341 anWe("RXS", "RX FIFO Q");
2342 DPRINTF(EthernetSM
, "RXS: RxFIFO empty, stopping ticking\n");
2346 anPq("RXS", "RX FIFO Q");
2347 anBegin("RXS", "Get Desc");
2350 pkt
= rxFifo
.front();
2353 pktOffset
= rxDescCache
.writePacket(pkt
, pktOffset
);
2354 DPRINTF(EthernetSM
, "RXS: Writing packet into memory\n");
2355 if (pktOffset
== pkt
->length
) {
2356 anBegin( "RXS", "FIFO Dequeue");
2357 DPRINTF(EthernetSM
, "RXS: Removing packet from FIFO\n");
2359 anDq("RXS", "RX FIFO Q");
2363 DPRINTF(EthernetSM
, "RXS: stopping ticking until packet DMA completes\n");
2366 anBegin("RXS", "DMA Packet");
2372 if (txFifo
.empty()) {
2373 anWe("TXQ", "TX FIFO Q");
2379 anPq("TXQ", "TX FIFO Q");
2380 if (etherInt
->sendPacket(txFifo
.front())) {
2381 cpa
->hwQ(CPA::FL_NONE
, sys
, macAddr
, "TXQ", "WireQ", 0);
2382 if (DTRACE(EthernetSM
)) {
2383 IpPtr
ip(txFifo
.front());
2385 DPRINTF(EthernetSM
, "Transmitting Ip packet with Id=%d\n",
2388 DPRINTF(EthernetSM
, "Transmitting Non-Ip packet\n");
2390 anDq("TXQ", "TX FIFO Q");
2391 anBegin("TXQ", "Wire Send");
2393 "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
2396 txBytes
+= txFifo
.front()->length
;
2402 // We'll get woken up when the packet ethTxDone() gets called
2410 DPRINTF(EthernetSM
, "IGbE: -------------- Cycle --------------\n");
2422 if (rxTick
|| txTick
|| txFifoTick
)
2423 schedule(tickEvent
, curTick
+ ticks(1));
2429 anBegin("TXQ", "Send Done");
2430 // restart the tx state machines if they are stopped
2431 // fifo to send another packet
2432 // tx sm to put more data into the fifo
2433 txFifoTick
= true && !drainEvent
;
2434 if (txDescCache
.descLeft() != 0 && !drainEvent
)
2439 DPRINTF(EthernetSM
, "TxFIFO: Transmission complete\n");
2443 IGbE::serialize(std::ostream
&os
)
2445 PciDev::serialize(os
);
2448 SERIALIZE_SCALAR(eeOpBits
);
2449 SERIALIZE_SCALAR(eeAddrBits
);
2450 SERIALIZE_SCALAR(eeDataBits
);
2451 SERIALIZE_SCALAR(eeOpcode
);
2452 SERIALIZE_SCALAR(eeAddr
);
2453 SERIALIZE_SCALAR(lastInterrupt
);
2454 SERIALIZE_ARRAY(flash
,iGbReg::EEPROM_SIZE
);
2456 rxFifo
.serialize("rxfifo", os
);
2457 txFifo
.serialize("txfifo", os
);
2459 bool txPktExists
= txPacket
;
2460 SERIALIZE_SCALAR(txPktExists
);
2462 txPacket
->serialize("txpacket", os
);
2464 Tick rdtr_time
= 0, radv_time
= 0, tidv_time
= 0, tadv_time
= 0,
2467 if (rdtrEvent
.scheduled())
2468 rdtr_time
= rdtrEvent
.when();
2469 SERIALIZE_SCALAR(rdtr_time
);
2471 if (radvEvent
.scheduled())
2472 radv_time
= radvEvent
.when();
2473 SERIALIZE_SCALAR(radv_time
);
2475 if (tidvEvent
.scheduled())
2476 tidv_time
= tidvEvent
.when();
2477 SERIALIZE_SCALAR(tidv_time
);
2479 if (tadvEvent
.scheduled())
2480 tadv_time
= tadvEvent
.when();
2481 SERIALIZE_SCALAR(tadv_time
);
2483 if (interEvent
.scheduled())
2484 inter_time
= interEvent
.when();
2485 SERIALIZE_SCALAR(inter_time
);
2487 SERIALIZE_SCALAR(pktOffset
);
2489 nameOut(os
, csprintf("%s.TxDescCache", name()));
2490 txDescCache
.serialize(os
);
2492 nameOut(os
, csprintf("%s.RxDescCache", name()));
2493 rxDescCache
.serialize(os
);
2497 IGbE::unserialize(Checkpoint
*cp
, const std::string
§ion
)
2499 PciDev::unserialize(cp
, section
);
2501 regs
.unserialize(cp
, section
);
2502 UNSERIALIZE_SCALAR(eeOpBits
);
2503 UNSERIALIZE_SCALAR(eeAddrBits
);
2504 UNSERIALIZE_SCALAR(eeDataBits
);
2505 UNSERIALIZE_SCALAR(eeOpcode
);
2506 UNSERIALIZE_SCALAR(eeAddr
);
2507 UNSERIALIZE_SCALAR(lastInterrupt
);
2508 UNSERIALIZE_ARRAY(flash
,iGbReg::EEPROM_SIZE
);
2510 rxFifo
.unserialize("rxfifo", cp
, section
);
2511 txFifo
.unserialize("txfifo", cp
, section
);
2514 UNSERIALIZE_SCALAR(txPktExists
);
2516 txPacket
= new EthPacketData(16384);
2517 txPacket
->unserialize("txpacket", cp
, section
);
2524 Tick rdtr_time
, radv_time
, tidv_time
, tadv_time
, inter_time
;
2525 UNSERIALIZE_SCALAR(rdtr_time
);
2526 UNSERIALIZE_SCALAR(radv_time
);
2527 UNSERIALIZE_SCALAR(tidv_time
);
2528 UNSERIALIZE_SCALAR(tadv_time
);
2529 UNSERIALIZE_SCALAR(inter_time
);
2532 schedule(rdtrEvent
, rdtr_time
);
2535 schedule(radvEvent
, radv_time
);
2538 schedule(tidvEvent
, tidv_time
);
2541 schedule(tadvEvent
, tadv_time
);
2544 schedule(interEvent
, inter_time
);
2546 UNSERIALIZE_SCALAR(pktOffset
);
2548 txDescCache
.unserialize(cp
, csprintf("%s.TxDescCache", section
));
2550 rxDescCache
.unserialize(cp
, csprintf("%s.RxDescCache", section
));
2554 IGbEParams::create()
2556 return new IGbE(this);