2 * Copyright (c) 2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * Device model for Intel's 8254x line of gigabit ethernet controllers.
33 * In particular an 82547 revision 2 (82547GI) MAC because it seems to have the
34 * fewest workarounds in the driver. It will probably work with most of the
35 * other MACs with slight modifications.
40 * @todo really there are multiple dma engines.. we should implement them.
45 #include "base/inet.hh"
46 #include "base/trace.hh"
47 #include "dev/i8254xGBe.hh"
48 #include "mem/packet.hh"
49 #include "mem/packet_access.hh"
50 #include "params/IGbE.hh"
51 #include "sim/stats.hh"
52 #include "sim/system.hh"
54 using namespace iGbReg
;
57 IGbE::IGbE(const Params
*p
)
58 : EtherDevice(p
), etherInt(NULL
), drainEvent(NULL
), useFlowControl(p
->use_flow_control
),
59 rxFifo(p
->rx_fifo_size
), txFifo(p
->tx_fifo_size
), rxTick(false),
60 txTick(false), txFifoTick(false), rxDmaPacket(false), rdtrEvent(this), radvEvent(this),
61 tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
62 rxDescCache(this, name()+".RxDesc", p
->rx_desc_cache_size
),
63 txDescCache(this, name()+".TxDesc", p
->tx_desc_cache_size
), clock(p
->clock
)
65 etherInt
= new IGbEInt(name() + ".int", this);
67 // Initialized internal registers per Intel documentation
68 // All registers intialized to 0 by per register constructor
73 regs
.sts
.speed(3); // Say we're 1000Mbps
74 regs
.sts
.fd(1); // full duplex
75 regs
.sts
.lu(1); // link up
81 regs
.rxdctl
.wthresh(1);
92 // clear all 64 16 bit words of the eeprom
93 memset(&flash
, 0, EEPROM_SIZE
*2);
95 // Set the MAC address
96 memcpy(flash
, p
->hardware_address
.bytes(), ETH_ADDR_LEN
);
97 for (int x
= 0; x
< ETH_ADDR_LEN
/2; x
++)
98 flash
[x
] = htobe(flash
[x
]);
101 for (int x
= 0; x
< EEPROM_SIZE
; x
++)
102 csum
+= htobe(flash
[x
]);
105 // Magic happy checksum value
106 flash
[EEPROM_SIZE
-1] = htobe((uint16_t)(EEPROM_CSUM
- csum
));
113 IGbE::getEthPort(const std::string
&if_name
, int idx
)
116 if (if_name
== "interface") {
117 if (etherInt
->getPeer())
118 panic("Port already connected to\n");
125 IGbE::writeConfig(PacketPtr pkt
)
127 int offset
= pkt
->getAddr() & PCI_CONFIG_SIZE
;
128 if (offset
< PCI_DEVICE_SPECIFIC
)
129 PciDev::writeConfig(pkt
);
131 panic("Device specific PCI config space not implemented.\n");
134 /// Some work may need to be done here based for the pci COMMAND bits.
141 IGbE::read(PacketPtr pkt
)
146 if (!getBAR(pkt
->getAddr(), bar
, daddr
))
147 panic("Invalid PCI memory access to unmapped memory.\n");
149 // Only Memory register BAR is allowed
152 // Only 32bit accesses allowed
153 assert(pkt
->getSize() == 4);
155 DPRINTF(Ethernet
, "Read device register %#X\n", daddr
);
160 /// Handle read of register here
166 pkt
->set
<uint32_t>(regs
.ctrl());
169 pkt
->set
<uint32_t>(regs
.sts());
172 pkt
->set
<uint32_t>(regs
.eecd());
175 pkt
->set
<uint32_t>(regs
.eerd());
178 pkt
->set
<uint32_t>(regs
.ctrl_ext());
181 pkt
->set
<uint32_t>(regs
.mdic());
184 DPRINTF(Ethernet
, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", regs
.icr(),
185 regs
.imr
, regs
.iam
, regs
.ctrl_ext
.iame());
186 pkt
->set
<uint32_t>(regs
.icr());
187 if (regs
.icr
.int_assert() || regs
.imr
== 0) {
188 regs
.icr
= regs
.icr() & ~mask(30);
189 DPRINTF(Ethernet
, "Cleared ICR. ICR=%#x\n", regs
.icr());
191 if (regs
.ctrl_ext
.iame() && regs
.icr
.int_assert())
192 regs
.imr
&= ~regs
.iam
;
196 pkt
->set
<uint32_t>(regs
.itr());
199 pkt
->set
<uint32_t>(regs
.rctl());
202 pkt
->set
<uint32_t>(regs
.fcttv());
205 pkt
->set
<uint32_t>(regs
.tctl());
208 pkt
->set
<uint32_t>(regs
.pba());
212 pkt
->set
<uint32_t>(0); // We don't care, so just return 0
215 pkt
->set
<uint32_t>(regs
.fcrtl());
218 pkt
->set
<uint32_t>(regs
.fcrth());
221 pkt
->set
<uint32_t>(regs
.rdba
.rdbal());
224 pkt
->set
<uint32_t>(regs
.rdba
.rdbah());
227 pkt
->set
<uint32_t>(regs
.rdlen());
230 pkt
->set
<uint32_t>(regs
.rdh());
233 pkt
->set
<uint32_t>(regs
.rdt());
236 pkt
->set
<uint32_t>(regs
.rdtr());
237 if (regs
.rdtr
.fpd()) {
238 rxDescCache
.writeback(0);
239 DPRINTF(EthernetIntr
, "Posting interrupt because of RDTR.FPD write\n");
240 postInterrupt(IT_RXT
);
245 pkt
->set
<uint32_t>(regs
.radv());
248 pkt
->set
<uint32_t>(regs
.tdba
.tdbal());
251 pkt
->set
<uint32_t>(regs
.tdba
.tdbah());
254 pkt
->set
<uint32_t>(regs
.tdlen());
257 pkt
->set
<uint32_t>(regs
.tdh());
260 pkt
->set
<uint32_t>(regs
.tdt());
263 pkt
->set
<uint32_t>(regs
.tidv());
266 pkt
->set
<uint32_t>(regs
.txdctl());
269 pkt
->set
<uint32_t>(regs
.tadv());
272 pkt
->set
<uint32_t>(regs
.rxcsum());
275 pkt
->set
<uint32_t>(regs
.manc());
278 if (!(daddr
>= REG_VFTA
&& daddr
< (REG_VFTA
+ VLAN_FILTER_TABLE_SIZE
*4)) &&
279 !(daddr
>= REG_RAL
&& daddr
< (REG_RAL
+ RCV_ADDRESS_TABLE_SIZE
*8)) &&
280 !(daddr
>= REG_MTA
&& daddr
< (REG_MTA
+ MULTICAST_TABLE_SIZE
*4)) &&
281 !(daddr
>= REG_CRCERRS
&& daddr
< (REG_CRCERRS
+ STATS_REGS_SIZE
)))
282 panic("Read request to unknown register number: %#x\n", daddr
);
284 pkt
->set
<uint32_t>(0);
287 pkt
->makeAtomicResponse();
292 IGbE::write(PacketPtr pkt
)
298 if (!getBAR(pkt
->getAddr(), bar
, daddr
))
299 panic("Invalid PCI memory access to unmapped memory.\n");
301 // Only Memory register BAR is allowed
304 // Only 32bit accesses allowed
305 assert(pkt
->getSize() == sizeof(uint32_t));
307 DPRINTF(Ethernet
, "Wrote device register %#X value %#X\n", daddr
, pkt
->get
<uint32_t>());
310 /// Handle write of register here
312 uint32_t val
= pkt
->get
<uint32_t>();
320 if (regs
.ctrl
.tfce())
321 warn("TX Flow control enabled, should implement\n");
322 if (regs
.ctrl
.rfce())
323 warn("RX Flow control enabled, should implement\n");
333 oldClk
= regs
.eecd
.sk();
335 // See if this is a eeprom access and emulate accordingly
336 if (!oldClk
&& regs
.eecd
.sk()) {
338 eeOpcode
= eeOpcode
<< 1 | regs
.eecd
.din();
340 } else if (eeAddrBits
< 8 && eeOpcode
== EEPROM_READ_OPCODE_SPI
) {
341 eeAddr
= eeAddr
<< 1 | regs
.eecd
.din();
343 } else if (eeDataBits
< 16 && eeOpcode
== EEPROM_READ_OPCODE_SPI
) {
344 assert(eeAddr
>>1 < EEPROM_SIZE
);
345 DPRINTF(EthernetEEPROM
, "EEPROM bit read: %d word: %#X\n",
346 flash
[eeAddr
>>1] >> eeDataBits
& 0x1, flash
[eeAddr
>>1]);
347 regs
.eecd
.dout((flash
[eeAddr
>>1] >> (15-eeDataBits
)) & 0x1);
349 } else if (eeDataBits
< 8 && eeOpcode
== EEPROM_RDSR_OPCODE_SPI
) {
353 panic("What's going on with eeprom interface? opcode:"
354 " %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode
,
355 (uint32_t)eeOpBits
, (uint32_t)eeAddr
,
356 (uint32_t)eeAddrBits
, (uint32_t)eeDataBits
);
358 // Reset everything for the next command
359 if ((eeDataBits
== 16 && eeOpcode
== EEPROM_READ_OPCODE_SPI
) ||
360 (eeDataBits
== 8 && eeOpcode
== EEPROM_RDSR_OPCODE_SPI
)) {
368 DPRINTF(EthernetEEPROM
, "EEPROM: opcode: %#X:%d addr: %#X:%d\n",
369 (uint32_t)eeOpcode
, (uint32_t) eeOpBits
,
370 (uint32_t)eeAddr
>>1, (uint32_t)eeAddrBits
);
371 if (eeOpBits
== 8 && !(eeOpcode
== EEPROM_READ_OPCODE_SPI
||
372 eeOpcode
== EEPROM_RDSR_OPCODE_SPI
))
373 panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode
,
378 // If driver requests eeprom access, immediately give it to it
379 regs
.eecd
.ee_gnt(regs
.eecd
.ee_req());
387 panic("No support for interrupt on mdic complete\n");
388 if (regs
.mdic
.phyadd() != 1)
389 panic("No support for reading anything but phy\n");
390 DPRINTF(Ethernet
, "%s phy address %x\n", regs
.mdic
.op() == 1 ? "Writing"
391 : "Reading", regs
.mdic
.regadd());
392 switch (regs
.mdic
.regadd()) {
394 regs
.mdic
.data(0x796D); // link up
397 regs
.mdic
.data(0x02A8);
400 regs
.mdic
.data(0x0380);
403 regs
.mdic
.data(0x7C00);
406 regs
.mdic
.data(0x3000);
409 regs
.mdic
.data(0x180); // some random length
417 DPRINTF(Ethernet
, "Writing ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", regs
.icr(),
418 regs
.imr
, regs
.iam
, regs
.ctrl_ext
.iame());
419 if (regs
.ctrl_ext
.iame())
420 regs
.imr
&= ~regs
.iam
;
421 regs
.icr
= ~bits(val
,30,0) & regs
.icr();
428 DPRINTF(EthernetIntr
, "Posting interrupt because of ICS write\n");
429 postInterrupt((IntTypes
)val
);
445 if (regs
.rctl
.rst()) {
447 DPRINTF(EthernetSM
, "RXS: Got RESET!\n");
465 if (regs
.tctl
.en() && !oldtctl
.en()) {
471 regs
.pba
.txa(64 - regs
.pba
.rxa());
481 ; // We don't care, so don't store anything
490 regs
.rdba
.rdbal( val
& ~mask(4));
491 rxDescCache
.areaChanged();
494 regs
.rdba
.rdbah(val
);
495 rxDescCache
.areaChanged();
498 regs
.rdlen
= val
& ~mask(7);
499 rxDescCache
.areaChanged();
503 rxDescCache
.areaChanged();
507 DPRINTF(EthernetSM
, "RXS: RDT Updated.\n");
508 if (getState() == SimObject::Running
) {
509 DPRINTF(EthernetSM
, "RXS: RDT Fetching Descriptors!\n");
510 rxDescCache
.fetchDescriptors();
512 DPRINTF(EthernetSM
, "RXS: RDT NOT Fetching Desc b/c draining!\n");
522 regs
.tdba
.tdbal( val
& ~mask(4));
523 txDescCache
.areaChanged();
526 regs
.tdba
.tdbah(val
);
527 txDescCache
.areaChanged();
530 regs
.tdlen
= val
& ~mask(7);
531 txDescCache
.areaChanged();
535 txDescCache
.areaChanged();
539 DPRINTF(EthernetSM
, "TXS: TX Tail pointer updated\n");
540 if (getState() == SimObject::Running
) {
541 DPRINTF(EthernetSM
, "TXS: TDT Fetching Descriptors!\n");
542 txDescCache
.fetchDescriptors();
544 DPRINTF(EthernetSM
, "TXS: TDT NOT Fetching Desc b/c draining!\n");
563 if (!(daddr
>= REG_VFTA
&& daddr
< (REG_VFTA
+ VLAN_FILTER_TABLE_SIZE
*4)) &&
564 !(daddr
>= REG_RAL
&& daddr
< (REG_RAL
+ RCV_ADDRESS_TABLE_SIZE
*8)) &&
565 !(daddr
>= REG_MTA
&& daddr
< (REG_MTA
+ MULTICAST_TABLE_SIZE
*4)))
566 panic("Write request to unknown register number: %#x\n", daddr
);
569 pkt
->makeAtomicResponse();
574 IGbE::postInterrupt(IntTypes t
, bool now
)
578 // Interrupt is already pending
579 if (t
& regs
.icr() && !now
)
582 regs
.icr
= regs
.icr() | t
;
583 if (regs
.itr
.interval() == 0 || now
) {
584 if (interEvent
.scheduled()) {
585 interEvent
.deschedule();
589 DPRINTF(EthernetIntr
, "EINT: Scheduling timer interrupt for %d ticks\n",
590 Clock::Int::ns
* 256 * regs
.itr
.interval());
591 if (!interEvent
.scheduled()) {
592 interEvent
.schedule(curTick
+ Clock::Int::ns
* 256 * regs
.itr
.interval());
598 IGbE::delayIntEvent()
608 if (!(regs
.icr() & regs
.imr
)) {
609 DPRINTF(Ethernet
, "Interrupt Masked. Not Posting\n");
613 DPRINTF(Ethernet
, "Posting Interrupt\n");
616 if (interEvent
.scheduled()) {
617 interEvent
.deschedule();
620 if (rdtrEvent
.scheduled()) {
622 rdtrEvent
.deschedule();
624 if (radvEvent
.scheduled()) {
626 radvEvent
.deschedule();
628 if (tadvEvent
.scheduled()) {
630 tadvEvent
.deschedule();
632 if (tidvEvent
.scheduled()) {
634 tidvEvent
.deschedule();
637 regs
.icr
.int_assert(1);
638 DPRINTF(EthernetIntr
, "EINT: Posting interrupt to CPU now. Vector %#x\n",
648 if (regs
.icr
.int_assert()) {
649 regs
.icr
.int_assert(0);
650 DPRINTF(EthernetIntr
, "EINT: Clearing interrupt to CPU now. Vector %#x\n",
659 DPRINTF(Ethernet
, "Checking interrupts icr: %#x imr: %#x\n", regs
.icr(),
661 // Check if we need to clear the cpu interrupt
662 if (!(regs
.icr() & regs
.imr
)) {
663 DPRINTF(Ethernet
, "Mask cleaned all interrupts\n");
664 if (interEvent
.scheduled())
665 interEvent
.deschedule();
666 if (regs
.icr
.int_assert())
669 DPRINTF(Ethernet
, "ITR = %#X itr.interval = %#X\n", regs
.itr(), regs
.itr
.interval());
671 if (regs
.icr() & regs
.imr
) {
672 if (regs
.itr
.interval() == 0) {
675 DPRINTF(Ethernet
, "Possibly scheduling interrupt because of imr write\n");
676 if (!interEvent
.scheduled()) {
677 DPRINTF(Ethernet
, "Scheduling for %d\n", curTick
+ Clock::Int::ns
678 * 256 * regs
.itr
.interval());
679 interEvent
.schedule(curTick
+ Clock::Int::ns
* 256 * regs
.itr
.interval());
688 IGbE::RxDescCache::RxDescCache(IGbE
*i
, const std::string n
, int s
)
689 : DescCache
<RxDesc
>(i
, n
, s
), pktDone(false), pktEvent(this)
695 IGbE::RxDescCache::writePacket(EthPacketPtr packet
)
697 // We shouldn't have to deal with any of these yet
698 DPRINTF(EthernetDesc
, "Packet Length: %d Desc Size: %d\n",
699 packet
->length
, igbe
->regs
.rctl
.descSize());
700 assert(packet
->length
< igbe
->regs
.rctl
.descSize());
702 assert(unusedCache
.size());
703 //if (!unusedCache.size())
708 igbe
->dmaWrite(igbe
->platform
->pciToDma(unusedCache
.front()->buf
),
709 packet
->length
, &pktEvent
, packet
->data
);
713 IGbE::RxDescCache::pktComplete()
715 assert(unusedCache
.size());
717 desc
= unusedCache
.front();
719 uint16_t crcfixup
= igbe
->regs
.rctl
.secrc() ? 0 : 4 ;
720 desc
->len
= htole((uint16_t)(pktPtr
->length
+ crcfixup
));
721 DPRINTF(EthernetDesc
, "pktPtr->length: %d stripcrc offset: %d value written: %d %d\n",
722 pktPtr
->length
, crcfixup
,
723 htole((uint16_t)(pktPtr
->length
+ crcfixup
)),
724 (uint16_t)(pktPtr
->length
+ crcfixup
));
726 // no support for anything but starting at 0
727 assert(igbe
->regs
.rxcsum
.pcss() == 0);
729 DPRINTF(EthernetDesc
, "Packet written to memory updating Descriptor\n");
731 uint8_t status
= RXDS_DD
| RXDS_EOP
;
737 DPRINTF(EthernetDesc
, "Proccesing Ip packet with Id=%d\n", ip
->id());
739 if (igbe
->regs
.rxcsum
.ipofld()) {
740 DPRINTF(EthernetDesc
, "Checking IP checksum\n");
742 desc
->csum
= htole(cksum(ip
));
743 if (cksum(ip
) != 0) {
745 DPRINTF(EthernetDesc
, "Checksum is bad!!\n");
749 if (tcp
&& igbe
->regs
.rxcsum
.tuofld()) {
750 DPRINTF(EthernetDesc
, "Checking TCP checksum\n");
751 status
|= RXDS_TCPCS
;
752 desc
->csum
= htole(cksum(tcp
));
753 if (cksum(tcp
) != 0) {
754 DPRINTF(EthernetDesc
, "Checksum is bad!!\n");
760 if (udp
&& igbe
->regs
.rxcsum
.tuofld()) {
761 DPRINTF(EthernetDesc
, "Checking UDP checksum\n");
762 status
|= RXDS_UDPCS
;
763 desc
->csum
= htole(cksum(udp
));
764 if (cksum(udp
) != 0) {
765 DPRINTF(EthernetDesc
, "Checksum is bad!!\n");
770 DPRINTF(EthernetSM
, "Proccesing Non-Ip packet\n");
774 desc
->status
= htole(status
);
775 desc
->errors
= htole(err
);
777 // No vlan support at this point... just set it to 0
780 // Deal with the rx timer interrupts
781 if (igbe
->regs
.rdtr
.delay()) {
782 DPRINTF(EthernetSM
, "RXS: Scheduling DTR for %d\n",
783 igbe
->regs
.rdtr
.delay() * igbe
->intClock());
784 igbe
->rdtrEvent
.reschedule(curTick
+ igbe
->regs
.rdtr
.delay() *
785 igbe
->intClock(),true);
788 if (igbe
->regs
.radv
.idv() && igbe
->regs
.rdtr
.delay()) {
789 DPRINTF(EthernetSM
, "RXS: Scheduling ADV for %d\n",
790 igbe
->regs
.radv
.idv() * igbe
->intClock());
791 if (!igbe
->radvEvent
.scheduled()) {
792 igbe
->radvEvent
.schedule(curTick
+ igbe
->regs
.radv
.idv() *
797 // if neither radv or rdtr, maybe itr is set...
798 if (!igbe
->regs
.rdtr
.delay()) {
799 DPRINTF(EthernetSM
, "RXS: Receive interrupt delay disabled, posting IT_RXT\n");
800 igbe
->postInterrupt(IT_RXT
);
803 // If the packet is small enough, interrupt appropriately
804 // I wonder if this is delayed or not?!
805 if (pktPtr
->length
<= igbe
->regs
.rsrpd
.idv()) {
806 DPRINTF(EthernetSM
, "RXS: Posting IT_SRPD beacuse small packet received\n");
807 igbe
->postInterrupt(IT_SRPD
);
810 DPRINTF(EthernetDesc
, "Processing of this descriptor complete\n");
811 unusedCache
.pop_front();
812 usedCache
.push_back(desc
);
823 IGbE::RxDescCache::enableSm()
825 if (!igbe
->drainEvent
) {
827 igbe
->restartClock();
832 IGbE::RxDescCache::packetDone()
842 IGbE::RxDescCache::hasOutstandingEvents()
844 return pktEvent
.scheduled() || wbEvent
.scheduled() ||
845 fetchEvent
.scheduled();
849 IGbE::RxDescCache::serialize(std::ostream
&os
)
851 DescCache
<RxDesc
>::serialize(os
);
852 SERIALIZE_SCALAR(pktDone
);
856 IGbE::RxDescCache::unserialize(Checkpoint
*cp
, const std::string
§ion
)
858 DescCache
<RxDesc
>::unserialize(cp
, section
);
859 UNSERIALIZE_SCALAR(pktDone
);
863 ///////////////////////////////////// IGbE::TxDesc /////////////////////////////////
865 IGbE::TxDescCache::TxDescCache(IGbE
*i
, const std::string n
, int s
)
866 : DescCache
<TxDesc
>(i
,n
, s
), pktDone(false), isTcp(false), pktWaiting(false),
873 IGbE::TxDescCache::getPacketSize()
875 assert(unusedCache
.size());
879 DPRINTF(EthernetDesc
, "Starting processing of descriptor\n");
881 while (unusedCache
.size() && TxdOp::isContext(unusedCache
.front())) {
882 DPRINTF(EthernetDesc
, "Got context descriptor type... skipping\n");
884 // I think we can just ignore these for now?
885 desc
= unusedCache
.front();
886 DPRINTF(EthernetDesc
, "Descriptor upper: %#x lower: %#X\n", desc
->d1
,
888 // is this going to be a tcp or udp packet?
889 isTcp
= TxdOp::tcp(desc
) ? true : false;
891 // make sure it's ipv4
892 //assert(TxdOp::ip(desc));
895 unusedCache
.pop_front();
896 usedCache
.push_back(desc
);
899 if (!unusedCache
.size())
902 DPRINTF(EthernetDesc
, "Next TX packet is %d bytes\n",
903 TxdOp::getLen(unusedCache
.front()));
905 return TxdOp::getLen(unusedCache
.front());
909 IGbE::TxDescCache::getPacketData(EthPacketPtr p
)
911 assert(unusedCache
.size());
914 desc
= unusedCache
.front();
916 assert((TxdOp::isLegacy(desc
) || TxdOp::isData(desc
)) && TxdOp::getLen(desc
));
922 DPRINTF(EthernetDesc
, "Starting DMA of packet at offset %d\n", p
->length
);
923 igbe
->dmaRead(igbe
->platform
->pciToDma(TxdOp::getBuf(desc
)),
924 TxdOp::getLen(desc
), &pktEvent
, p
->data
+ p
->length
);
930 IGbE::TxDescCache::pktComplete()
934 assert(unusedCache
.size());
937 DPRINTF(EthernetDesc
, "DMA of packet complete\n");
940 desc
= unusedCache
.front();
941 assert((TxdOp::isLegacy(desc
) || TxdOp::isData(desc
)) && TxdOp::getLen(desc
));
943 DPRINTF(EthernetDesc
, "TxDescriptor data d1: %#llx d2: %#llx\n", desc
->d1
, desc
->d2
);
945 if (!TxdOp::eop(desc
)) {
946 pktPtr
->length
+= TxdOp::getLen(desc
);
947 unusedCache
.pop_front();
948 usedCache
.push_back(desc
);
953 DPRINTF(EthernetDesc
, "Partial Packet Descriptor of %d bytes Done\n",
961 pktMultiDesc
= false;
963 // Set the length of the data in the EtherPacket
964 pktPtr
->length
+= TxdOp::getLen(desc
);
966 // no support for vlans
967 assert(!TxdOp::vle(desc
));
969 // we alway report status
970 assert(TxdOp::rs(desc
));
972 // we only support single packet descriptors at this point
973 assert(TxdOp::eop(desc
));
975 // set that this packet is done
978 DPRINTF(EthernetDesc
, "TxDescriptor data d1: %#llx d2: %#llx\n", desc
->d1
, desc
->d2
);
980 if (DTRACE(EthernetDesc
)) {
983 DPRINTF(EthernetDesc
, "Proccesing Ip packet with Id=%d\n",
986 DPRINTF(EthernetSM
, "Proccesing Non-Ip packet\n");
989 // Checksums are only ofloaded for new descriptor types
990 if (TxdOp::isData(desc
) && ( TxdOp::ixsm(desc
) || TxdOp::txsm(desc
)) ) {
991 DPRINTF(EthernetDesc
, "Calculating checksums for packet\n");
994 if (TxdOp::ixsm(desc
)) {
997 DPRINTF(EthernetDesc
, "Calculated IP checksum\n");
999 if (TxdOp::txsm(desc
)) {
1004 tcp
->sum(cksum(tcp
));
1005 DPRINTF(EthernetDesc
, "Calculated TCP checksum\n");
1009 udp
->sum(cksum(udp
));
1010 DPRINTF(EthernetDesc
, "Calculated UDP checksum\n");
1012 panic("Told to checksum, but don't know how\n");
1017 if (TxdOp::ide(desc
)) {
1018 // Deal with the rx timer interrupts
1019 DPRINTF(EthernetDesc
, "Descriptor had IDE set\n");
1020 if (igbe
->regs
.tidv
.idv()) {
1021 DPRINTF(EthernetDesc
, "setting tidv\n");
1022 igbe
->tidvEvent
.reschedule(curTick
+ igbe
->regs
.tidv
.idv() *
1023 igbe
->intClock(), true);
1026 if (igbe
->regs
.tadv
.idv() && igbe
->regs
.tidv
.idv()) {
1027 DPRINTF(EthernetDesc
, "setting tadv\n");
1028 if (!igbe
->tadvEvent
.scheduled()) {
1029 igbe
->tadvEvent
.schedule(curTick
+ igbe
->regs
.tadv
.idv() *
1037 unusedCache
.pop_front();
1038 usedCache
.push_back(desc
);
1043 DPRINTF(EthernetDesc
, "Descriptor Done\n");
1045 if (igbe
->regs
.txdctl
.wthresh() == 0) {
1046 DPRINTF(EthernetDesc
, "WTHRESH == 0, writing back descriptor\n");
1048 } else if (igbe
->regs
.txdctl
.wthresh() >= usedCache
.size()) {
1049 DPRINTF(EthernetDesc
, "used > WTHRESH, writing back descriptor\n");
1050 writeback((igbe
->cacheBlockSize()-1)>>4);
1057 IGbE::TxDescCache::serialize(std::ostream
&os
)
1059 DescCache
<TxDesc
>::serialize(os
);
1060 SERIALIZE_SCALAR(pktDone
);
1061 SERIALIZE_SCALAR(isTcp
);
1062 SERIALIZE_SCALAR(pktWaiting
);
1063 SERIALIZE_SCALAR(pktMultiDesc
);
1067 IGbE::TxDescCache::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1069 DescCache
<TxDesc
>::unserialize(cp
, section
);
1070 UNSERIALIZE_SCALAR(pktDone
);
1071 UNSERIALIZE_SCALAR(isTcp
);
1072 UNSERIALIZE_SCALAR(pktWaiting
);
1073 UNSERIALIZE_SCALAR(pktMultiDesc
);
1077 IGbE::TxDescCache::packetAvailable()
1087 IGbE::TxDescCache::enableSm()
1089 if (!igbe
->drainEvent
) {
1090 igbe
->txTick
= true;
1091 igbe
->restartClock();
1096 IGbE::TxDescCache::hasOutstandingEvents()
1098 return pktEvent
.scheduled() || wbEvent
.scheduled() ||
1099 fetchEvent
.scheduled();
1103 ///////////////////////////////////// IGbE /////////////////////////////////
1106 IGbE::restartClock()
1108 if (!tickEvent
.scheduled() && (rxTick
|| txTick
|| txFifoTick
) && getState() ==
1110 tickEvent
.schedule((curTick
/ticks(1)) * ticks(1) + ticks(1));
1114 IGbE::drain(Event
*de
)
1117 count
= pioPort
->drain(de
) + dmaPort
->drain(de
);
1118 if (rxDescCache
.hasOutstandingEvents() ||
1119 txDescCache
.hasOutstandingEvents()) {
1128 if (tickEvent
.scheduled())
1129 tickEvent
.deschedule();
1132 changeState(Draining
);
1134 changeState(Drained
);
1142 SimObject::resume();
1160 if (!rxDescCache
.hasOutstandingEvents() &&
1161 !txDescCache
.hasOutstandingEvents()) {
1162 drainEvent
->process();
1168 IGbE::txStateMachine()
1170 if (!regs
.tctl
.en()) {
1172 DPRINTF(EthernetSM
, "TXS: TX disabled, stopping ticking\n");
1176 // If we have a packet available and it's length is not 0 (meaning it's not
1177 // a multidescriptor packet) put it in the fifo, otherwise an the next
1178 // iteration we'll get the rest of the data
1179 if (txPacket
&& txDescCache
.packetAvailable()
1180 && !txDescCache
.packetMultiDesc() && txPacket
->length
) {
1183 DPRINTF(EthernetSM
, "TXS: packet placed in TX FIFO\n");
1184 success
= txFifo
.push(txPacket
);
1185 txFifoTick
= true && !drainEvent
;
1188 txDescCache
.writeback((cacheBlockSize()-1)>>4);
1192 // Only support descriptor granularity
1193 assert(regs
.txdctl
.gran());
1194 if (regs
.txdctl
.lwthresh() && txDescCache
.descLeft() < (regs
.txdctl
.lwthresh() * 8)) {
1195 DPRINTF(EthernetSM
, "TXS: LWTHRESH caused posting of TXDLOW\n");
1196 postInterrupt(IT_TXDLOW
);
1200 txPacket
= new EthPacketData(16384);
1203 if (!txDescCache
.packetWaiting()) {
1204 if (txDescCache
.descLeft() == 0) {
1205 postInterrupt(IT_TXQE
);
1206 txDescCache
.writeback(0);
1207 txDescCache
.fetchDescriptors();
1208 DPRINTF(EthernetSM
, "TXS: No descriptors left in ring, forcing "
1209 "writeback stopping ticking and posting TXQE\n");
1215 if (!(txDescCache
.descUnused())) {
1216 txDescCache
.fetchDescriptors();
1217 DPRINTF(EthernetSM
, "TXS: No descriptors available in cache, fetching and stopping ticking\n");
1224 size
= txDescCache
.getPacketSize();
1225 if (size
> 0 && txFifo
.avail() > size
) {
1226 DPRINTF(EthernetSM
, "TXS: Reserving %d bytes in FIFO and begining "
1227 "DMA of next packet\n", size
);
1228 txFifo
.reserve(size
);
1229 txDescCache
.getPacketData(txPacket
);
1230 } else if (size
<= 0) {
1231 DPRINTF(EthernetSM
, "TXS: getPacketSize returned: %d\n", size
);
1232 DPRINTF(EthernetSM
, "TXS: No packets to get, writing back used descriptors\n");
1233 txDescCache
.writeback(0);
1235 DPRINTF(EthernetSM
, "TXS: FIFO full, stopping ticking until space "
1236 "available in FIFO\n");
1243 DPRINTF(EthernetSM
, "TXS: Nothing to do, stopping ticking\n");
1248 IGbE::ethRxPkt(EthPacketPtr pkt
)
1250 DPRINTF(Ethernet
, "RxFIFO: Receiving pcakte from wire\n");
1252 if (!regs
.rctl
.en()) {
1253 DPRINTF(Ethernet
, "RxFIFO: RX not enabled, dropping\n");
1257 // restart the state machines if they are stopped
1258 rxTick
= true && !drainEvent
;
1259 if ((rxTick
|| txTick
) && !tickEvent
.scheduled()) {
1260 DPRINTF(EthernetSM
, "RXS: received packet into fifo, starting ticking\n");
1264 if (!rxFifo
.push(pkt
)) {
1265 DPRINTF(Ethernet
, "RxFIFO: Packet won't fit in fifo... dropped\n");
1266 postInterrupt(IT_RXO
, true);
1275 IGbE::rxStateMachine()
1277 if (!regs
.rctl
.en()) {
1279 DPRINTF(EthernetSM
, "RXS: RX disabled, stopping ticking\n");
1283 // If the packet is done check for interrupts/descriptors/etc
1284 if (rxDescCache
.packetDone()) {
1285 rxDmaPacket
= false;
1286 DPRINTF(EthernetSM
, "RXS: Packet completed DMA to memory\n");
1287 int descLeft
= rxDescCache
.descLeft();
1288 switch (regs
.rctl
.rdmts()) {
1289 case 2: if (descLeft
> .125 * regs
.rdlen()) break;
1290 case 1: if (descLeft
> .250 * regs
.rdlen()) break;
1291 case 0: if (descLeft
> .500 * regs
.rdlen()) break;
1292 DPRINTF(Ethernet
, "RXS: Interrupting (RXDMT) because of descriptors left\n");
1293 postInterrupt(IT_RXDMT
);
1297 if (descLeft
== 0) {
1298 rxDescCache
.writeback(0);
1299 DPRINTF(EthernetSM
, "RXS: No descriptors left in ring, forcing"
1300 " writeback and stopping ticking\n");
1304 // only support descriptor granulaties
1305 assert(regs
.rxdctl
.gran());
1307 if (regs
.rxdctl
.wthresh() >= rxDescCache
.descUsed()) {
1308 DPRINTF(EthernetSM
, "RXS: Writing back because WTHRESH >= descUsed\n");
1309 if (regs
.rxdctl
.wthresh() < (cacheBlockSize()>>4))
1310 rxDescCache
.writeback(regs
.rxdctl
.wthresh()-1);
1312 rxDescCache
.writeback((cacheBlockSize()-1)>>4);
1315 if ((rxDescCache
.descUnused() < regs
.rxdctl
.pthresh()) &&
1316 ((rxDescCache
.descLeft() - rxDescCache
.descUnused()) > regs
.rxdctl
.hthresh())) {
1317 DPRINTF(EthernetSM
, "RXS: Fetching descriptors because descUnused < PTHRESH\n");
1318 rxDescCache
.fetchDescriptors();
1321 if (rxDescCache
.descUnused() == 0) {
1322 rxDescCache
.fetchDescriptors();
1323 DPRINTF(EthernetSM
, "RXS: No descriptors available in cache, "
1324 "fetching descriptors and stopping ticking\n");
1331 DPRINTF(EthernetSM
, "RXS: stopping ticking until packet DMA completes\n");
1336 if (!rxDescCache
.descUnused()) {
1337 rxDescCache
.fetchDescriptors();
1338 DPRINTF(EthernetSM
, "RXS: No descriptors available in cache, stopping ticking\n");
1340 DPRINTF(EthernetSM
, "RXS: No descriptors available, fetching\n");
1344 if (rxFifo
.empty()) {
1345 DPRINTF(EthernetSM
, "RXS: RxFIFO empty, stopping ticking\n");
1351 pkt
= rxFifo
.front();
1354 rxDescCache
.writePacket(pkt
);
1355 DPRINTF(EthernetSM
, "RXS: Writing packet into memory\n");
1356 DPRINTF(EthernetSM
, "RXS: Removing packet from FIFO\n");
1358 DPRINTF(EthernetSM
, "RXS: stopping ticking until packet DMA completes\n");
1366 if (txFifo
.empty()) {
1372 if (etherInt
->sendPacket(txFifo
.front())) {
1373 if (DTRACE(EthernetSM
)) {
1374 IpPtr
ip(txFifo
.front());
1376 DPRINTF(EthernetSM
, "Transmitting Ip packet with Id=%d\n",
1379 DPRINTF(EthernetSM
, "Transmitting Non-Ip packet\n");
1381 DPRINTF(EthernetSM
, "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
1385 // We'll get woken up when the packet ethTxDone() gets called
1393 DPRINTF(EthernetSM
, "IGbE: -------------- Cycle --------------\n");
1405 if (rxTick
|| txTick
|| txFifoTick
)
1406 tickEvent
.schedule(curTick
+ ticks(1));
1412 // restart the tx state machines if they are stopped
1413 // fifo to send another packet
1414 // tx sm to put more data into the fifo
1415 txFifoTick
= true && !drainEvent
;
1416 if (txDescCache
.descLeft() != 0 && !drainEvent
)
1421 DPRINTF(EthernetSM
, "TxFIFO: Transmission complete\n");
1425 IGbE::serialize(std::ostream
&os
)
1427 PciDev::serialize(os
);
1430 SERIALIZE_SCALAR(eeOpBits
);
1431 SERIALIZE_SCALAR(eeAddrBits
);
1432 SERIALIZE_SCALAR(eeDataBits
);
1433 SERIALIZE_SCALAR(eeOpcode
);
1434 SERIALIZE_SCALAR(eeAddr
);
1435 SERIALIZE_ARRAY(flash
,iGbReg::EEPROM_SIZE
);
1437 rxFifo
.serialize("rxfifo", os
);
1438 txFifo
.serialize("txfifo", os
);
1440 bool txPktExists
= txPacket
;
1441 SERIALIZE_SCALAR(txPktExists
);
1443 txPacket
->serialize("txpacket", os
);
1445 Tick rdtr_time
= 0, radv_time
= 0, tidv_time
= 0, tadv_time
= 0,
1448 if (rdtrEvent
.scheduled())
1449 rdtr_time
= rdtrEvent
.when();
1450 SERIALIZE_SCALAR(rdtr_time
);
1452 if (radvEvent
.scheduled())
1453 radv_time
= radvEvent
.when();
1454 SERIALIZE_SCALAR(radv_time
);
1456 if (tidvEvent
.scheduled())
1457 tidv_time
= tidvEvent
.when();
1458 SERIALIZE_SCALAR(tidv_time
);
1460 if (tadvEvent
.scheduled())
1461 tadv_time
= tadvEvent
.when();
1462 SERIALIZE_SCALAR(tadv_time
);
1464 if (interEvent
.scheduled())
1465 inter_time
= interEvent
.when();
1466 SERIALIZE_SCALAR(inter_time
);
1468 nameOut(os
, csprintf("%s.TxDescCache", name()));
1469 txDescCache
.serialize(os
);
1471 nameOut(os
, csprintf("%s.RxDescCache", name()));
1472 rxDescCache
.serialize(os
);
1476 IGbE::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1478 PciDev::unserialize(cp
, section
);
1480 regs
.unserialize(cp
, section
);
1481 UNSERIALIZE_SCALAR(eeOpBits
);
1482 UNSERIALIZE_SCALAR(eeAddrBits
);
1483 UNSERIALIZE_SCALAR(eeDataBits
);
1484 UNSERIALIZE_SCALAR(eeOpcode
);
1485 UNSERIALIZE_SCALAR(eeAddr
);
1486 UNSERIALIZE_ARRAY(flash
,iGbReg::EEPROM_SIZE
);
1488 rxFifo
.unserialize("rxfifo", cp
, section
);
1489 txFifo
.unserialize("txfifo", cp
, section
);
1492 UNSERIALIZE_SCALAR(txPktExists
);
1494 txPacket
= new EthPacketData(16384);
1495 txPacket
->unserialize("txpacket", cp
, section
);
1502 Tick rdtr_time
, radv_time
, tidv_time
, tadv_time
, inter_time
;
1503 UNSERIALIZE_SCALAR(rdtr_time
);
1504 UNSERIALIZE_SCALAR(radv_time
);
1505 UNSERIALIZE_SCALAR(tidv_time
);
1506 UNSERIALIZE_SCALAR(tadv_time
);
1507 UNSERIALIZE_SCALAR(inter_time
);
1510 rdtrEvent
.schedule(rdtr_time
);
1513 radvEvent
.schedule(radv_time
);
1516 tidvEvent
.schedule(tidv_time
);
1519 tadvEvent
.schedule(tadv_time
);
1522 interEvent
.schedule(inter_time
);
1524 txDescCache
.unserialize(cp
, csprintf("%s.TxDescCache", section
));
1526 rxDescCache
.unserialize(cp
, csprintf("%s.RxDescCache", section
));
1530 IGbEParams::create()
1532 return new IGbE(this);