2 * Copyright (c) 2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * Device model for Intel's 8254x line of gigabit ethernet controllers.
33 * In particular an 82547 revision 2 (82547GI) MAC because it seems to have the
34 * fewest workarounds in the driver. It will probably work with most of the
35 * other MACs with slight modifications.
40 * @todo really there are multiple dma engines.. we should implement them.
45 #include "base/inet.hh"
46 #include "base/trace.hh"
47 #include "dev/i8254xGBe.hh"
48 #include "mem/packet.hh"
49 #include "mem/packet_access.hh"
50 #include "params/IGbE.hh"
51 #include "params/IGbEInt.hh"
52 #include "sim/stats.hh"
53 #include "sim/system.hh"
55 using namespace iGbReg
;
59 : PciDev(p
), etherInt(NULL
), drainEvent(NULL
), useFlowControl(p
->use_flow_control
),
60 rxFifo(p
->rx_fifo_size
), txFifo(p
->tx_fifo_size
), rxTick(false),
61 txTick(false), txFifoTick(false), rdtrEvent(this), radvEvent(this),
62 tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
63 rxDescCache(this, name()+".RxDesc", p
->rx_desc_cache_size
),
64 txDescCache(this, name()+".TxDesc", p
->tx_desc_cache_size
), clock(p
->clock
)
66 // Initialized internal registers per Intel documentation
67 // All registers intialized to 0 by per register constructor
72 regs
.sts
.speed(3); // Say we're 1000Mbps
73 regs
.sts
.fd(1); // full duplex
74 regs
.sts
.lu(1); // link up
80 regs
.rxdctl
.wthresh(1);
91 // clear all 64 16 bit words of the eeprom
92 memset(&flash
, 0, EEPROM_SIZE
*2);
94 // Set the MAC address
95 memcpy(flash
, p
->hardware_address
.bytes(), ETH_ADDR_LEN
);
96 for (int x
= 0; x
< ETH_ADDR_LEN
/2; x
++)
97 flash
[x
] = htobe(flash
[x
]);
100 for (int x
= 0; x
< EEPROM_SIZE
; x
++)
101 csum
+= htobe(flash
[x
]);
104 // Magic happy checksum value
105 flash
[EEPROM_SIZE
-1] = htobe((uint16_t)(EEPROM_CSUM
- csum
));
113 IGbE::writeConfig(PacketPtr pkt
)
115 int offset
= pkt
->getAddr() & PCI_CONFIG_SIZE
;
116 if (offset
< PCI_DEVICE_SPECIFIC
)
117 PciDev::writeConfig(pkt
);
119 panic("Device specific PCI config space not implemented.\n");
122 /// Some work may need to be done here based for the pci COMMAND bits.
129 IGbE::read(PacketPtr pkt
)
134 if (!getBAR(pkt
->getAddr(), bar
, daddr
))
135 panic("Invalid PCI memory access to unmapped memory.\n");
137 // Only Memory register BAR is allowed
140 // Only 32bit accesses allowed
141 assert(pkt
->getSize() == 4);
143 DPRINTF(Ethernet
, "Read device register %#X\n", daddr
);
148 /// Handle read of register here
154 pkt
->set
<uint32_t>(regs
.ctrl());
157 pkt
->set
<uint32_t>(regs
.sts());
160 pkt
->set
<uint32_t>(regs
.eecd());
163 pkt
->set
<uint32_t>(regs
.eerd());
166 pkt
->set
<uint32_t>(regs
.ctrl_ext());
169 pkt
->set
<uint32_t>(regs
.mdic());
172 DPRINTF(Ethernet
, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", regs
.icr(),
173 regs
.imr
, regs
.iam
, regs
.ctrl_ext
.iame());
174 pkt
->set
<uint32_t>(regs
.icr());
175 if (regs
.icr
.int_assert() || regs
.imr
== 0) {
176 regs
.icr
= regs
.icr() & ~mask(30);
177 DPRINTF(Ethernet
, "Cleared ICR. ICR=%#x\n", regs
.icr());
179 if (regs
.ctrl_ext
.iame() && regs
.icr
.int_assert())
180 regs
.imr
&= ~regs
.iam
;
184 pkt
->set
<uint32_t>(regs
.itr());
187 pkt
->set
<uint32_t>(regs
.rctl());
190 pkt
->set
<uint32_t>(regs
.fcttv());
193 pkt
->set
<uint32_t>(regs
.tctl());
196 pkt
->set
<uint32_t>(regs
.pba());
200 pkt
->set
<uint32_t>(0); // We don't care, so just return 0
203 pkt
->set
<uint32_t>(regs
.fcrtl());
206 pkt
->set
<uint32_t>(regs
.fcrth());
209 pkt
->set
<uint32_t>(regs
.rdba
.rdbal());
212 pkt
->set
<uint32_t>(regs
.rdba
.rdbah());
215 pkt
->set
<uint32_t>(regs
.rdlen());
218 pkt
->set
<uint32_t>(regs
.rdh());
221 pkt
->set
<uint32_t>(regs
.rdt());
224 pkt
->set
<uint32_t>(regs
.rdtr());
225 if (regs
.rdtr
.fpd()) {
226 rxDescCache
.writeback(0);
227 DPRINTF(EthernetIntr
, "Posting interrupt because of RDTR.FPD write\n");
228 postInterrupt(IT_RXT
);
233 pkt
->set
<uint32_t>(regs
.radv());
236 pkt
->set
<uint32_t>(regs
.tdba
.tdbal());
239 pkt
->set
<uint32_t>(regs
.tdba
.tdbah());
242 pkt
->set
<uint32_t>(regs
.tdlen());
245 pkt
->set
<uint32_t>(regs
.tdh());
248 pkt
->set
<uint32_t>(regs
.tdt());
251 pkt
->set
<uint32_t>(regs
.tidv());
254 pkt
->set
<uint32_t>(regs
.txdctl());
257 pkt
->set
<uint32_t>(regs
.tadv());
260 pkt
->set
<uint32_t>(regs
.rxcsum());
263 pkt
->set
<uint32_t>(regs
.manc());
266 if (!(daddr
>= REG_VFTA
&& daddr
< (REG_VFTA
+ VLAN_FILTER_TABLE_SIZE
*4)) &&
267 !(daddr
>= REG_RAL
&& daddr
< (REG_RAL
+ RCV_ADDRESS_TABLE_SIZE
*8)) &&
268 !(daddr
>= REG_MTA
&& daddr
< (REG_MTA
+ MULTICAST_TABLE_SIZE
*4)) &&
269 !(daddr
>= REG_CRCERRS
&& daddr
< (REG_CRCERRS
+ STATS_REGS_SIZE
)))
270 panic("Read request to unknown register number: %#x\n", daddr
);
272 pkt
->set
<uint32_t>(0);
275 pkt
->makeAtomicResponse();
280 IGbE::write(PacketPtr pkt
)
286 if (!getBAR(pkt
->getAddr(), bar
, daddr
))
287 panic("Invalid PCI memory access to unmapped memory.\n");
289 // Only Memory register BAR is allowed
292 // Only 32bit accesses allowed
293 assert(pkt
->getSize() == sizeof(uint32_t));
295 DPRINTF(Ethernet
, "Wrote device register %#X value %#X\n", daddr
, pkt
->get
<uint32_t>());
298 /// Handle write of register here
300 uint32_t val
= pkt
->get
<uint32_t>();
308 if (regs
.ctrl
.tfce())
309 warn("TX Flow control enabled, should implement\n");
310 if (regs
.ctrl
.rfce())
311 warn("RX Flow control enabled, should implement\n");
321 oldClk
= regs
.eecd
.sk();
323 // See if this is a eeprom access and emulate accordingly
324 if (!oldClk
&& regs
.eecd
.sk()) {
326 eeOpcode
= eeOpcode
<< 1 | regs
.eecd
.din();
328 } else if (eeAddrBits
< 8 && eeOpcode
== EEPROM_READ_OPCODE_SPI
) {
329 eeAddr
= eeAddr
<< 1 | regs
.eecd
.din();
331 } else if (eeDataBits
< 16 && eeOpcode
== EEPROM_READ_OPCODE_SPI
) {
332 assert(eeAddr
>>1 < EEPROM_SIZE
);
333 DPRINTF(EthernetEEPROM
, "EEPROM bit read: %d word: %#X\n",
334 flash
[eeAddr
>>1] >> eeDataBits
& 0x1, flash
[eeAddr
>>1]);
335 regs
.eecd
.dout((flash
[eeAddr
>>1] >> (15-eeDataBits
)) & 0x1);
337 } else if (eeDataBits
< 8 && eeOpcode
== EEPROM_RDSR_OPCODE_SPI
) {
341 panic("What's going on with eeprom interface? opcode:"
342 " %#x:%d addr: %#x:%d, data: %d\n", (uint32_t)eeOpcode
,
343 (uint32_t)eeOpBits
, (uint32_t)eeAddr
,
344 (uint32_t)eeAddrBits
, (uint32_t)eeDataBits
);
346 // Reset everything for the next command
347 if ((eeDataBits
== 16 && eeOpcode
== EEPROM_READ_OPCODE_SPI
) ||
348 (eeDataBits
== 8 && eeOpcode
== EEPROM_RDSR_OPCODE_SPI
)) {
356 DPRINTF(EthernetEEPROM
, "EEPROM: opcode: %#X:%d addr: %#X:%d\n",
357 (uint32_t)eeOpcode
, (uint32_t) eeOpBits
,
358 (uint32_t)eeAddr
>>1, (uint32_t)eeAddrBits
);
359 if (eeOpBits
== 8 && !(eeOpcode
== EEPROM_READ_OPCODE_SPI
||
360 eeOpcode
== EEPROM_RDSR_OPCODE_SPI
))
361 panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode
,
366 // If driver requests eeprom access, immediately give it to it
367 regs
.eecd
.ee_gnt(regs
.eecd
.ee_req());
375 panic("No support for interrupt on mdic complete\n");
376 if (regs
.mdic
.phyadd() != 1)
377 panic("No support for reading anything but phy\n");
378 DPRINTF(Ethernet
, "%s phy address %x\n", regs
.mdic
.op() == 1 ? "Writing"
379 : "Reading", regs
.mdic
.regadd());
380 switch (regs
.mdic
.regadd()) {
382 regs
.mdic
.data(0x796D); // link up
385 regs
.mdic
.data(0x02A8);
388 regs
.mdic
.data(0x0380);
391 regs
.mdic
.data(0x7C00);
394 regs
.mdic
.data(0x3000);
397 regs
.mdic
.data(0x180); // some random length
405 DPRINTF(Ethernet
, "Writing ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n", regs
.icr(),
406 regs
.imr
, regs
.iam
, regs
.ctrl_ext
.iame());
407 if (regs
.ctrl_ext
.iame())
408 regs
.imr
&= ~regs
.iam
;
409 regs
.icr
= ~bits(val
,30,0) & regs
.icr();
416 DPRINTF(EthernetIntr
, "Posting interrupt because of ICS write\n");
417 postInterrupt((IntTypes
)val
);
433 if (regs
.rctl
.rst()) {
435 DPRINTF(EthernetSM
, "RXS: Got RESET!\n");
453 if (regs
.tctl
.en() && !oldtctl
.en()) {
459 regs
.pba
.txa(64 - regs
.pba
.rxa());
469 ; // We don't care, so don't store anything
478 regs
.rdba
.rdbal( val
& ~mask(4));
479 rxDescCache
.areaChanged();
482 regs
.rdba
.rdbah(val
);
483 rxDescCache
.areaChanged();
486 regs
.rdlen
= val
& ~mask(7);
487 rxDescCache
.areaChanged();
491 rxDescCache
.areaChanged();
505 regs
.tdba
.tdbal( val
& ~mask(4));
506 txDescCache
.areaChanged();
509 regs
.tdba
.tdbah(val
);
510 txDescCache
.areaChanged();
513 regs
.tdlen
= val
& ~mask(7);
514 txDescCache
.areaChanged();
518 txDescCache
.areaChanged();
541 if (!(daddr
>= REG_VFTA
&& daddr
< (REG_VFTA
+ VLAN_FILTER_TABLE_SIZE
*4)) &&
542 !(daddr
>= REG_RAL
&& daddr
< (REG_RAL
+ RCV_ADDRESS_TABLE_SIZE
*8)) &&
543 !(daddr
>= REG_MTA
&& daddr
< (REG_MTA
+ MULTICAST_TABLE_SIZE
*4)))
544 panic("Write request to unknown register number: %#x\n", daddr
);
547 pkt
->makeAtomicResponse();
552 IGbE::postInterrupt(IntTypes t
, bool now
)
556 // Interrupt is already pending
560 if (regs
.icr() & regs
.imr
)
562 regs
.icr
= regs
.icr() | t
;
563 if (!interEvent
.scheduled())
564 interEvent
.schedule(curTick
+ Clock::Int::ns
* 256 *
565 regs
.itr
.interval());
567 regs
.icr
= regs
.icr() | t
;
568 if (regs
.itr
.interval() == 0 || now
) {
569 if (interEvent
.scheduled())
570 interEvent
.deschedule();
573 DPRINTF(EthernetIntr
, "EINT: Scheduling timer interrupt for %d ticks\n",
574 Clock::Int::ns
* 256 * regs
.itr
.interval());
575 if (!interEvent
.scheduled())
576 interEvent
.schedule(curTick
+ Clock::Int::ns
* 256 * regs
.itr
.interval());
584 if (rdtrEvent
.scheduled()) {
586 rdtrEvent
.deschedule();
588 if (radvEvent
.scheduled()) {
590 radvEvent
.deschedule();
592 if (tadvEvent
.scheduled()) {
594 tadvEvent
.deschedule();
596 if (tidvEvent
.scheduled()) {
598 tidvEvent
.deschedule();
601 regs
.icr
.int_assert(1);
602 DPRINTF(EthernetIntr
, "EINT: Posting interrupt to CPU now. Vector %#x\n",
610 if (regs
.icr
.int_assert()) {
611 regs
.icr
.int_assert(0);
612 DPRINTF(EthernetIntr
, "EINT: Clearing interrupt to CPU now. Vector %#x\n",
621 // Check if we need to clear the cpu interrupt
622 if (!(regs
.icr() & regs
.imr
)) {
623 if (interEvent
.scheduled())
624 interEvent
.deschedule();
625 if (regs
.icr
.int_assert())
629 if (regs
.icr() & regs
.imr
) {
630 if (regs
.itr
.interval() == 0) {
633 if (!interEvent
.scheduled())
634 interEvent
.schedule(curTick
+ Clock::Int::ns
* 256 * regs
.itr
.interval());
642 IGbE::RxDescCache::RxDescCache(IGbE
*i
, const std::string n
, int s
)
643 : DescCache
<RxDesc
>(i
, n
, s
), pktDone(false), pktEvent(this)
649 IGbE::RxDescCache::writePacket(EthPacketPtr packet
)
651 // We shouldn't have to deal with any of these yet
652 DPRINTF(EthernetDesc
, "Packet Length: %d Desc Size: %d\n",
653 packet
->length
, igbe
->regs
.rctl
.descSize());
654 assert(packet
->length
< igbe
->regs
.rctl
.descSize());
656 if (!unusedCache
.size())
661 igbe
->dmaWrite(igbe
->platform
->pciToDma(unusedCache
.front()->buf
),
662 packet
->length
, &pktEvent
, packet
->data
);
667 IGbE::RxDescCache::pktComplete()
669 assert(unusedCache
.size());
671 desc
= unusedCache
.front();
673 uint16_t crcfixup
= igbe
->regs
.rctl
.secrc() ? 0 : 4 ;
674 desc
->len
= htole((uint16_t)(pktPtr
->length
+ crcfixup
));
675 DPRINTF(EthernetDesc
, "pktPtr->length: %d stripcrc offset: %d value written: %d %d\n",
676 pktPtr
->length
, crcfixup
,
677 htole((uint16_t)(pktPtr
->length
+ crcfixup
)),
678 (uint16_t)(pktPtr
->length
+ crcfixup
));
680 // no support for anything but starting at 0
681 assert(igbe
->regs
.rxcsum
.pcss() == 0);
683 DPRINTF(EthernetDesc
, "Packet written to memory updating Descriptor\n");
685 uint8_t status
= RXDS_DD
| RXDS_EOP
;
691 DPRINTF(EthernetDesc
, "Proccesing Ip packet with Id=%d\n", ip
->id());
693 if (igbe
->regs
.rxcsum
.ipofld()) {
694 DPRINTF(EthernetDesc
, "Checking IP checksum\n");
696 desc
->csum
= htole(cksum(ip
));
697 if (cksum(ip
) != 0) {
699 DPRINTF(EthernetDesc
, "Checksum is bad!!\n");
703 if (tcp
&& igbe
->regs
.rxcsum
.tuofld()) {
704 DPRINTF(EthernetDesc
, "Checking TCP checksum\n");
705 status
|= RXDS_TCPCS
;
706 desc
->csum
= htole(cksum(tcp
));
707 if (cksum(tcp
) != 0) {
708 DPRINTF(EthernetDesc
, "Checksum is bad!!\n");
714 if (udp
&& igbe
->regs
.rxcsum
.tuofld()) {
715 DPRINTF(EthernetDesc
, "Checking UDP checksum\n");
716 status
|= RXDS_UDPCS
;
717 desc
->csum
= htole(cksum(udp
));
718 if (cksum(udp
) != 0) {
719 DPRINTF(EthernetDesc
, "Checksum is bad!!\n");
724 DPRINTF(EthernetSM
, "Proccesing Non-Ip packet\n");
728 desc
->status
= htole(status
);
729 desc
->errors
= htole(err
);
731 // No vlan support at this point... just set it to 0
734 // Deal with the rx timer interrupts
735 if (igbe
->regs
.rdtr
.delay()) {
736 DPRINTF(EthernetSM
, "RXS: Scheduling DTR for %d\n",
737 igbe
->regs
.rdtr
.delay() * igbe
->intClock());
738 igbe
->rdtrEvent
.reschedule(curTick
+ igbe
->regs
.rdtr
.delay() *
739 igbe
->intClock(),true);
742 if (igbe
->regs
.radv
.idv() && igbe
->regs
.rdtr
.delay()) {
743 DPRINTF(EthernetSM
, "RXS: Scheduling ADV for %d\n",
744 igbe
->regs
.radv
.idv() * igbe
->intClock());
745 if (!igbe
->radvEvent
.scheduled())
746 igbe
->radvEvent
.schedule(curTick
+ igbe
->regs
.radv
.idv() *
750 // if neither radv or rdtr, maybe itr is set...
751 if (!igbe
->regs
.rdtr
.delay()) {
752 DPRINTF(EthernetSM
, "RXS: Receive interrupt delay disabled, posting IT_RXT\n");
753 igbe
->postInterrupt(IT_RXT
);
756 // If the packet is small enough, interrupt appropriately
757 // I wonder if this is delayed or not?!
758 if (pktPtr
->length
<= igbe
->regs
.rsrpd
.idv()) {
759 DPRINTF(EthernetSM
, "RXS: Posting IT_SRPD beacuse small packet received\n");
760 igbe
->postInterrupt(IT_SRPD
);
763 DPRINTF(EthernetDesc
, "Processing of this descriptor complete\n");
764 unusedCache
.pop_front();
765 usedCache
.push_back(desc
);
773 IGbE::RxDescCache::enableSm()
776 igbe
->restartClock();
780 IGbE::RxDescCache::packetDone()
790 IGbE::RxDescCache::hasOutstandingEvents()
792 return pktEvent
.scheduled() || wbEvent
.scheduled() ||
793 fetchEvent
.scheduled();
797 IGbE::RxDescCache::serialize(std::ostream
&os
)
799 DescCache
<RxDesc
>::serialize(os
);
800 SERIALIZE_SCALAR(pktDone
);
804 IGbE::RxDescCache::unserialize(Checkpoint
*cp
, const std::string
§ion
)
806 DescCache
<RxDesc
>::unserialize(cp
, section
);
807 UNSERIALIZE_SCALAR(pktDone
);
811 ///////////////////////////////////// IGbE::TxDesc /////////////////////////////////
813 IGbE::TxDescCache::TxDescCache(IGbE
*i
, const std::string n
, int s
)
814 : DescCache
<TxDesc
>(i
,n
, s
), pktDone(false), isTcp(false), pktWaiting(false),
821 IGbE::TxDescCache::getPacketSize()
823 assert(unusedCache
.size());
827 DPRINTF(EthernetDesc
, "Starting processing of descriptor\n");
829 while (unusedCache
.size() && TxdOp::isContext(unusedCache
.front())) {
830 DPRINTF(EthernetDesc
, "Got context descriptor type... skipping\n");
832 // I think we can just ignore these for now?
833 desc
= unusedCache
.front();
834 // is this going to be a tcp or udp packet?
835 isTcp
= TxdOp::tcp(desc
) ? true : false;
837 // make sure it's ipv4
838 assert(TxdOp::ip(desc
));
841 unusedCache
.pop_front();
842 usedCache
.push_back(desc
);
845 if (!unusedCache
.size())
848 DPRINTF(EthernetDesc
, "Next TX packet is %d bytes\n",
849 TxdOp::getLen(unusedCache
.front()));
851 return TxdOp::getLen(unusedCache
.front());
855 IGbE::TxDescCache::getPacketData(EthPacketPtr p
)
857 assert(unusedCache
.size());
860 desc
= unusedCache
.front();
862 assert((TxdOp::isLegacy(desc
) || TxdOp::isData(desc
)) && TxdOp::getLen(desc
));
868 DPRINTF(EthernetDesc
, "Starting DMA of packet\n");
869 igbe
->dmaRead(igbe
->platform
->pciToDma(TxdOp::getBuf(desc
)),
870 TxdOp::getLen(desc
), &pktEvent
, p
->data
+ p
->length
);
876 IGbE::TxDescCache::pktComplete()
880 assert(unusedCache
.size());
883 DPRINTF(EthernetDesc
, "DMA of packet complete\n");
886 desc
= unusedCache
.front();
887 assert((TxdOp::isLegacy(desc
) || TxdOp::isData(desc
)) && TxdOp::getLen(desc
));
889 DPRINTF(EthernetDesc
, "TxDescriptor data d1: %#llx d2: %#llx\n", desc
->d1
, desc
->d2
);
891 if (!TxdOp::eop(desc
)) {
892 // This only supports two descriptors per tx packet
893 assert(pktPtr
->length
== 0);
894 pktPtr
->length
= TxdOp::getLen(desc
);
895 unusedCache
.pop_front();
896 usedCache
.push_back(desc
);
901 DPRINTF(EthernetDesc
, "Partial Packet Descriptor Done\n");
906 // Set the length of the data in the EtherPacket
907 pktPtr
->length
+= TxdOp::getLen(desc
);
909 // no support for vlans
910 assert(!TxdOp::vle(desc
));
912 // we alway report status
913 assert(TxdOp::rs(desc
));
915 // we only support single packet descriptors at this point
916 assert(TxdOp::eop(desc
));
918 // set that this packet is done
921 DPRINTF(EthernetDesc
, "TxDescriptor data d1: %#llx d2: %#llx\n", desc
->d1
, desc
->d2
);
923 if (DTRACE(EthernetDesc
)) {
926 DPRINTF(EthernetDesc
, "Proccesing Ip packet with Id=%d\n",
929 DPRINTF(EthernetSM
, "Proccesing Non-Ip packet\n");
932 // Checksums are only ofloaded for new descriptor types
933 if (TxdOp::isData(desc
) && ( TxdOp::ixsm(desc
) || TxdOp::txsm(desc
)) ) {
934 DPRINTF(EthernetDesc
, "Calculating checksums for packet\n");
937 if (TxdOp::ixsm(desc
)) {
940 DPRINTF(EthernetDesc
, "Calculated IP checksum\n");
942 if (TxdOp::txsm(desc
)) {
947 tcp
->sum(cksum(tcp
));
948 DPRINTF(EthernetDesc
, "Calculated TCP checksum\n");
953 udp
->sum(cksum(udp
));
954 DPRINTF(EthernetDesc
, "Calculated UDP checksum\n");
959 if (TxdOp::ide(desc
)) {
960 // Deal with the rx timer interrupts
961 DPRINTF(EthernetDesc
, "Descriptor had IDE set\n");
962 if (igbe
->regs
.tidv
.idv()) {
963 DPRINTF(EthernetDesc
, "setting tidv\n");
964 igbe
->tidvEvent
.reschedule(curTick
+ igbe
->regs
.tidv
.idv() *
965 igbe
->intClock(), true);
968 if (igbe
->regs
.tadv
.idv() && igbe
->regs
.tidv
.idv()) {
969 DPRINTF(EthernetDesc
, "setting tadv\n");
970 if (!igbe
->tadvEvent
.scheduled())
971 igbe
->tadvEvent
.schedule(curTick
+ igbe
->regs
.tadv
.idv() *
978 unusedCache
.pop_front();
979 usedCache
.push_back(desc
);
984 DPRINTF(EthernetDesc
, "Descriptor Done\n");
986 if (igbe
->regs
.txdctl
.wthresh() == 0) {
987 DPRINTF(EthernetDesc
, "WTHRESH == 0, writing back descriptor\n");
989 } else if (igbe
->regs
.txdctl
.wthresh() >= usedCache
.size()) {
990 DPRINTF(EthernetDesc
, "used > WTHRESH, writing back descriptor\n");
991 writeback((igbe
->cacheBlockSize()-1)>>4);
998 IGbE::TxDescCache::serialize(std::ostream
&os
)
1000 DescCache
<TxDesc
>::serialize(os
);
1001 SERIALIZE_SCALAR(pktDone
);
1002 SERIALIZE_SCALAR(isTcp
);
1003 SERIALIZE_SCALAR(pktWaiting
);
1007 IGbE::TxDescCache::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1009 DescCache
<TxDesc
>::unserialize(cp
, section
);
1010 UNSERIALIZE_SCALAR(pktDone
);
1011 UNSERIALIZE_SCALAR(isTcp
);
1012 UNSERIALIZE_SCALAR(pktWaiting
);
1016 IGbE::TxDescCache::packetAvailable()
1026 IGbE::TxDescCache::enableSm()
1028 igbe
->txTick
= true;
1029 igbe
->restartClock();
1033 IGbE::TxDescCache::hasOutstandingEvents()
1035 return pktEvent
.scheduled() || wbEvent
.scheduled() ||
1036 fetchEvent
.scheduled();
1040 ///////////////////////////////////// IGbE /////////////////////////////////
1043 IGbE::restartClock()
1045 if (!tickEvent
.scheduled() && (rxTick
|| txTick
|| txFifoTick
) && getState() ==
1047 tickEvent
.schedule((curTick
/cycles(1)) * cycles(1) + cycles(1));
1051 IGbE::drain(Event
*de
)
1054 count
= pioPort
->drain(de
) + dmaPort
->drain(de
);
1055 if (rxDescCache
.hasOutstandingEvents() ||
1056 txDescCache
.hasOutstandingEvents()) {
1065 if (tickEvent
.scheduled())
1066 tickEvent
.deschedule();
1069 changeState(Draining
);
1071 changeState(Drained
);
1079 SimObject::resume();
1094 if (rxDescCache
.hasOutstandingEvents() ||
1095 txDescCache
.hasOutstandingEvents()) {
1096 drainEvent
->process();
1102 IGbE::txStateMachine()
1104 if (!regs
.tctl
.en()) {
1106 DPRINTF(EthernetSM
, "TXS: TX disabled, stopping ticking\n");
1110 // If we have a packet available and it's length is not 0 (meaning it's not
1111 // a multidescriptor packet) put it in the fifo, otherwise an the next
1112 // iteration we'll get the rest of the data
1113 if (txPacket
&& txDescCache
.packetAvailable() && txPacket
->length
) {
1115 DPRINTF(EthernetSM
, "TXS: packet placed in TX FIFO\n");
1116 success
= txFifo
.push(txPacket
);
1120 txDescCache
.writeback((cacheBlockSize()-1)>>4);
1124 // Only support descriptor granularity
1125 assert(regs
.txdctl
.gran());
1126 if (regs
.txdctl
.lwthresh() && txDescCache
.descLeft() < (regs
.txdctl
.lwthresh() * 8)) {
1127 DPRINTF(EthernetSM
, "TXS: LWTHRESH caused posting of TXDLOW\n");
1128 postInterrupt(IT_TXDLOW
);
1132 txPacket
= new EthPacketData(16384);
1135 if (!txDescCache
.packetWaiting()) {
1136 if (txDescCache
.descLeft() == 0) {
1137 DPRINTF(EthernetSM
, "TXS: No descriptors left in ring, forcing "
1138 "writeback stopping ticking and posting TXQE\n");
1139 txDescCache
.writeback(0);
1141 postInterrupt(IT_TXQE
, true);
1146 if (!(txDescCache
.descUnused())) {
1147 DPRINTF(EthernetSM
, "TXS: No descriptors available in cache, fetching and stopping ticking\n");
1149 txDescCache
.fetchDescriptors();
1154 size
= txDescCache
.getPacketSize();
1155 if (size
> 0 && txFifo
.avail() > size
) {
1156 DPRINTF(EthernetSM
, "TXS: Reserving %d bytes in FIFO and begining "
1157 "DMA of next packet\n", size
);
1158 txFifo
.reserve(size
);
1159 txDescCache
.getPacketData(txPacket
);
1160 } else if (size
<= 0) {
1161 DPRINTF(EthernetSM
, "TXS: No packets to get, writing back used descriptors\n");
1162 txDescCache
.writeback(0);
1164 DPRINTF(EthernetSM
, "TXS: FIFO full, stopping ticking until space "
1165 "available in FIFO\n");
1166 txDescCache
.writeback((cacheBlockSize()-1)>>4);
1173 DPRINTF(EthernetSM
, "TXS: Nothing to do, stopping ticking\n");
1178 IGbE::ethRxPkt(EthPacketPtr pkt
)
1180 DPRINTF(Ethernet
, "RxFIFO: Receiving pcakte from wire\n");
1181 if (!regs
.rctl
.en()) {
1182 DPRINTF(Ethernet
, "RxFIFO: RX not enabled, dropping\n");
1186 // restart the state machines if they are stopped
1188 if ((rxTick
|| txTick
) && !tickEvent
.scheduled()) {
1189 DPRINTF(EthernetSM
, "RXS: received packet into fifo, starting ticking\n");
1193 if (!rxFifo
.push(pkt
)) {
1194 DPRINTF(Ethernet
, "RxFIFO: Packet won't fit in fifo... dropped\n");
1195 postInterrupt(IT_RXO
, true);
1203 IGbE::rxStateMachine()
1205 if (!regs
.rctl
.en()) {
1207 DPRINTF(EthernetSM
, "RXS: RX disabled, stopping ticking\n");
1211 // If the packet is done check for interrupts/descriptors/etc
1212 if (rxDescCache
.packetDone()) {
1213 rxDmaPacket
= false;
1214 DPRINTF(EthernetSM
, "RXS: Packet completed DMA to memory\n");
1215 int descLeft
= rxDescCache
.descLeft();
1216 switch (regs
.rctl
.rdmts()) {
1217 case 2: if (descLeft
> .125 * regs
.rdlen()) break;
1218 case 1: if (descLeft
> .250 * regs
.rdlen()) break;
1219 case 0: if (descLeft
> .500 * regs
.rdlen()) break;
1220 DPRINTF(Ethernet
, "RXS: Interrupting (RXDMT) because of descriptors left\n");
1221 postInterrupt(IT_RXDMT
);
1225 if (descLeft
== 0) {
1226 DPRINTF(EthernetSM
, "RXS: No descriptors left in ring, forcing"
1227 " writeback and stopping ticking\n");
1228 rxDescCache
.writeback(0);
1232 // only support descriptor granulaties
1233 assert(regs
.rxdctl
.gran());
1235 if (regs
.rxdctl
.wthresh() >= rxDescCache
.descUsed()) {
1236 DPRINTF(EthernetSM
, "RXS: Writing back because WTHRESH >= descUsed\n");
1237 if (regs
.rxdctl
.wthresh() < (cacheBlockSize()>>4))
1238 rxDescCache
.writeback(regs
.rxdctl
.wthresh()-1);
1240 rxDescCache
.writeback((cacheBlockSize()-1)>>4);
1243 if ((rxDescCache
.descUnused() < regs
.rxdctl
.pthresh()) &&
1244 ((rxDescCache
.descLeft() - rxDescCache
.descUnused()) > regs
.rxdctl
.hthresh())) {
1245 DPRINTF(EthernetSM
, "RXS: Fetching descriptors because descUnused < PTHRESH\n");
1246 rxDescCache
.fetchDescriptors();
1249 if (rxDescCache
.descUnused() == 0) {
1250 DPRINTF(EthernetSM
, "RXS: No descriptors available in cache, "
1251 "fetching descriptors and stopping ticking\n");
1253 rxDescCache
.fetchDescriptors();
1259 DPRINTF(EthernetSM
, "RXS: stopping ticking until packet DMA completes\n");
1264 if (!rxDescCache
.descUnused()) {
1265 DPRINTF(EthernetSM
, "RXS: No descriptors available in cache, stopping ticking\n");
1267 DPRINTF(EthernetSM
, "RXS: No descriptors available, fetching\n");
1268 rxDescCache
.fetchDescriptors();
1272 if (rxFifo
.empty()) {
1273 DPRINTF(EthernetSM
, "RXS: RxFIFO empty, stopping ticking\n");
1279 pkt
= rxFifo
.front();
1281 DPRINTF(EthernetSM
, "RXS: Writing packet into memory\n");
1282 if (!rxDescCache
.writePacket(pkt
)) {
1286 DPRINTF(EthernetSM
, "RXS: Removing packet from FIFO\n");
1288 DPRINTF(EthernetSM
, "RXS: stopping ticking until packet DMA completes\n");
1296 if (txFifo
.empty()) {
1302 if (etherInt
->sendPacket(txFifo
.front())) {
1303 DPRINTF(EthernetSM
, "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
1307 // We'll get woken up when the packet ethTxDone() gets called
1316 DPRINTF(EthernetSM
, "IGbE: -------------- Cycle --------------\n");
1328 if (rxTick
|| txTick
|| txFifoTick
)
1329 tickEvent
.schedule(curTick
+ cycles(1));
1335 // restart the tx state machines if they are stopped
1336 // fifo to send another packet
1337 // tx sm to put more data into the fifo
1342 DPRINTF(EthernetSM
, "TxFIFO: Transmission complete\n");
1346 IGbE::serialize(std::ostream
&os
)
1348 PciDev::serialize(os
);
1351 SERIALIZE_SCALAR(eeOpBits
);
1352 SERIALIZE_SCALAR(eeAddrBits
);
1353 SERIALIZE_SCALAR(eeDataBits
);
1354 SERIALIZE_SCALAR(eeOpcode
);
1355 SERIALIZE_SCALAR(eeAddr
);
1356 SERIALIZE_ARRAY(flash
,iGbReg::EEPROM_SIZE
);
1358 rxFifo
.serialize("rxfifo", os
);
1359 txFifo
.serialize("txfifo", os
);
1361 bool txPktExists
= txPacket
;
1362 SERIALIZE_SCALAR(txPktExists
);
1364 txPacket
->serialize("txpacket", os
);
1366 Tick rdtr_time
= 0, radv_time
= 0, tidv_time
= 0, tadv_time
= 0,
1369 if (rdtrEvent
.scheduled())
1370 rdtr_time
= rdtrEvent
.when();
1371 SERIALIZE_SCALAR(rdtr_time
);
1373 if (radvEvent
.scheduled())
1374 radv_time
= radvEvent
.when();
1375 SERIALIZE_SCALAR(radv_time
);
1377 if (tidvEvent
.scheduled())
1378 rdtr_time
= tidvEvent
.when();
1379 SERIALIZE_SCALAR(tidv_time
);
1381 if (tadvEvent
.scheduled())
1382 rdtr_time
= tadvEvent
.when();
1383 SERIALIZE_SCALAR(tadv_time
);
1385 if (interEvent
.scheduled())
1386 rdtr_time
= interEvent
.when();
1387 SERIALIZE_SCALAR(inter_time
);
1389 nameOut(os
, csprintf("%s.TxDescCache", name()));
1390 txDescCache
.serialize(os
);
1392 nameOut(os
, csprintf("%s.RxDescCache", name()));
1393 rxDescCache
.serialize(os
);
1397 IGbE::unserialize(Checkpoint
*cp
, const std::string
§ion
)
1399 PciDev::unserialize(cp
, section
);
1401 regs
.unserialize(cp
, section
);
1402 UNSERIALIZE_SCALAR(eeOpBits
);
1403 UNSERIALIZE_SCALAR(eeAddrBits
);
1404 UNSERIALIZE_SCALAR(eeDataBits
);
1405 UNSERIALIZE_SCALAR(eeOpcode
);
1406 UNSERIALIZE_SCALAR(eeAddr
);
1407 UNSERIALIZE_ARRAY(flash
,iGbReg::EEPROM_SIZE
);
1409 rxFifo
.unserialize("rxfifo", cp
, section
);
1410 txFifo
.unserialize("txfifo", cp
, section
);
1413 UNSERIALIZE_SCALAR(txPktExists
);
1415 txPacket
= new EthPacketData(16384);
1416 txPacket
->unserialize("txpacket", cp
, section
);
1423 Tick rdtr_time
, radv_time
, tidv_time
, tadv_time
, inter_time
;
1424 UNSERIALIZE_SCALAR(rdtr_time
);
1425 UNSERIALIZE_SCALAR(radv_time
);
1426 UNSERIALIZE_SCALAR(tidv_time
);
1427 UNSERIALIZE_SCALAR(tadv_time
);
1428 UNSERIALIZE_SCALAR(inter_time
);
1431 rdtrEvent
.schedule(rdtr_time
);
1434 radvEvent
.schedule(radv_time
);
1437 tidvEvent
.schedule(tidv_time
);
1440 tadvEvent
.schedule(tadv_time
);
1443 interEvent
.schedule(inter_time
);
1445 txDescCache
.unserialize(cp
, csprintf("%s.TxDescCache", section
));
1447 rxDescCache
.unserialize(cp
, csprintf("%s.RxDescCache", section
));
1451 IGbEIntParams::create()
1453 IGbEInt
*dev_int
= new IGbEInt(name
, device
);
1455 EtherInt
*p
= (EtherInt
*)peer
;
1457 dev_int
->setPeer(p
);
1458 p
->setPeer(dev_int
);
1465 IGbEParams::create()
1467 return new IGbE(this);