src/dev/i8254xGBe.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /* @file
  32  * Device model for Intel's 8254x line of gigabit ethernet controllers.
  33  */
  34
  35 #ifndef __DEV_I8254XGBE_HH__
  36 #define __DEV_I8254XGBE_HH__
  37
  38 #include <deque>
  39 #include <string>
  40
  41 #include "base/cp_annotate.hh"
  42 #include "base/inet.hh"
  43 #include "debug/EthernetDesc.hh"
  44 #include "debug/EthernetIntr.hh"
  45 #include "dev/etherdevice.hh"
  46 #include "dev/etherint.hh"
  47 #include "dev/etherpkt.hh"
  48 #include "dev/i8254xGBe_defs.hh"
  49 #include "dev/pcidev.hh"
  50 #include "dev/pktfifo.hh"
  51 #include "params/IGbE.hh"
  52 #include "sim/eventq.hh"
  53
  54 class IGbEInt;
  55
  56 class IGbE : public EtherDevice
  57 {
  58   private:
  59     IGbEInt *etherInt;
  60     CPA *cpa;
  61
  62     // device registers
  63     iGbReg::Regs regs;
  64
  65     // eeprom data, status and control bits
  66     int eeOpBits, eeAddrBits, eeDataBits;
  67     uint8_t eeOpcode, eeAddr;
  68     uint16_t flash[iGbReg::EEPROM_SIZE];
  69
  70     // The drain event if we have one
  71     DrainManager *drainManager;
  72
  73     // packet fifos
  74     PacketFifo rxFifo;
  75     PacketFifo txFifo;
  76
  77     // Packet that we are currently putting into the txFifo
  78     EthPacketPtr txPacket;
  79
  80     // Should to Rx/Tx State machine tick?
  81     bool rxTick;
  82     bool txTick;
  83     bool txFifoTick;
  84
  85     bool rxDmaPacket;
  86
  87     // Number of bytes copied from current RX packet
  88     unsigned pktOffset;
  89
  90     // Delays in managaging descriptors
  91     Tick fetchDelay, wbDelay;
  92     Tick fetchCompDelay, wbCompDelay;
  93     Tick rxWriteDelay, txReadDelay;
  94
  95     // Event and function to deal with RDTR timer expiring
  96     void rdtrProcess() {
  97         rxDescCache.writeback(0);
  98         DPRINTF(EthernetIntr,
  99                 "Posting RXT interrupt because RDTR timer expired\n");
 100         postInterrupt(iGbReg::IT_RXT);
 101     }
 102
 103     //friend class EventWrapper<IGbE, &IGbE::rdtrProcess>;
 104     EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent;
 105
 106     // Event and function to deal with RADV timer expiring
 107     void radvProcess() {
 108         rxDescCache.writeback(0);
 109         DPRINTF(EthernetIntr,
 110                 "Posting RXT interrupt because RADV timer expired\n");
 111         postInterrupt(iGbReg::IT_RXT);
 112     }
 113
 114     //friend class EventWrapper<IGbE, &IGbE::radvProcess>;
 115     EventWrapper<IGbE, &IGbE::radvProcess> radvEvent;
 116
 117     // Event and function to deal with TADV timer expiring
 118     void tadvProcess() {
 119         txDescCache.writeback(0);
 120         DPRINTF(EthernetIntr,
 121                 "Posting TXDW interrupt because TADV timer expired\n");
 122         postInterrupt(iGbReg::IT_TXDW);
 123     }
 124
 125     //friend class EventWrapper<IGbE, &IGbE::tadvProcess>;
 126     EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent;
 127
 128     // Event and function to deal with TIDV timer expiring
 129     void tidvProcess() {
 130         txDescCache.writeback(0);
 131         DPRINTF(EthernetIntr,
 132                 "Posting TXDW interrupt because TIDV timer expired\n");
 133         postInterrupt(iGbReg::IT_TXDW);
 134     }
 135     //friend class EventWrapper<IGbE, &IGbE::tidvProcess>;
 136     EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent;
 137
 138     // Main event to tick the device
 139     void tick();
 140     //friend class EventWrapper<IGbE, &IGbE::tick>;
 141     EventWrapper<IGbE, &IGbE::tick> tickEvent;
 142
 143
 144     uint64_t macAddr;
 145
 146     void rxStateMachine();
 147     void txStateMachine();
 148     void txWire();
 149
 150     /** Write an interrupt into the interrupt pending register and check mask
 151      * and interrupt limit timer before sending interrupt to CPU
 152      * @param t the type of interrupt we are posting
 153      * @param now should we ignore the interrupt limiting timer
 154      */
 155     void postInterrupt(iGbReg::IntTypes t, bool now = false);
 156
 157     /** Check and see if changes to the mask register have caused an interrupt
 158      * to need to be sent or perhaps removed an interrupt cause.
 159      */
 160     void chkInterrupt();
 161
 162     /** Send an interrupt to the cpu
 163      */
 164     void delayIntEvent();
 165     void cpuPostInt();
 166     // Event to moderate interrupts
 167     EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent;
 168
 169     /** Clear the interupt line to the cpu
 170      */
 171     void cpuClearInt();
 172
 173     Tick intClock() { return SimClock::Int::ns * 1024; }
 174
 175     /** This function is used to restart the clock so it can handle things like
 176      * draining and resume in one place. */
 177     void restartClock();
 178
 179     /** Check if all the draining things that need to occur have occured and
 180      * handle the drain event if so.
 181      */
 182     void checkDrain();
 183
 184     void anBegin(std::string sm, std::string st, int flags = CPA::FL_NONE) {
 185         cpa->hwBegin((CPA::flags)flags, sys, macAddr, sm, st);
 186     }
 187
 188     void anQ(std::string sm, std::string q) {
 189         cpa->hwQ(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
 190     }
 191
 192     void anDq(std::string sm, std::string q) {
 193         cpa->hwDq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
 194     }
 195
 196     void anPq(std::string sm, std::string q, int num = 1) {
 197         cpa->hwPq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
 198     }
 199
 200     void anRq(std::string sm, std::string q, int num = 1) {
 201         cpa->hwRq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
 202     }
 203
 204     void anWe(std::string sm, std::string q) {
 205         cpa->hwWe(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
 206     }
 207
 208     void anWf(std::string sm, std::string q) {
 209         cpa->hwWf(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
 210     }
 211
 212
 213     template<class T>
 214     class DescCache
 215     {
 216       protected:
 217         virtual Addr descBase() const = 0;
 218         virtual long descHead() const = 0;
 219         virtual long descTail() const = 0;
 220         virtual long descLen() const = 0;
 221         virtual void updateHead(long h) = 0;
 222         virtual void enableSm() = 0;
 223         virtual void actionAfterWb() {}
 224         virtual void fetchAfterWb() = 0;
 225
 226         typedef std::deque<T *> CacheType;
 227         CacheType usedCache;
 228         CacheType unusedCache;
 229
 230         T *fetchBuf;
 231         T *wbBuf;
 232
 233         // Pointer to the device we cache for
 234         IGbE *igbe;
 235
 236         // Name of this  descriptor cache
 237         std::string _name;
 238
 239         // How far we've cached
 240         int cachePnt;
 241
 242         // The size of the descriptor cache
 243         int size;
 244
 245         // How many descriptors we are currently fetching
 246         int curFetching;
 247
 248         // How many descriptors we are currently writing back
 249         int wbOut;
 250
 251         // if the we wrote back to the end of the descriptor ring and are going
 252         // to have to wrap and write more
 253         bool moreToWb;
 254
 255         // What the alignment is of the next descriptor writeback
 256         Addr wbAlignment;
 257
 258         /** The packet that is currently being dmad to memory if any */
 259         EthPacketPtr pktPtr;
 260
 261         /** Shortcut for DMA address translation */
 262         Addr pciToDma(Addr a) { return igbe->platform->pciToDma(a); }
 263
 264       public:
 265         /** Annotate sm*/
 266         std::string annSmFetch, annSmWb, annUnusedDescQ, annUsedCacheQ,
 267             annUsedDescQ, annUnusedCacheQ, annDescQ;
 268
 269         DescCache(IGbE *i, const std::string n, int s);
 270         virtual ~DescCache();
 271
 272         std::string name() { return _name; }
 273
 274         /** If the address/len/head change when we've got descriptors that are
 275          * dirty that is very bad. This function checks that we don't and if we
 276          * do panics.
 277          */
 278         void areaChanged();
 279
 280         void writeback(Addr aMask);
 281         void writeback1();
 282         EventWrapper<DescCache, &DescCache::writeback1> wbDelayEvent;
 283
 284         /** Fetch a chunk of descriptors into the descriptor cache.
 285          * Calls fetchComplete when the memory system returns the data
 286          */
 287         void fetchDescriptors();
 288         void fetchDescriptors1();
 289         EventWrapper<DescCache, &DescCache::fetchDescriptors1> fetchDelayEvent;
 290
 291         /** Called by event when dma to read descriptors is completed
 292          */
 293         void fetchComplete();
 294         EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent;
 295
 296         /** Called by event when dma to writeback descriptors is completed
 297          */
 298         void wbComplete();
 299         EventWrapper<DescCache, &DescCache::wbComplete> wbEvent;
 300
 301         /* Return the number of descriptors left in the ring, so the device has
 302          * a way to figure out if it needs to interrupt.
 303          */
 304         unsigned
 305         descLeft() const
 306         {
 307             unsigned left = unusedCache.size();
 308             if (cachePnt > descTail())
 309                 left += (descLen() - cachePnt + descTail());
 310             else
 311                 left += (descTail() - cachePnt);
 312
 313             return left;
 314         }
 315
 316         /* Return the number of descriptors used and not written back.
 317          */
 318         unsigned descUsed() const { return usedCache.size(); }
 319
 320         /* Return the number of cache unused descriptors we have. */
 321         unsigned descUnused() const { return unusedCache.size(); }
 322
 323         /* Get into a state where the descriptor address/head/etc colud be
 324          * changed */
 325         void reset();
 326
 327         virtual void serialize(std::ostream &os);
 328         virtual void unserialize(Checkpoint *cp, const std::string &section);
 329
 330         virtual bool hasOutstandingEvents() {
 331             return wbEvent.scheduled() || fetchEvent.scheduled();
 332         }
 333
 334     };
 335
 336
 337     class RxDescCache : public DescCache<iGbReg::RxDesc>
 338     {
 339       protected:
 340         virtual Addr descBase() const { return igbe->regs.rdba(); }
 341         virtual long descHead() const { return igbe->regs.rdh(); }
 342         virtual long descLen() const { return igbe->regs.rdlen() >> 4; }
 343         virtual long descTail() const { return igbe->regs.rdt(); }
 344         virtual void updateHead(long h) { igbe->regs.rdh(h); }
 345         virtual void enableSm();
 346         virtual void fetchAfterWb() {
 347             if (!igbe->rxTick && igbe->getDrainState() == Drainable::Running)
 348                 fetchDescriptors();
 349         }
 350
 351         bool pktDone;
 352
 353         /** Variable to head with header/data completion events */
 354         int splitCount;
 355
 356         /** Bytes of packet that have been copied, so we know when to
 357             set EOP */
 358         unsigned bytesCopied;
 359
 360       public:
 361         RxDescCache(IGbE *i, std::string n, int s);
 362
 363         /** Write the given packet into the buffer(s) pointed to by the
 364          * descriptor and update the book keeping. Should only be called when
 365          * there are no dma's pending.
 366          * @param packet ethernet packet to write
 367          * @param pkt_offset bytes already copied from the packet to memory
 368          * @return pkt_offset + number of bytes copied during this call
 369          */
 370         int writePacket(EthPacketPtr packet, int pkt_offset);
 371
 372         /** Called by event when dma to write packet is completed
 373          */
 374         void pktComplete();
 375
 376         /** Check if the dma on the packet has completed and RX state machine
 377          * can continue
 378          */
 379         bool packetDone();
 380
 381         EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent;
 382
 383         // Event to handle issuing header and data write at the same time
 384         // and only callking pktComplete() when both are completed
 385         void pktSplitDone();
 386         EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent;
 387         EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent;
 388
 389         virtual bool hasOutstandingEvents();
 390
 391         virtual void serialize(std::ostream &os);
 392         virtual void unserialize(Checkpoint *cp, const std::string &section);
 393     };
 394     friend class RxDescCache;
 395
 396     RxDescCache rxDescCache;
 397
 398     class TxDescCache  : public DescCache<iGbReg::TxDesc>
 399     {
 400       protected:
 401         virtual Addr descBase() const { return igbe->regs.tdba(); }
 402         virtual long descHead() const { return igbe->regs.tdh(); }
 403         virtual long descTail() const { return igbe->regs.tdt(); }
 404         virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
 405         virtual void updateHead(long h) { igbe->regs.tdh(h); }
 406         virtual void enableSm();
 407         virtual void actionAfterWb();
 408         virtual void fetchAfterWb() {
 409             if (!igbe->txTick && igbe->getDrainState() == Drainable::Running)
 410                 fetchDescriptors();
 411         }
 412
 413
 414
 415         bool pktDone;
 416         bool isTcp;
 417         bool pktWaiting;
 418         bool pktMultiDesc;
 419         Addr completionAddress;
 420         bool completionEnabled;
 421         uint32_t descEnd;
 422
 423
 424         // tso variables
 425         bool useTso;
 426         Addr tsoHeaderLen;
 427         Addr tsoMss;
 428         Addr tsoTotalLen;
 429         Addr tsoUsedLen;
 430         Addr tsoPrevSeq;
 431         Addr tsoPktPayloadBytes;
 432         bool tsoLoadedHeader;
 433         bool tsoPktHasHeader;
 434         uint8_t tsoHeader[256];
 435         Addr tsoDescBytesUsed;
 436         Addr tsoCopyBytes;
 437         int tsoPkts;
 438
 439       public:
 440         TxDescCache(IGbE *i, std::string n, int s);
 441
 442         /** Tell the cache to DMA a packet from main memory into its buffer and
 443          * return the size the of the packet to reserve space in tx fifo.
 444          * @return size of the packet
 445          */
 446         unsigned getPacketSize(EthPacketPtr p);
 447         void getPacketData(EthPacketPtr p);
 448         void processContextDesc();
 449
 450         /** Return the number of dsecriptors in a cache block for threshold
 451          * operations.
 452          */
 453         unsigned
 454         descInBlock(unsigned num_desc)
 455         {
 456             return num_desc / igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc);
 457         }
 458
 459         /** Ask if the packet has been transfered so the state machine can give
 460          * it to the fifo.
 461          * @return packet available in descriptor cache
 462          */
 463         bool packetAvailable();
 464
 465         /** Ask if we are still waiting for the packet to be transfered.
 466          * @return packet still in transit.
 467          */
 468         bool packetWaiting() { return pktWaiting; }
 469
 470         /** Ask if this packet is composed of multiple descriptors
 471          * so even if we've got data, we need to wait for more before
 472          * we can send it out.
 473          * @return packet can't be sent out because it's a multi-descriptor
 474          * packet
 475          */
 476         bool packetMultiDesc() { return pktMultiDesc;}
 477
 478         /** Called by event when dma to write packet is completed
 479          */
 480         void pktComplete();
 481         EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent;
 482
 483         void headerComplete();
 484         EventWrapper<TxDescCache, &TxDescCache::headerComplete> headerEvent;
 485
 486
 487         void completionWriteback(Addr a, bool enabled) {
 488             DPRINTF(EthernetDesc,
 489                     "Completion writeback Addr: %#x enabled: %d\n",
 490                     a, enabled);
 491             completionAddress = a;
 492             completionEnabled = enabled;
 493         }
 494
 495         virtual bool hasOutstandingEvents();
 496
 497         void nullCallback() {
 498             DPRINTF(EthernetDesc, "Completion writeback complete\n");
 499         }
 500         EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent;
 501
 502         virtual void serialize(std::ostream &os);
 503         virtual void unserialize(Checkpoint *cp, const std::string &section);
 504
 505     };
 506     friend class TxDescCache;
 507
 508     TxDescCache txDescCache;
 509
 510   public:
 511     typedef IGbEParams Params;
 512     const Params *
 513     params() const {
 514         return dynamic_cast<const Params *>(_params);
 515     }
 516
 517     IGbE(const Params *params);
 518     ~IGbE();
 519     virtual void init();
 520
 521     virtual EtherInt *getEthPort(const std::string &if_name, int idx);
 522
 523     Tick lastInterrupt;
 524
 525     virtual Tick read(PacketPtr pkt);
 526     virtual Tick write(PacketPtr pkt);
 527
 528     virtual Tick writeConfig(PacketPtr pkt);
 529
 530     bool ethRxPkt(EthPacketPtr packet);
 531     void ethTxDone();
 532
 533     virtual void serialize(std::ostream &os);
 534     virtual void unserialize(Checkpoint *cp, const std::string &section);
 535
 536     unsigned int drain(DrainManager *dm);
 537     void drainResume();
 538
 539 };
 540
 541 class IGbEInt : public EtherInt
 542 {
 543   private:
 544     IGbE *dev;
 545
 546   public:
 547     IGbEInt(const std::string &name, IGbE *d)
 548         : EtherInt(name), dev(d)
 549     { }
 550
 551     virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
 552     virtual void sendDone() { dev->ethTxDone(); }
 553 };
 554
 555 #endif //__DEV_I8254XGBE_HH__