src/dev/i8254xGBe.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /* @file
  32  * Device model for Intel's 8254x line of gigabit ethernet controllers.
  33  */
  34
  35 #ifndef __DEV_I8254XGBE_HH__
  36 #define __DEV_I8254XGBE_HH__
  37
  38 #include <deque>
  39 #include <string>
  40
  41 #include "base/cp_annotate.hh"
  42 #include "base/inet.hh"
  43 #include "debug/EthernetDesc.hh"
  44 #include "debug/EthernetIntr.hh"
  45 #include "dev/etherdevice.hh"
  46 #include "dev/etherint.hh"
  47 #include "dev/etherpkt.hh"
  48 #include "dev/i8254xGBe_defs.hh"
  49 #include "dev/pcidev.hh"
  50 #include "dev/pktfifo.hh"
  51 #include "params/IGbE.hh"
  52 #include "sim/eventq.hh"
  53
  54 class IGbEInt;
  55
  56 class IGbE : public EtherDevice
  57 {
  58   private:
  59     IGbEInt *etherInt;
  60     CPA *cpa;
  61
  62     // device registers
  63     iGbReg::Regs regs;
  64
  65     // eeprom data, status and control bits
  66     int eeOpBits, eeAddrBits, eeDataBits;
  67     uint8_t eeOpcode, eeAddr;
  68     uint16_t flash[iGbReg::EEPROM_SIZE];
  69
  70     // The drain event if we have one
  71     Event *drainEvent;
  72
  73     // cached parameters from params struct
  74     bool useFlowControl;
  75
  76     // packet fifos
  77     PacketFifo rxFifo;
  78     PacketFifo txFifo;
  79
  80     // Packet that we are currently putting into the txFifo
  81     EthPacketPtr txPacket;
  82
  83     // Should to Rx/Tx State machine tick?
  84     bool rxTick;
  85     bool txTick;
  86     bool txFifoTick;
  87
  88     bool rxDmaPacket;
  89
  90     // Number of bytes copied from current RX packet
  91     unsigned pktOffset;
  92
  93     // Delays in managaging descriptors
  94     Tick fetchDelay, wbDelay;
  95     Tick fetchCompDelay, wbCompDelay;
  96     Tick rxWriteDelay, txReadDelay;
  97
  98     // Event and function to deal with RDTR timer expiring
  99     void rdtrProcess() {
 100         rxDescCache.writeback(0);
 101         DPRINTF(EthernetIntr,
 102                 "Posting RXT interrupt because RDTR timer expired\n");
 103         postInterrupt(iGbReg::IT_RXT);
 104     }
 105
 106     //friend class EventWrapper<IGbE, &IGbE::rdtrProcess>;
 107     EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent;
 108
 109     // Event and function to deal with RADV timer expiring
 110     void radvProcess() {
 111         rxDescCache.writeback(0);
 112         DPRINTF(EthernetIntr,
 113                 "Posting RXT interrupt because RADV timer expired\n");
 114         postInterrupt(iGbReg::IT_RXT);
 115     }
 116
 117     //friend class EventWrapper<IGbE, &IGbE::radvProcess>;
 118     EventWrapper<IGbE, &IGbE::radvProcess> radvEvent;
 119
 120     // Event and function to deal with TADV timer expiring
 121     void tadvProcess() {
 122         txDescCache.writeback(0);
 123         DPRINTF(EthernetIntr,
 124                 "Posting TXDW interrupt because TADV timer expired\n");
 125         postInterrupt(iGbReg::IT_TXDW);
 126     }
 127
 128     //friend class EventWrapper<IGbE, &IGbE::tadvProcess>;
 129     EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent;
 130
 131     // Event and function to deal with TIDV timer expiring
 132     void tidvProcess() {
 133         txDescCache.writeback(0);
 134         DPRINTF(EthernetIntr,
 135                 "Posting TXDW interrupt because TIDV timer expired\n");
 136         postInterrupt(iGbReg::IT_TXDW);
 137     }
 138     //friend class EventWrapper<IGbE, &IGbE::tidvProcess>;
 139     EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent;
 140
 141     // Main event to tick the device
 142     void tick();
 143     //friend class EventWrapper<IGbE, &IGbE::tick>;
 144     EventWrapper<IGbE, &IGbE::tick> tickEvent;
 145
 146
 147     uint64_t macAddr;
 148
 149     void rxStateMachine();
 150     void txStateMachine();
 151     void txWire();
 152
 153     /** Write an interrupt into the interrupt pending register and check mask
 154      * and interrupt limit timer before sending interrupt to CPU
 155      * @param t the type of interrupt we are posting
 156      * @param now should we ignore the interrupt limiting timer
 157      */
 158     void postInterrupt(iGbReg::IntTypes t, bool now = false);
 159
 160     /** Check and see if changes to the mask register have caused an interrupt
 161      * to need to be sent or perhaps removed an interrupt cause.
 162      */
 163     void chkInterrupt();
 164
 165     /** Send an interrupt to the cpu
 166      */
 167     void delayIntEvent();
 168     void cpuPostInt();
 169     // Event to moderate interrupts
 170     EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent;
 171
 172     /** Clear the interupt line to the cpu
 173      */
 174     void cpuClearInt();
 175
 176     Tick intClock() { return SimClock::Int::ns * 1024; }
 177
 178     /** This function is used to restart the clock so it can handle things like
 179      * draining and resume in one place. */
 180     void restartClock();
 181
 182     /** Check if all the draining things that need to occur have occured and
 183      * handle the drain event if so.
 184      */
 185     void checkDrain();
 186
 187     void anBegin(std::string sm, std::string st, int flags = CPA::FL_NONE) {
 188         cpa->hwBegin((CPA::flags)flags, sys, macAddr, sm, st);
 189     }
 190
 191     void anQ(std::string sm, std::string q) {
 192         cpa->hwQ(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
 193     }
 194
 195     void anDq(std::string sm, std::string q) {
 196         cpa->hwDq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
 197     }
 198
 199     void anPq(std::string sm, std::string q, int num = 1) {
 200         cpa->hwPq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
 201     }
 202
 203     void anRq(std::string sm, std::string q, int num = 1) {
 204         cpa->hwRq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
 205     }
 206
 207     void anWe(std::string sm, std::string q) {
 208         cpa->hwWe(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
 209     }
 210
 211     void anWf(std::string sm, std::string q) {
 212         cpa->hwWf(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
 213     }
 214
 215
 216     template<class T>
 217     class DescCache
 218     {
 219       protected:
 220         virtual Addr descBase() const = 0;
 221         virtual long descHead() const = 0;
 222         virtual long descTail() const = 0;
 223         virtual long descLen() const = 0;
 224         virtual void updateHead(long h) = 0;
 225         virtual void enableSm() = 0;
 226         virtual void actionAfterWb() {}
 227         virtual void fetchAfterWb() = 0;
 228
 229         typedef std::deque<T *> CacheType;
 230         CacheType usedCache;
 231         CacheType unusedCache;
 232
 233         T *fetchBuf;
 234         T *wbBuf;
 235
 236         // Pointer to the device we cache for
 237         IGbE *igbe;
 238
 239         // Name of this  descriptor cache
 240         std::string _name;
 241
 242         // How far we've cached
 243         int cachePnt;
 244
 245         // The size of the descriptor cache
 246         int size;
 247
 248         // How many descriptors we are currently fetching
 249         int curFetching;
 250
 251         // How many descriptors we are currently writing back
 252         int wbOut;
 253
 254         // if the we wrote back to the end of the descriptor ring and are going
 255         // to have to wrap and write more
 256         bool moreToWb;
 257
 258         // What the alignment is of the next descriptor writeback
 259         Addr wbAlignment;
 260
 261         /** The packet that is currently being dmad to memory if any */
 262         EthPacketPtr pktPtr;
 263
 264         /** Shortcut for DMA address translation */
 265         Addr pciToDma(Addr a) { return igbe->platform->pciToDma(a); }
 266
 267       public:
 268         /** Annotate sm*/
 269         std::string annSmFetch, annSmWb, annUnusedDescQ, annUsedCacheQ,
 270             annUsedDescQ, annUnusedCacheQ, annDescQ;
 271
 272         DescCache(IGbE *i, const std::string n, int s);
 273         virtual ~DescCache();
 274
 275         std::string name() { return _name; }
 276
 277         /** If the address/len/head change when we've got descriptors that are
 278          * dirty that is very bad. This function checks that we don't and if we
 279          * do panics.
 280          */
 281         void areaChanged();
 282
 283         void writeback(Addr aMask);
 284         void writeback1();
 285         EventWrapper<DescCache, &DescCache::writeback1> wbDelayEvent;
 286
 287         /** Fetch a chunk of descriptors into the descriptor cache.
 288          * Calls fetchComplete when the memory system returns the data
 289          */
 290         void fetchDescriptors();
 291         void fetchDescriptors1();
 292         EventWrapper<DescCache, &DescCache::fetchDescriptors1> fetchDelayEvent;
 293
 294         /** Called by event when dma to read descriptors is completed
 295          */
 296         void fetchComplete();
 297         EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent;
 298
 299         /** Called by event when dma to writeback descriptors is completed
 300          */
 301         void wbComplete();
 302         EventWrapper<DescCache, &DescCache::wbComplete> wbEvent;
 303
 304         /* Return the number of descriptors left in the ring, so the device has
 305          * a way to figure out if it needs to interrupt.
 306          */
 307         unsigned
 308         descLeft() const
 309         {
 310             unsigned left = unusedCache.size();
 311             if (cachePnt > descTail())
 312                 left += (descLen() - cachePnt + descTail());
 313             else
 314                 left += (descTail() - cachePnt);
 315
 316             return left;
 317         }
 318
 319         /* Return the number of descriptors used and not written back.
 320          */
 321         unsigned descUsed() const { return usedCache.size(); }
 322
 323         /* Return the number of cache unused descriptors we have. */
 324         unsigned descUnused() const { return unusedCache.size(); }
 325
 326         /* Get into a state where the descriptor address/head/etc colud be
 327          * changed */
 328         void reset();
 329
 330         virtual void serialize(std::ostream &os);
 331         virtual void unserialize(Checkpoint *cp, const std::string &section);
 332
 333         virtual bool hasOutstandingEvents() {
 334             return wbEvent.scheduled() || fetchEvent.scheduled();
 335         }
 336
 337     };
 338
 339
 340     class RxDescCache : public DescCache<iGbReg::RxDesc>
 341     {
 342       protected:
 343         virtual Addr descBase() const { return igbe->regs.rdba(); }
 344         virtual long descHead() const { return igbe->regs.rdh(); }
 345         virtual long descLen() const { return igbe->regs.rdlen() >> 4; }
 346         virtual long descTail() const { return igbe->regs.rdt(); }
 347         virtual void updateHead(long h) { igbe->regs.rdh(h); }
 348         virtual void enableSm();
 349         virtual void fetchAfterWb() {
 350             if (!igbe->rxTick && igbe->getState() == SimObject::Running)
 351                 fetchDescriptors();
 352         }
 353
 354         bool pktDone;
 355
 356         /** Variable to head with header/data completion events */
 357         int splitCount;
 358
 359         /** Bytes of packet that have been copied, so we know when to
 360             set EOP */
 361         unsigned bytesCopied;
 362
 363       public:
 364         RxDescCache(IGbE *i, std::string n, int s);
 365
 366         /** Write the given packet into the buffer(s) pointed to by the
 367          * descriptor and update the book keeping. Should only be called when
 368          * there are no dma's pending.
 369          * @param packet ethernet packet to write
 370          * @param pkt_offset bytes already copied from the packet to memory
 371          * @return pkt_offset + number of bytes copied during this call
 372          */
 373         int writePacket(EthPacketPtr packet, int pkt_offset);
 374
 375         /** Called by event when dma to write packet is completed
 376          */
 377         void pktComplete();
 378
 379         /** Check if the dma on the packet has completed and RX state machine
 380          * can continue
 381          */
 382         bool packetDone();
 383
 384         EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent;
 385
 386         // Event to handle issuing header and data write at the same time
 387         // and only callking pktComplete() when both are completed
 388         void pktSplitDone();
 389         EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent;
 390         EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent;
 391
 392         virtual bool hasOutstandingEvents();
 393
 394         virtual void serialize(std::ostream &os);
 395         virtual void unserialize(Checkpoint *cp, const std::string &section);
 396     };
 397     friend class RxDescCache;
 398
 399     RxDescCache rxDescCache;
 400
 401     class TxDescCache  : public DescCache<iGbReg::TxDesc>
 402     {
 403       protected:
 404         virtual Addr descBase() const { return igbe->regs.tdba(); }
 405         virtual long descHead() const { return igbe->regs.tdh(); }
 406         virtual long descTail() const { return igbe->regs.tdt(); }
 407         virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
 408         virtual void updateHead(long h) { igbe->regs.tdh(h); }
 409         virtual void enableSm();
 410         virtual void actionAfterWb();
 411         virtual void fetchAfterWb() {
 412             if (!igbe->txTick && igbe->getState() == SimObject::Running)
 413                 fetchDescriptors();
 414         }
 415
 416
 417
 418         bool pktDone;
 419         bool isTcp;
 420         bool pktWaiting;
 421         bool pktMultiDesc;
 422         Addr completionAddress;
 423         bool completionEnabled;
 424         uint32_t descEnd;
 425
 426
 427         // tso variables
 428         bool useTso;
 429         Addr tsoHeaderLen;
 430         Addr tsoMss;
 431         Addr tsoTotalLen;
 432         Addr tsoUsedLen;
 433         Addr tsoPrevSeq;
 434         Addr tsoPktPayloadBytes;
 435         bool tsoLoadedHeader;
 436         bool tsoPktHasHeader;
 437         uint8_t tsoHeader[256];
 438         Addr tsoDescBytesUsed;
 439         Addr tsoCopyBytes;
 440         int tsoPkts;
 441
 442       public:
 443         TxDescCache(IGbE *i, std::string n, int s);
 444
 445         /** Tell the cache to DMA a packet from main memory into its buffer and
 446          * return the size the of the packet to reserve space in tx fifo.
 447          * @return size of the packet
 448          */
 449         unsigned getPacketSize(EthPacketPtr p);
 450         void getPacketData(EthPacketPtr p);
 451         void processContextDesc();
 452
 453         /** Return the number of dsecriptors in a cache block for threshold
 454          * operations.
 455          */
 456         unsigned
 457         descInBlock(unsigned num_desc)
 458         {
 459             return num_desc / igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc);
 460         }
 461
 462         /** Ask if the packet has been transfered so the state machine can give
 463          * it to the fifo.
 464          * @return packet available in descriptor cache
 465          */
 466         bool packetAvailable();
 467
 468         /** Ask if we are still waiting for the packet to be transfered.
 469          * @return packet still in transit.
 470          */
 471         bool packetWaiting() { return pktWaiting; }
 472
 473         /** Ask if this packet is composed of multiple descriptors
 474          * so even if we've got data, we need to wait for more before
 475          * we can send it out.
 476          * @return packet can't be sent out because it's a multi-descriptor
 477          * packet
 478          */
 479         bool packetMultiDesc() { return pktMultiDesc;}
 480
 481         /** Called by event when dma to write packet is completed
 482          */
 483         void pktComplete();
 484         EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent;
 485
 486         void headerComplete();
 487         EventWrapper<TxDescCache, &TxDescCache::headerComplete> headerEvent;
 488
 489
 490         void completionWriteback(Addr a, bool enabled) {
 491             DPRINTF(EthernetDesc,
 492                     "Completion writeback Addr: %#x enabled: %d\n",
 493                     a, enabled);
 494             completionAddress = a;
 495             completionEnabled = enabled;
 496         }
 497
 498         virtual bool hasOutstandingEvents();
 499
 500         void nullCallback() {
 501             DPRINTF(EthernetDesc, "Completion writeback complete\n");
 502         }
 503         EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent;
 504
 505         virtual void serialize(std::ostream &os);
 506         virtual void unserialize(Checkpoint *cp, const std::string &section);
 507
 508     };
 509     friend class TxDescCache;
 510
 511     TxDescCache txDescCache;
 512
 513   public:
 514     typedef IGbEParams Params;
 515     const Params *
 516     params() const {
 517         return dynamic_cast<const Params *>(_params);
 518     }
 519
 520     IGbE(const Params *params);
 521     ~IGbE() {}
 522     virtual void init();
 523
 524     virtual EtherInt *getEthPort(const std::string &if_name, int idx);
 525
 526     Tick clock;
 527     Tick lastInterrupt;
 528     inline Tick ticks(int numCycles) const { return numCycles * clock; }
 529
 530     virtual Tick read(PacketPtr pkt);
 531     virtual Tick write(PacketPtr pkt);
 532
 533     virtual Tick writeConfig(PacketPtr pkt);
 534
 535     bool ethRxPkt(EthPacketPtr packet);
 536     void ethTxDone();
 537
 538     virtual void serialize(std::ostream &os);
 539     virtual void unserialize(Checkpoint *cp, const std::string &section);
 540     virtual unsigned int drain(Event *de);
 541     virtual void resume();
 542
 543 };
 544
 545 class IGbEInt : public EtherInt
 546 {
 547   private:
 548     IGbE *dev;
 549
 550   public:
 551     IGbEInt(const std::string &name, IGbE *d)
 552         : EtherInt(name), dev(d)
 553     { }
 554
 555     virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
 556     virtual void sendDone() { dev->ethTxDone(); }
 557 };
 558
 559 #endif //__DEV_I8254XGBE_HH__