src/dev/i8254xGBe.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /* @file
  32  * Device model for Intel's 8254x line of gigabit ethernet controllers.
  33  */
  34
  35 #ifndef __DEV_I8254XGBE_HH__
  36 #define __DEV_I8254XGBE_HH__
  37
  38 #include "base/inet.hh"
  39 #include "base/statistics.hh"
  40 #include "dev/etherint.hh"
  41 #include "dev/etherpkt.hh"
  42 #include "dev/i8254xGBe_defs.hh"
  43 #include "dev/pcidev.hh"
  44 #include "dev/pktfifo.hh"
  45 #include "sim/eventq.hh"
  46
  47 class IGbEInt;
  48
  49 class IGbE : public PciDev
  50 {
  51   private:
  52     IGbEInt *etherInt;
  53     iGbReg::Regs regs;
  54     int eeOpBits, eeAddrBits, eeDataBits;
  55     uint8_t eeOpcode, eeAddr;
  56
  57     uint16_t flash[iGbReg::EEPROM_SIZE];
  58
  59
  60   public:
  61     struct Params : public PciDev::Params
  62     {
  63         ;
  64     };
  65
  66     IGbE(Params *params);
  67     ~IGbE() {;}
  68
  69     virtual Tick read(PacketPtr pkt);
  70     virtual Tick write(PacketPtr pkt);
  71
  72     virtual Tick writeConfig(PacketPtr pkt);
  73
  74     bool ethRxPkt(EthPacketPtr packet);
  75     void ethTxDone();
  76
  77     void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
  78
  79     const Params *params() const {return (const Params *)_params; }
  80
  81     virtual void serialize(std::ostream &os);
  82     virtual void unserialize(Checkpoint *cp, const std::string &section);
  83
  84
  85 };
  86
  87 class IGbEInt : public EtherInt
  88 {
  89   private:
  90     IGbE *dev;
  91
  92   public:
  93     IGbEInt(const std::string &name, IGbE *d)
  94         : EtherInt(name), dev(d)
  95         { dev->setEthInt(this); }
  96
  97     virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
  98     virtual void sendDone() { dev->ethTxDone(); }
  99 };
 100
 101
 102
 103
 104
 105 #endif //__DEV_I8254XGBE_HH__
 106