src/dev/i8254xGBe.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /* @file
  32  * Device model for Intel's 8254x line of gigabit ethernet controllers.
  33  */
  34
  35 #ifndef __DEV_I8254XGBE_HH__
  36 #define __DEV_I8254XGBE_HH__
  37
  38 #include "base/inet.hh"
  39 #include "base/statistics.hh"
  40 #include "dev/etherint.hh"
  41 #include "dev/etherpkt.hh"
  42 #include "dev/i8254xGBe_defs.hh"
  43 #include "dev/pcidev.hh"
  44 #include "dev/pktfifo.hh"
  45 #include "sim/eventq.hh"
  46
  47 class IGbEInt;
  48
  49 class IGbE : public PciDev
  50 {
  51   private:
  52     IGbEInt *etherInt;
  53     iGbReg::Regs regs;
  54     int eeOpBits, eeAddrBits, eeDataBits;
  55     uint8_t eeOpcode, eeAddr;
  56
  57     bool useFlowControl;
  58
  59     uint16_t flash[iGbReg::EEPROM_SIZE];
  60
  61
  62   public:
  63     struct Params : public PciDev::Params
  64     {
  65         bool use_flow_control;
  66     };
  67
  68     IGbE(Params *params);
  69     ~IGbE() {;}
  70
  71     virtual Tick read(PacketPtr pkt);
  72     virtual Tick write(PacketPtr pkt);
  73
  74     virtual Tick writeConfig(PacketPtr pkt);
  75
  76     bool ethRxPkt(EthPacketPtr packet);
  77     void ethTxDone();
  78
  79     void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
  80
  81     const Params *params() const {return (const Params *)_params; }
  82
  83     virtual void serialize(std::ostream &os);
  84     virtual void unserialize(Checkpoint *cp, const std::string &section);
  85
  86
  87 };
  88
  89 class IGbEInt : public EtherInt
  90 {
  91   private:
  92     IGbE *dev;
  93
  94   public:
  95     IGbEInt(const std::string &name, IGbE *d)
  96         : EtherInt(name), dev(d)
  97         { dev->setEthInt(this); }
  98
  99     virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
 100     virtual void sendDone() { dev->ethTxDone(); }
 101 };
 102
 103
 104
 105
 106
 107 #endif //__DEV_I8254XGBE_HH__
 108