2 * Copyright (c) 2006 The Regents of The University of Michigan
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32 * Device model for Intel's 8254x line of gigabit ethernet controllers.
35 #ifndef __DEV_I8254XGBE_HH__
36 #define __DEV_I8254XGBE_HH__
38 #include "base/inet.hh"
39 #include "base/statistics.hh"
40 #include "dev/etherint.hh"
41 #include "dev/etherpkt.hh"
42 #include "dev/pcidev.hh"
43 #include "dev/pktfifo.hh"
44 #include "sim/eventq.hh"
48 class IGbE : public PciDev
54 struct Params : public PciDev::Params
62 virtual Tick read(Packet *pkt);
63 virtual Tick write(Packet *pkt);
65 virtual Tick writeConfig(Packet *pkt);
67 bool ethRxPkt(EthPacketPtr packet);
70 void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
72 const Params *params() const {return (const Params *)_params; }
74 virtual void serialize(std::ostream &os);
75 virtual void unserialize(Checkpoint *cp, const std::string §ion);
80 class IGbEInt : public EtherInt
86 IGbEInt(const std::string &name, IGbE *d)
87 : EtherInt(name), dev(d)
88 { dev->setEthInt(this); }
90 virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
91 virtual void sendDone() { dev->ethTxDone(); }
98 #endif //__DEV_I8254XGBE_HH__