src/dev/i8254xGBe.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /* @file
  32  * Device model for Intel's 8254x line of gigabit ethernet controllers.
  33  */
  34
  35 #ifndef __DEV_I8254XGBE_HH__
  36 #define __DEV_I8254XGBE_HH__
  37
  38 #include <deque>
  39 #include <string>
  40
  41 #include "base/inet.hh"
  42 #include "base/statistics.hh"
  43 #include "dev/etherint.hh"
  44 #include "dev/etherpkt.hh"
  45 #include "dev/i8254xGBe_defs.hh"
  46 #include "dev/pcidev.hh"
  47 #include "dev/pktfifo.hh"
  48 #include "sim/eventq.hh"
  49
  50 class IGbEInt;
  51
  52 class IGbE : public PciDev
  53 {
  54   private:
  55     IGbEInt *etherInt;
  56
  57     // device registers
  58     iGbReg::Regs regs;
  59
  60     // eeprom data, status and control bits
  61     int eeOpBits, eeAddrBits, eeDataBits;
  62     uint8_t eeOpcode, eeAddr;
  63     uint16_t flash[iGbReg::EEPROM_SIZE];
  64
  65     // The drain event if we have one
  66     Event *drainEvent;
  67
  68     // cached parameters from params struct
  69     bool useFlowControl;
  70
  71     // packet fifos
  72     PacketFifo rxFifo;
  73     PacketFifo txFifo;
  74
  75     // Packet that we are currently putting into the txFifo
  76     EthPacketPtr txPacket;
  77
  78     // Should to Rx/Tx State machine tick?
  79     bool rxTick;
  80     bool txTick;
  81     bool txFifoTick;
  82
  83     bool rxDmaPacket;
  84
  85     // Event and function to deal with RDTR timer expiring
  86     void rdtrProcess() {
  87         rxDescCache.writeback(0);
  88         DPRINTF(EthernetIntr, "Posting RXT interrupt because RDTR timer expired\n");
  89         postInterrupt(iGbReg::IT_RXT, true);
  90     }
  91
  92     //friend class EventWrapper<IGbE, &IGbE::rdtrProcess>;
  93     EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent;
  94
  95     // Event and function to deal with RADV timer expiring
  96     void radvProcess() {
  97         rxDescCache.writeback(0);
  98         DPRINTF(EthernetIntr, "Posting RXT interrupt because RADV timer expired\n");
  99         postInterrupt(iGbReg::IT_RXT, true);
 100     }
 101
 102     //friend class EventWrapper<IGbE, &IGbE::radvProcess>;
 103     EventWrapper<IGbE, &IGbE::radvProcess> radvEvent;
 104
 105     // Event and function to deal with TADV timer expiring
 106     void tadvProcess() {
 107         txDescCache.writeback(0);
 108         DPRINTF(EthernetIntr, "Posting TXDW interrupt because TADV timer expired\n");
 109         postInterrupt(iGbReg::IT_TXDW, true);
 110     }
 111
 112     //friend class EventWrapper<IGbE, &IGbE::tadvProcess>;
 113     EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent;
 114
 115     // Event and function to deal with TIDV timer expiring
 116     void tidvProcess() {
 117         txDescCache.writeback(0);
 118         DPRINTF(EthernetIntr, "Posting TXDW interrupt because TIDV timer expired\n");
 119         postInterrupt(iGbReg::IT_TXDW, true);
 120     }
 121     //friend class EventWrapper<IGbE, &IGbE::tidvProcess>;
 122     EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent;
 123
 124     // Main event to tick the device
 125     void tick();
 126     //friend class EventWrapper<IGbE, &IGbE::tick>;
 127     EventWrapper<IGbE, &IGbE::tick> tickEvent;
 128
 129
 130     void rxStateMachine();
 131     void txStateMachine();
 132     void txWire();
 133
 134     /** Write an interrupt into the interrupt pending register and check mask
 135      * and interrupt limit timer before sending interrupt to CPU
 136      * @param t the type of interrupt we are posting
 137      * @param now should we ignore the interrupt limiting timer
 138      */
 139     void postInterrupt(iGbReg::IntTypes t, bool now = false);
 140
 141     /** Check and see if changes to the mask register have caused an interrupt
 142      * to need to be sent or perhaps removed an interrupt cause.
 143      */
 144     void chkInterrupt();
 145
 146     /** Send an interrupt to the cpu
 147      */
 148     void cpuPostInt();
 149     // Event to moderate interrupts
 150     EventWrapper<IGbE, &IGbE::cpuPostInt> interEvent;
 151
 152     /** Clear the interupt line to the cpu
 153      */
 154     void cpuClearInt();
 155
 156     Tick intClock() { return Clock::Int::ns * 1024; }
 157
 158     /** This function is used to restart the clock so it can handle things like
 159      * draining and resume in one place. */
 160     void restartClock();
 161
 162     /** Check if all the draining things that need to occur have occured and
 163      * handle the drain event if so.
 164      */
 165     void checkDrain();
 166
 167     template<class T>
 168     class DescCache
 169     {
 170       protected:
 171         virtual Addr descBase() const = 0;
 172         virtual long descHead() const = 0;
 173         virtual long descTail() const = 0;
 174         virtual long descLen() const = 0;
 175         virtual void updateHead(long h) = 0;
 176         virtual void enableSm() = 0;
 177         virtual void intAfterWb() const {}
 178
 179         std::deque<T*> usedCache;
 180         std::deque<T*> unusedCache;
 181
 182         T *fetchBuf;
 183         T *wbBuf;
 184
 185         // Pointer to the device we cache for
 186         IGbE *igbe;
 187
 188         // Name of this  descriptor cache
 189         std::string _name;
 190
 191         // How far we've cached
 192         int cachePnt;
 193
 194         // The size of the descriptor cache
 195         int size;
 196
 197         // How many descriptors we are currently fetching
 198         int curFetching;
 199
 200         // How many descriptors we are currently writing back
 201         int wbOut;
 202
 203         // if the we wrote back to the end of the descriptor ring and are going
 204         // to have to wrap and write more
 205         bool moreToWb;
 206
 207         // What the alignment is of the next descriptor writeback
 208         Addr wbAlignment;
 209
 210        /** The packet that is currently being dmad to memory if any
 211          */
 212         EthPacketPtr pktPtr;
 213
 214       public:
 215         DescCache(IGbE *i, const std::string n, int s)
 216             : igbe(i), _name(n), cachePnt(0), size(s), curFetching(0), wbOut(0),
 217               pktPtr(NULL), fetchEvent(this), wbEvent(this)
 218         {
 219             fetchBuf = new T[size];
 220             wbBuf = new T[size];
 221         }
 222
 223         virtual ~DescCache()
 224         {
 225             reset();
 226         }
 227
 228         std::string name() { return _name; }
 229
 230         /** If the address/len/head change when we've got descriptors that are
 231          * dirty that is very bad. This function checks that we don't and if we
 232          * do panics.
 233          */
 234         void areaChanged()
 235         {
 236             if (usedCache.size() > 0 || curFetching || wbOut)
 237                 panic("Descriptor Address, Length or Head changed. Bad\n");
 238             reset();
 239
 240         }
 241
 242         void writeback(Addr aMask)
 243         {
 244             int curHead = descHead();
 245             int max_to_wb = usedCache.size();
 246
 247             DPRINTF(EthernetDesc, "Writing back descriptors head: %d tail: "
 248                     "%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n",
 249                     curHead, descTail(), descLen(), cachePnt, max_to_wb,
 250                     descLeft());
 251
 252             // Check if this writeback is less restrictive that the previous
 253             // and if so setup another one immediately following it
 254             if (wbOut && (aMask < wbAlignment)) {
 255                 moreToWb = true;
 256                 wbAlignment = aMask;
 257                 DPRINTF(EthernetDesc, "Writing back already in process, returning\n");
 258                 return;
 259             }
 260
 261
 262             moreToWb = false;
 263             wbAlignment = aMask;
 264
 265             if (max_to_wb + curHead >= descLen()) {
 266                 max_to_wb = descLen() - curHead;
 267                 moreToWb = true;
 268                 // this is by definition aligned correctly
 269             } else if (aMask != 0) {
 270                 // align the wb point to the mask
 271                 max_to_wb = max_to_wb & ~aMask;
 272             }
 273
 274             DPRINTF(EthernetDesc, "Writing back %d descriptors\n", max_to_wb);
 275
 276             if (max_to_wb <= 0 || wbOut)
 277                 return;
 278
 279             wbOut = max_to_wb;
 280
 281             for (int x = 0; x < wbOut; x++)
 282                 memcpy(&wbBuf[x], usedCache[x], sizeof(T));
 283
 284             for (int x = 0; x < wbOut; x++) {
 285                 assert(usedCache.size());
 286                 delete usedCache[0];
 287                 usedCache.pop_front();
 288             };
 289
 290
 291             assert(wbOut);
 292             igbe->dmaWrite(igbe->platform->pciToDma(descBase() + curHead * sizeof(T)),
 293                     wbOut * sizeof(T), &wbEvent, (uint8_t*)wbBuf);
 294         }
 295
 296         /** Fetch a chunk of descriptors into the descriptor cache.
 297          * Calls fetchComplete when the memory system returns the data
 298          */
 299         void fetchDescriptors()
 300         {
 301             size_t max_to_fetch;
 302
 303             if (descTail() >= cachePnt)
 304                 max_to_fetch = descTail() - cachePnt;
 305             else
 306                 max_to_fetch = descLen() - cachePnt;
 307
 308
 309             max_to_fetch = std::min(max_to_fetch, (size - usedCache.size() -
 310                         unusedCache.size()));
 311
 312             DPRINTF(EthernetDesc, "Fetching descriptors head: %d tail: "
 313                     "%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n",
 314                     descHead(), descTail(), descLen(), cachePnt,
 315                     max_to_fetch, descLeft());
 316
 317             // Nothing to do
 318             if (max_to_fetch == 0 || curFetching)
 319                 return;
 320
 321             // So we don't have two descriptor fetches going on at once
 322             curFetching = max_to_fetch;
 323
 324             DPRINTF(EthernetDesc, "Fetching descriptors at %#x (%#x), size: %#x\n",
 325                     descBase() + cachePnt * sizeof(T),
 326                     igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)),
 327                     curFetching * sizeof(T));
 328
 329             assert(curFetching);
 330             igbe->dmaRead(igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)),
 331                     curFetching * sizeof(T), &fetchEvent, (uint8_t*)fetchBuf);
 332         }
 333
 334
 335         /** Called by event when dma to read descriptors is completed
 336          */
 337         void fetchComplete()
 338         {
 339             T *newDesc;
 340             for (int x = 0; x < curFetching; x++) {
 341                 newDesc = new T;
 342                 memcpy(newDesc, &fetchBuf[x], sizeof(T));
 343                 unusedCache.push_back(newDesc);
 344             }
 345
 346 #ifndef NDEBUG
 347             int oldCp = cachePnt;
 348 #endif
 349
 350             cachePnt += curFetching;
 351             assert(cachePnt <= descLen());
 352             if (cachePnt == descLen())
 353                 cachePnt = 0;
 354
 355             curFetching = 0;
 356
 357             DPRINTF(EthernetDesc, "Fetching complete cachePnt %d -> %d\n",
 358                     oldCp, cachePnt);
 359
 360             enableSm();
 361             igbe->checkDrain();
 362         }
 363
 364         EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent;
 365
 366         /** Called by event when dma to writeback descriptors is completed
 367          */
 368         void wbComplete()
 369         {
 370             long  curHead = descHead();
 371 #ifndef NDEBUG
 372             long oldHead = curHead;
 373 #endif
 374
 375             curHead += wbOut;
 376             wbOut = 0;
 377
 378             if (curHead >= descLen())
 379                 curHead -= descLen();
 380
 381             // Update the head
 382             updateHead(curHead);
 383
 384             DPRINTF(EthernetDesc, "Writeback complete curHead %d -> %d\n",
 385                     oldHead, curHead);
 386
 387             // If we still have more to wb, call wb now
 388             if (moreToWb) {
 389                 DPRINTF(EthernetDesc, "Writeback has more todo\n");
 390                 writeback(wbAlignment);
 391             }
 392             intAfterWb();
 393             igbe->checkDrain();
 394         }
 395
 396
 397         EventWrapper<DescCache, &DescCache::wbComplete> wbEvent;
 398
 399         /* Return the number of descriptors left in the ring, so the device has
 400          * a way to figure out if it needs to interrupt.
 401          */
 402         int descLeft() const
 403         {
 404             int left = unusedCache.size();
 405             if (cachePnt - descTail() >= 0)
 406                 left += (cachePnt - descTail());
 407             else
 408                 left += (descTail() - cachePnt);
 409
 410             return left;
 411         }
 412
 413         /* Return the number of descriptors used and not written back.
 414          */
 415         int descUsed() const { return usedCache.size(); }
 416
 417         /* Return the number of cache unused descriptors we have. */
 418         int descUnused() const {return unusedCache.size(); }
 419
 420         /* Get into a state where the descriptor address/head/etc colud be
 421          * changed */
 422         void reset()
 423         {
 424             DPRINTF(EthernetDesc, "Reseting descriptor cache\n");
 425             for (int x = 0; x < usedCache.size(); x++)
 426                 delete usedCache[x];
 427             for (int x = 0; x < unusedCache.size(); x++)
 428                 delete unusedCache[x];
 429
 430             usedCache.clear();
 431             unusedCache.clear();
 432
 433             cachePnt = 0;
 434
 435         }
 436
 437         virtual void serialize(std::ostream &os)
 438         {
 439             SERIALIZE_SCALAR(cachePnt);
 440             SERIALIZE_SCALAR(curFetching);
 441             SERIALIZE_SCALAR(wbOut);
 442             SERIALIZE_SCALAR(moreToWb);
 443             SERIALIZE_SCALAR(wbAlignment);
 444
 445             int usedCacheSize = usedCache.size();
 446             SERIALIZE_SCALAR(usedCacheSize);
 447             for(int x = 0; x < usedCacheSize; x++) {
 448                 arrayParamOut(os, csprintf("usedCache_%d", x),
 449                         (uint8_t*)usedCache[x],sizeof(T));
 450             }
 451
 452             int unusedCacheSize = unusedCache.size();
 453             SERIALIZE_SCALAR(unusedCacheSize);
 454             for(int x = 0; x < unusedCacheSize; x++) {
 455                 arrayParamOut(os, csprintf("unusedCache_%d", x),
 456                         (uint8_t*)unusedCache[x],sizeof(T));
 457             }
 458         }
 459
 460         virtual void unserialize(Checkpoint *cp, const std::string &section)
 461         {
 462             UNSERIALIZE_SCALAR(cachePnt);
 463             UNSERIALIZE_SCALAR(curFetching);
 464             UNSERIALIZE_SCALAR(wbOut);
 465             UNSERIALIZE_SCALAR(moreToWb);
 466             UNSERIALIZE_SCALAR(wbAlignment);
 467
 468             int usedCacheSize;
 469             UNSERIALIZE_SCALAR(usedCacheSize);
 470             T *temp;
 471             for(int x = 0; x < usedCacheSize; x++) {
 472                 temp = new T;
 473                 arrayParamIn(cp, section, csprintf("usedCache_%d", x),
 474                         (uint8_t*)temp,sizeof(T));
 475                 usedCache.push_back(temp);
 476             }
 477
 478             int unusedCacheSize;
 479             UNSERIALIZE_SCALAR(unusedCacheSize);
 480             for(int x = 0; x < unusedCacheSize; x++) {
 481                 temp = new T;
 482                 arrayParamIn(cp, section, csprintf("unusedCache_%d", x),
 483                         (uint8_t*)temp,sizeof(T));
 484                 unusedCache.push_back(temp);
 485             }
 486         }
 487         virtual bool hasOutstandingEvents() {
 488             return wbEvent.scheduled() || fetchEvent.scheduled();
 489         }
 490
 491      };
 492
 493
 494     class RxDescCache : public DescCache<iGbReg::RxDesc>
 495     {
 496       protected:
 497         virtual Addr descBase() const { return igbe->regs.rdba(); }
 498         virtual long descHead() const { return igbe->regs.rdh(); }
 499         virtual long descLen() const { return igbe->regs.rdlen() >> 4; }
 500         virtual long descTail() const { return igbe->regs.rdt(); }
 501         virtual void updateHead(long h) { igbe->regs.rdh(h); }
 502         virtual void enableSm();
 503
 504         bool pktDone;
 505
 506       public:
 507         RxDescCache(IGbE *i, std::string n, int s);
 508
 509         /** Write the given packet into the buffer(s) pointed to by the
 510          * descriptor and update the book keeping. Should only be called when
 511          * there are no dma's pending.
 512          * @param packet ethernet packet to write
 513          * @return if the packet could be written (there was a free descriptor)
 514          */
 515         bool writePacket(EthPacketPtr packet);
 516         /** Called by event when dma to write packet is completed
 517          */
 518         void pktComplete();
 519
 520         /** Check if the dma on the packet has completed.
 521          */
 522
 523         bool packetDone();
 524
 525         EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent;
 526
 527         virtual bool hasOutstandingEvents();
 528
 529         virtual void serialize(std::ostream &os);
 530         virtual void unserialize(Checkpoint *cp, const std::string &section);
 531     };
 532     friend class RxDescCache;
 533
 534     RxDescCache rxDescCache;
 535
 536     class TxDescCache  : public DescCache<iGbReg::TxDesc>
 537     {
 538       protected:
 539         virtual Addr descBase() const { return igbe->regs.tdba(); }
 540         virtual long descHead() const { return igbe->regs.tdh(); }
 541         virtual long descTail() const { return igbe->regs.tdt(); }
 542         virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
 543         virtual void updateHead(long h) { igbe->regs.tdh(h); }
 544         virtual void enableSm();
 545         virtual void intAfterWb() const { igbe->postInterrupt(iGbReg::IT_TXDW);}
 546
 547         bool pktDone;
 548         bool isTcp;
 549         bool pktWaiting;
 550
 551       public:
 552         TxDescCache(IGbE *i, std::string n, int s);
 553
 554         /** Tell the cache to DMA a packet from main memory into its buffer and
 555          * return the size the of the packet to reserve space in tx fifo.
 556          * @return size of the packet
 557          */
 558         int getPacketSize();
 559         void getPacketData(EthPacketPtr p);
 560
 561         /** Ask if the packet has been transfered so the state machine can give
 562          * it to the fifo.
 563          * @return packet available in descriptor cache
 564          */
 565         bool packetAvailable();
 566
 567         /** Ask if we are still waiting for the packet to be transfered.
 568          * @return packet still in transit.
 569          */
 570         bool packetWaiting() { return pktWaiting; }
 571
 572         /** Called by event when dma to write packet is completed
 573          */
 574         void pktComplete();
 575         EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent;
 576
 577         virtual bool hasOutstandingEvents();
 578
 579         virtual void serialize(std::ostream &os);
 580         virtual void unserialize(Checkpoint *cp, const std::string &section);
 581
 582     };
 583     friend class TxDescCache;
 584
 585     TxDescCache txDescCache;
 586
 587   public:
 588     struct Params : public PciDev::Params
 589     {
 590         Net::EthAddr hardware_address;
 591         bool use_flow_control;
 592         int rx_fifo_size;
 593         int tx_fifo_size;
 594         int rx_desc_cache_size;
 595         int tx_desc_cache_size;
 596         Tick clock;
 597     };
 598
 599     IGbE(Params *params);
 600     ~IGbE() {;}
 601
 602     Tick clock;
 603     inline Tick cycles(int numCycles) const { return numCycles * clock; }
 604
 605     virtual Tick read(PacketPtr pkt);
 606     virtual Tick write(PacketPtr pkt);
 607
 608     virtual Tick writeConfig(PacketPtr pkt);
 609
 610     bool ethRxPkt(EthPacketPtr packet);
 611     void ethTxDone();
 612
 613     void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
 614
 615
 616     const Params *params() const {return (const Params *)_params; }
 617
 618     virtual void serialize(std::ostream &os);
 619     virtual void unserialize(Checkpoint *cp, const std::string &section);
 620     virtual unsigned int drain(Event *de);
 621     virtual void resume();
 622
 623 };
 624
 625 class IGbEInt : public EtherInt
 626 {
 627   private:
 628     IGbE *dev;
 629
 630   public:
 631     IGbEInt(const std::string &name, IGbE *d)
 632         : EtherInt(name), dev(d)
 633         { dev->setEthInt(this); }
 634
 635     virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
 636     virtual void sendDone() { dev->ethTxDone(); }
 637 };
 638
 639
 640
 641
 642
 643 #endif //__DEV_I8254XGBE_HH__
 644