src/dev/i8254xGBe_defs.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  */
  30
  31 /* @file
  32  * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers.
  33  */
  34 #include "base/bitfield.hh"
  35
  36 namespace iGbReg {
  37
  38
  39 // Registers used by the Intel GbE NIC
  40 const uint32_t REG_CTRL     = 0x00000;
  41 const uint32_t REG_STATUS   = 0x00008;
  42 const uint32_t REG_EECD     = 0x00010;
  43 const uint32_t REG_EERD     = 0x00014;
  44 const uint32_t REG_CTRL_EXT = 0x00018;
  45 const uint32_t REG_MDIC     = 0x00020;
  46 const uint32_t REG_FCAL     = 0x00028;
  47 const uint32_t REG_FCAH     = 0x0002C;
  48 const uint32_t REG_FCT      = 0x00030;
  49 const uint32_t REG_VET      = 0x00038;
  50 const uint32_t REG_PBA      = 0x01000;
  51 const uint32_t REG_ICR      = 0x000C0;
  52 const uint32_t REG_ITR      = 0x000C4;
  53 const uint32_t REG_ICS      = 0x000C8;
  54 const uint32_t REG_IMS      = 0x000D0;
  55 const uint32_t REG_IMC      = 0x000D8;
  56 const uint32_t REG_IAM      = 0x000E0;
  57 const uint32_t REG_RCTL     = 0x00100;
  58 const uint32_t REG_FCTTV    = 0x00170;
  59 const uint32_t REG_TIPG     = 0x00410;
  60 const uint32_t REG_AIFS     = 0x00458;
  61 const uint32_t REG_LEDCTL   = 0x00e00;
  62 const uint32_t REG_FCRTL    = 0x02160;
  63 const uint32_t REG_FCRTH    = 0x02168;
  64 const uint32_t REG_RDBAL    = 0x02800;
  65 const uint32_t REG_RDBAH    = 0x02804;
  66 const uint32_t REG_RDLEN    = 0x02808;
  67 const uint32_t REG_RDH      = 0x02810;
  68 const uint32_t REG_RDT      = 0x02818;
  69 const uint32_t REG_RDTR     = 0x02820;
  70 const uint32_t REG_RXDCTL   = 0x02828;
  71 const uint32_t REG_RADV     = 0x0282C;
  72 const uint32_t REG_TCTL     = 0x00400;
  73 const uint32_t REG_TDBAL    = 0x03800;
  74 const uint32_t REG_TDBAH    = 0x03804;
  75 const uint32_t REG_TDLEN    = 0x03808;
  76 const uint32_t REG_TDH      = 0x03810;
  77 const uint32_t REG_TDT      = 0x03818;
  78 const uint32_t REG_TIDV     = 0x03820;
  79 const uint32_t REG_TXDCTL   = 0x03828;
  80 const uint32_t REG_TADV     = 0x0382C;
  81 const uint32_t REG_CRCERRS  = 0x04000;
  82 const uint32_t REG_RXCSUM   = 0x05000;
  83 const uint32_t REG_MTA      = 0x05200;
  84 const uint32_t REG_RAL      = 0x05400;
  85 const uint32_t REG_RAH      = 0x05404;
  86 const uint32_t REG_VFTA     = 0x05600;
  87
  88 const uint32_t REG_WUC      = 0x05800;
  89 const uint32_t REG_MANC     = 0x05820;
  90
  91 const uint8_t EEPROM_READ_OPCODE_SPI    = 0x03;
  92 const uint8_t EEPROM_RDSR_OPCODE_SPI    = 0x05;
  93 const uint8_t EEPROM_SIZE               = 64;
  94 const uint16_t EEPROM_CSUM              = 0xBABA;
  95
  96 const uint8_t VLAN_FILTER_TABLE_SIZE    = 128;
  97 const uint8_t RCV_ADDRESS_TABLE_SIZE    = 16;
  98 const uint8_t MULTICAST_TABLE_SIZE      = 128;
  99 const uint32_t STATS_REGS_SIZE           = 0x124;
 100
 101
 102 // Registers in that are accessed in the PHY
 103 const uint8_t PHY_PSTATUS       = 0x1;
 104 const uint8_t PHY_PID           = 0x2;
 105 const uint8_t PHY_EPID          = 0x3;
 106 const uint8_t PHY_GSTATUS       = 10;
 107 const uint8_t PHY_EPSTATUS      = 15;
 108 const uint8_t PHY_AGC           = 18;
 109
 110 // Receive Descriptor Status Flags
 111 const uint8_t RXDS_PIF         = 0x80;
 112 const uint8_t RXDS_IPCS        = 0x40;
 113 const uint8_t RXDS_TCPCS       = 0x20;
 114 const uint8_t RXDS_UDPCS       = 0x10;
 115 const uint8_t RXDS_VP          = 0x08;
 116 const uint8_t RXDS_IXSM        = 0x04;
 117 const uint8_t RXDS_EOP         = 0x02;
 118 const uint8_t RXDS_DD          = 0x01;
 119
 120 // Receive Descriptor Error Flags
 121 const uint8_t RXDE_RXE         = 0x80;
 122 const uint8_t RXDE_IPE         = 0x40;
 123 const uint8_t RXDE_TCPE        = 0x20;
 124 const uint8_t RXDE_SEQ         = 0x04;
 125 const uint8_t RXDE_SE          = 0x02;
 126 const uint8_t RXDE_CE          = 0x01;
 127
 128 // Interrupt types
 129 enum IntTypes
 130 {
 131     IT_NONE    = 0x00000, //dummy value
 132     IT_TXDW    = 0x00001,
 133     IT_TXQE    = 0x00002,
 134     IT_LSC     = 0x00004,
 135     IT_RXSEQ   = 0x00008,
 136     IT_RXDMT   = 0x00010,
 137     IT_RXO     = 0x00040,
 138     IT_RXT     = 0x00080,
 139     IT_MADC    = 0x00200,
 140     IT_RXCFG   = 0x00400,
 141     IT_GPI0    = 0x02000,
 142     IT_GPI1    = 0x04000,
 143     IT_TXDLOW  = 0x08000,
 144     IT_SRPD    = 0x10000,
 145     IT_ACK     = 0x20000
 146 };
 147
 148 // Receive Descriptor struct
 149 struct RxDesc {
 150     Addr buf;
 151     uint16_t len;
 152     uint16_t csum;
 153     uint8_t status;
 154     uint8_t errors;
 155     uint16_t vlan;
 156 };
 157
 158 struct TxDesc {
 159     uint64_t d1;
 160     uint64_t d2;
 161 };
 162
 163 namespace TxdOp {
 164 const uint8_t TXD_CNXT = 0x0;
 165 const uint8_t TXD_DATA = 0x1;
 166
 167 bool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); }
 168 uint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); }
 169 bool isContext(TxDesc *d) { return !isLegacy(d) && getType(d) == TXD_CNXT; }
 170 bool isData(TxDesc *d) { return !isLegacy(d) && getType(d) == TXD_DATA; }
 171
 172 Addr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; }
 173 Addr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); }
 174 void setDd(TxDesc *d)
 175 {
 176     replaceBits(d->d2, 35, 32, ULL(1));
 177 }
 178
 179 bool ide(TxDesc *d)  { return bits(d->d2, 31,31); }
 180 bool vle(TxDesc *d)  { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); }
 181 bool rs(TxDesc *d)   { return bits(d->d2, 27,27); }
 182 bool ic(TxDesc *d)   { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); }
 183 bool tse(TxDesc *d)  { return (isData(d) || isContext(d)) && bits(d->d2, 26,26); }
 184 bool ifcs(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 25,25); }
 185 bool eop(TxDesc *d)  { assert(isLegacy(d) || isData(d)); return bits(d->d2, 24,24); }
 186 bool ip(TxDesc *d)   { assert(isContext(d)); return bits(d->d2, 25,25); }
 187 bool tcp(TxDesc *d)  { assert(isContext(d)); return bits(d->d2, 24,24); }
 188
 189 uint8_t getCso(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 23,16); }
 190 uint8_t getCss(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 47,40); }
 191
 192 bool ixsm(TxDesc *d)  { return isData(d) && bits(d->d2, 40,40); }
 193 bool txsm(TxDesc *d)  { return isData(d) && bits(d->d2, 41,41); }
 194
 195 int tucse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,63,48); }
 196 int tucso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,47,40); }
 197 int tucss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,39,32); }
 198 int ipcse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,31,16); }
 199 int ipcso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,15,8); }
 200 int ipcss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,7,0); }
 201 int mss(TxDesc *d) { assert(isContext(d)); return bits(d->d2,63,48); }
 202 int hdrlen(TxDesc *d) { assert(isContext(d)); return bits(d->d2,47,40); }
 203 } // namespace TxdOp
 204
 205
 206 #define ADD_FIELD32(NAME, OFFSET, BITS) \
 207     inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
 208     inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
 209
 210 #define ADD_FIELD64(NAME, OFFSET, BITS) \
 211     inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
 212     inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
 213
 214 struct Regs {
 215     template<class T>
 216     struct Reg {
 217         T _data;
 218         T operator()() { return _data; }
 219         const Reg<T> &operator=(T d) { _data = d; return *this;}
 220         bool operator==(T d) { return d == _data; }
 221         void operator()(T d) { _data = d; }
 222         Reg() { _data = 0; }
 223         void serialize(std::ostream &os)
 224         {
 225             SERIALIZE_SCALAR(_data);
 226         }
 227         void unserialize(Checkpoint *cp, const std::string &section)
 228         {
 229             UNSERIALIZE_SCALAR(_data);
 230         }
 231     };
 232
 233     struct CTRL : public Reg<uint32_t> { // 0x0000 CTRL Register
 234         using Reg<uint32_t>::operator=;
 235         ADD_FIELD32(fd,0,1);       // full duplex
 236         ADD_FIELD32(bem,1,1);      // big endian mode
 237         ADD_FIELD32(pcipr,2,1);    // PCI priority
 238         ADD_FIELD32(lrst,3,1);     // link reset
 239         ADD_FIELD32(tme,4,1);      // test mode enable
 240         ADD_FIELD32(asde,5,1);     // Auto-speed detection
 241         ADD_FIELD32(slu,6,1);      // Set link up
 242         ADD_FIELD32(ilos,7,1);     // invert los-of-signal
 243         ADD_FIELD32(speed,8,2);    // speed selection bits
 244         ADD_FIELD32(be32,10,1);    // big endian mode 32
 245         ADD_FIELD32(frcspd,11,1);  // force speed
 246         ADD_FIELD32(frcdpx,12,1);  // force duplex
 247         ADD_FIELD32(duden,13,1);   // dock/undock enable
 248         ADD_FIELD32(dudpol,14,1);  // dock/undock polarity
 249         ADD_FIELD32(fphyrst,15,1); // force phy reset
 250         ADD_FIELD32(extlen,16,1);  // external link status enable
 251         ADD_FIELD32(rsvd,17,1);    // reserved
 252         ADD_FIELD32(sdp0d,18,1);   // software controlled pin data
 253         ADD_FIELD32(sdp1d,19,1);   // software controlled pin data
 254         ADD_FIELD32(sdp2d,20,1);   // software controlled pin data
 255         ADD_FIELD32(sdp3d,21,1);   // software controlled pin data
 256         ADD_FIELD32(sdp0i,22,1);   // software controlled pin dir
 257         ADD_FIELD32(sdp1i,23,1);   // software controlled pin dir
 258         ADD_FIELD32(sdp2i,24,1);   // software controlled pin dir
 259         ADD_FIELD32(sdp3i,25,1);   // software controlled pin dir
 260         ADD_FIELD32(rst,26,1);     // reset
 261         ADD_FIELD32(rfce,27,1);    // receive flow control enable
 262         ADD_FIELD32(tfce,28,1);    // transmit flow control enable
 263         ADD_FIELD32(rte,29,1);     // routing tag enable
 264         ADD_FIELD32(vme,30,1);     // vlan enable
 265         ADD_FIELD32(phyrst,31,1);  // phy reset
 266     };
 267     CTRL ctrl;
 268
 269     struct STATUS : public Reg<uint32_t> { // 0x0008 STATUS Register
 270         using Reg<uint32_t>::operator=;
 271         ADD_FIELD32(fd,0,1);       // full duplex
 272         ADD_FIELD32(lu,1,1);       // link up
 273         ADD_FIELD32(func,2,2);     // function id
 274         ADD_FIELD32(txoff,4,1);    // transmission paused
 275         ADD_FIELD32(tbimode,5,1);  // tbi mode
 276         ADD_FIELD32(speed,6,2);    // link speed
 277         ADD_FIELD32(asdv,8,2);     // auto speed detection value
 278         ADD_FIELD32(mtxckok,10,1); // mtx clock running ok
 279         ADD_FIELD32(pci66,11,1);   // In 66Mhz pci slot
 280         ADD_FIELD32(bus64,12,1);   // in 64 bit slot
 281         ADD_FIELD32(pcix,13,1);    // Pci mode
 282         ADD_FIELD32(pcixspd,14,2); // pci x speed
 283     };
 284     STATUS sts;
 285
 286     struct EECD : public Reg<uint32_t> { // 0x0010 EECD Register
 287         using Reg<uint32_t>::operator=;
 288         ADD_FIELD32(sk,0,1);       // clack input to the eeprom
 289         ADD_FIELD32(cs,1,1);       // chip select to eeprom
 290         ADD_FIELD32(din,2,1);      // data input to eeprom
 291         ADD_FIELD32(dout,3,1);     // data output bit
 292         ADD_FIELD32(fwe,4,2);      // flash write enable
 293         ADD_FIELD32(ee_req,6,1);   // request eeprom access
 294         ADD_FIELD32(ee_gnt,7,1);   // grant eeprom access
 295         ADD_FIELD32(ee_pres,8,1);  // eeprom present
 296         ADD_FIELD32(ee_size,9,1);  // eeprom size
 297         ADD_FIELD32(ee_sz1,10,1);  // eeprom size
 298         ADD_FIELD32(rsvd,11,2);    // reserved
 299         ADD_FIELD32(ee_type,13,1); // type of eeprom
 300     } ;
 301     EECD eecd;
 302
 303     struct EERD : public Reg<uint32_t> { // 0x0014 EERD Register
 304         using Reg<uint32_t>::operator=;
 305         ADD_FIELD32(start,0,1);  // start read
 306         ADD_FIELD32(done,4,1);   // done read
 307         ADD_FIELD32(addr,8,8);   // address
 308         ADD_FIELD32(data,16,16); // data
 309     };
 310     EERD eerd;
 311
 312     struct CTRL_EXT : public Reg<uint32_t> { // 0x0018 CTRL_EXT Register
 313         using Reg<uint32_t>::operator=;
 314         ADD_FIELD32(gpi_en,0,4);      // enable interrupts from gpio
 315         ADD_FIELD32(phyint,5,1);      // reads the phy internal int status
 316         ADD_FIELD32(sdp2_data,6,1);   // data from gpio sdp
 317         ADD_FIELD32(spd3_data,7,1);   // data frmo gpio sdp
 318         ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2
 319         ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2
 320         ADD_FIELD32(asdchk,12,1);     // initiate auto-speed-detection
 321         ADD_FIELD32(eerst,13,1);      // reset the eeprom
 322         ADD_FIELD32(spd_byps,15,1);   // bypass speed select
 323         ADD_FIELD32(ro_dis,17,1);     // disable relaxed memory ordering
 324         ADD_FIELD32(vreg,21,1);       // power down the voltage regulator
 325         ADD_FIELD32(link_mode,22,2);  // interface to talk to the link
 326         ADD_FIELD32(iame, 27,1);      // interrupt acknowledge auto-mask ??
 327         ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device
 328         ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ??
 329     };
 330     CTRL_EXT ctrl_ext;
 331
 332     struct MDIC : public Reg<uint32_t> { // 0x0020 MDIC Register
 333         using Reg<uint32_t>::operator=;
 334         ADD_FIELD32(data,0,16);   // data
 335         ADD_FIELD32(regadd,16,5); // register address
 336         ADD_FIELD32(phyadd,21,5); // phy addresses
 337         ADD_FIELD32(op,26,2);     // opcode
 338         ADD_FIELD32(r,28,1);      // ready
 339         ADD_FIELD32(i,29,1);      // interrupt
 340         ADD_FIELD32(e,30,1);      // error
 341     };
 342     MDIC mdic;
 343
 344     struct ICR : public Reg<uint32_t> { // 0x00C0 ICR Register
 345         using Reg<uint32_t>::operator=;
 346         ADD_FIELD32(txdw,0,1)   // tx descr witten back
 347         ADD_FIELD32(txqe,1,1)   // tx queue empty
 348         ADD_FIELD32(lsc,2,1)    // link status change
 349         ADD_FIELD32(rxseq,3,1)  // rcv sequence error
 350         ADD_FIELD32(rxdmt0,4,1) // rcv descriptor min thresh
 351         ADD_FIELD32(rsvd1,5,1)  // reserved
 352         ADD_FIELD32(rxo,6,1)    // receive overrunn
 353         ADD_FIELD32(rxt0,7,1)   // receiver timer interrupt
 354         ADD_FIELD32(mdac,9,1)   // mdi/o access complete
 355         ADD_FIELD32(rxcfg,10,1)  // recv /c/ ordered sets
 356         ADD_FIELD32(phyint,12,1) // phy interrupt
 357         ADD_FIELD32(gpi1,13,1)   // gpi int 1
 358         ADD_FIELD32(gpi2,14,1)   // gpi int 2
 359         ADD_FIELD32(txdlow,15,1) // transmit desc low thresh
 360         ADD_FIELD32(srpd,16,1)   // small receive packet detected
 361         ADD_FIELD32(ack,17,1);    // receive ack frame
 362         ADD_FIELD32(int_assert, 31,1); // interrupt caused a system interrupt
 363     };
 364     ICR icr;
 365
 366     uint32_t imr; // register that contains the current interrupt mask
 367
 368     struct ITR : public Reg<uint32_t> { // 0x00C4 ITR Register
 369         using Reg<uint32_t>::operator=;
 370         ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval
 371                                      // specified in 256ns interrupts
 372     };
 373     ITR itr;
 374
 375     // When CTRL_EXT.IAME and the ICR.INT_ASSERT is 1 an ICR read or write
 376     // causes the IAM register contents to be written into the IMC
 377     // automatically clearing all interrupts that have a bit in the IAM set
 378     uint32_t iam;
 379
 380     struct RCTL : public Reg<uint32_t> { // 0x0100 RCTL Register
 381         using Reg<uint32_t>::operator=;
 382         ADD_FIELD32(rst,0,1);   // Reset
 383         ADD_FIELD32(en,1,1);    // Enable
 384         ADD_FIELD32(sbp,2,1);   // Store bad packets
 385         ADD_FIELD32(upe,3,1);   // Unicast Promiscuous enabled
 386         ADD_FIELD32(mpe,4,1);   // Multicast promiscuous enabled
 387         ADD_FIELD32(lpe,5,1);   // long packet reception enabled
 388         ADD_FIELD32(lbm,6,2);   //
 389         ADD_FIELD32(rdmts,8,2); //
 390         ADD_FIELD32(mo,12,2);    //
 391         ADD_FIELD32(mdr,14,1);   //
 392         ADD_FIELD32(bam,15,1);   //
 393         ADD_FIELD32(bsize,16,2); //
 394         ADD_FIELD32(vfe,18,1);   //
 395         ADD_FIELD32(cfien,19,1); //
 396         ADD_FIELD32(cfi,20,1);   //
 397         ADD_FIELD32(dpf,22,1);   // discard pause frames
 398         ADD_FIELD32(pmcf,23,1);  // pass mac control  frames
 399         ADD_FIELD32(bsex,25,1);  // buffer size extension
 400         ADD_FIELD32(secrc,26,1); // strip ethernet crc from incoming packet
 401         int descSize()
 402         {
 403             switch(bsize()) {
 404                 case 0: return bsex() == 0 ? 2048 : -1;
 405                 case 1: return bsex() == 0 ? 1024 : 16384;
 406                 case 2: return bsex() == 0 ? 512 : 8192;
 407                 case 3: return bsex() == 0 ? 256 : 4096;
 408                 default:
 409                         return -1;
 410             }
 411         }
 412     };
 413     RCTL rctl;
 414
 415     struct FCTTV : public Reg<uint32_t> { // 0x0170 FCTTV
 416         using Reg<uint32_t>::operator=;
 417         ADD_FIELD32(ttv,0,16);    // Transmit Timer Value
 418     };
 419     FCTTV fcttv;
 420
 421     struct TCTL : public Reg<uint32_t> { // 0x0400 TCTL Register
 422         using Reg<uint32_t>::operator=;
 423         ADD_FIELD32(rst,0,1);    // Reset
 424         ADD_FIELD32(en,1,1);     // Enable
 425         ADD_FIELD32(bce,2,1);    // busy check enable
 426         ADD_FIELD32(psp,3,1);    // pad short packets
 427         ADD_FIELD32(ct,4,8);     // collision threshold
 428         ADD_FIELD32(cold,12,10); // collision distance
 429         ADD_FIELD32(swxoff,22,1); // software xoff transmission
 430         ADD_FIELD32(pbe,23,1);    // packet burst enable
 431         ADD_FIELD32(rtlc,24,1);   // retransmit late collisions
 432         ADD_FIELD32(nrtu,25,1);   // on underrun no TX
 433         ADD_FIELD32(mulr,26,1);   // multiple request
 434     };
 435     TCTL tctl;
 436
 437     struct PBA : public Reg<uint32_t> { // 0x1000 PBA Register
 438         using Reg<uint32_t>::operator=;
 439         ADD_FIELD32(rxa,0,16);
 440         ADD_FIELD32(txa,16,16);
 441     };
 442     PBA pba;
 443
 444     struct FCRTL : public Reg<uint32_t> { // 0x2160 FCRTL Register
 445         using Reg<uint32_t>::operator=;
 446         ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have
 447                                // a larger buffer
 448         ADD_FIELD32(xone, 31,1);
 449     };
 450     FCRTL fcrtl;
 451
 452     struct FCRTH : public Reg<uint32_t> { // 0x2168 FCRTL Register
 453         using Reg<uint32_t>::operator=;
 454         ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have
 455                                //a larger buffer
 456         ADD_FIELD32(xfce, 31,1);
 457     };
 458     FCRTH fcrth;
 459
 460     struct RDBA : public Reg<uint64_t> { // 0x2800 RDBA Register
 461         using Reg<uint64_t>::operator=;
 462         ADD_FIELD64(rdbal,0,32); // base address of rx descriptor ring
 463         ADD_FIELD64(rdbah,32,32); // base address of rx descriptor ring
 464     };
 465     RDBA rdba;
 466
 467     struct RDLEN : public Reg<uint32_t> { // 0x2808 RDLEN Register
 468         using Reg<uint32_t>::operator=;
 469         ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
 470     };
 471     RDLEN rdlen;
 472
 473     struct RDH : public Reg<uint32_t> { // 0x2810 RDH Register
 474         using Reg<uint32_t>::operator=;
 475         ADD_FIELD32(rdh,0,16); // head of the descriptor ring
 476     };
 477     RDH rdh;
 478
 479     struct RDT : public Reg<uint32_t> { // 0x2818 RDT Register
 480         using Reg<uint32_t>::operator=;
 481         ADD_FIELD32(rdt,0,16); // tail of the descriptor ring
 482     };
 483     RDT rdt;
 484
 485     struct RDTR : public Reg<uint32_t> { // 0x2820 RDTR Register
 486         using Reg<uint32_t>::operator=;
 487         ADD_FIELD32(delay,0,16); // receive delay timer
 488         ADD_FIELD32(fpd, 31,1);   // flush partial descriptor block ??
 489     };
 490     RDTR rdtr;
 491
 492     struct RXDCTL : public Reg<uint32_t> { // 0x2828 RXDCTL Register
 493         using Reg<uint32_t>::operator=;
 494         ADD_FIELD32(pthresh,0,6);   // prefetch threshold, less that this
 495                                     // consider prefetch
 496         ADD_FIELD32(hthresh,8,6);   // number of descriptors in host mem to
 497                                     // consider prefetch
 498         ADD_FIELD32(wthresh,16,6);  // writeback threshold
 499         ADD_FIELD32(gran,24,1);     // granularity 0 = desc, 1 = cacheline
 500     };
 501     RXDCTL rxdctl;
 502
 503     struct RADV : public Reg<uint32_t> { // 0x282C RADV Register
 504         using Reg<uint32_t>::operator=;
 505         ADD_FIELD32(idv,0,16); // absolute interrupt delay
 506     };
 507     RADV radv;
 508
 509     struct RSRPD : public Reg<uint32_t> { // 0x2C00 RSRPD Register
 510         using Reg<uint32_t>::operator=;
 511         ADD_FIELD32(idv,0,12); // size to interrutp on small packets
 512     };
 513     RSRPD rsrpd;
 514
 515     struct TDBA : public Reg<uint64_t> { // 0x3800 TDBAL Register
 516         using Reg<uint64_t>::operator=;
 517         ADD_FIELD64(tdbal,0,32); // base address of transmit descriptor ring
 518         ADD_FIELD64(tdbah,32,32); // base address of transmit descriptor ring
 519     };
 520     TDBA tdba;
 521
 522     struct TDLEN : public Reg<uint32_t> { // 0x3808 TDLEN Register
 523         using Reg<uint32_t>::operator=;
 524         ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
 525     };
 526     TDLEN tdlen;
 527
 528     struct TDH : public Reg<uint32_t> { // 0x3810 TDH Register
 529         using Reg<uint32_t>::operator=;
 530         ADD_FIELD32(tdh,0,16); // head of the descriptor ring
 531     };
 532     TDH tdh;
 533
 534     struct TDT : public Reg<uint32_t> { // 0x3818 TDT Register
 535         using Reg<uint32_t>::operator=;
 536         ADD_FIELD32(tdt,0,16); // tail of the descriptor ring
 537     };
 538     TDT tdt;
 539
 540     struct TIDV : public Reg<uint32_t> { // 0x3820 TIDV Register
 541         using Reg<uint32_t>::operator=;
 542         ADD_FIELD32(idv,0,16); // interrupt delay
 543     };
 544     TIDV tidv;
 545
 546     struct TXDCTL : public Reg<uint32_t> { // 0x3828 TXDCTL Register
 547         using Reg<uint32_t>::operator=;
 548         ADD_FIELD32(pthresh, 0,6);  // if number of descriptors control has is
 549                                     // below this number, a prefetch is considered
 550         ADD_FIELD32(hthresh,8,8);   // number of valid descriptors is host memory
 551                                     // before a prefetch is considered
 552         ADD_FIELD32(wthresh,16,6);  // number of descriptors to keep until
 553                                     // writeback is considered
 554         ADD_FIELD32(gran, 24,1);    // granulatiry of above values (0 = cacheline,
 555                                     // 1 == desscriptor)
 556         ADD_FIELD32(lwthresh,25,7); // xmit descriptor low thresh, interrupt
 557                                     // below this level
 558     };
 559     TXDCTL txdctl;
 560
 561     struct TADV : public Reg<uint32_t> { // 0x382C TADV Register
 562         using Reg<uint32_t>::operator=;
 563         ADD_FIELD32(idv,0,16); // absolute interrupt delay
 564     };
 565     TADV tadv;
 566
 567     struct RXCSUM : public Reg<uint32_t> { // 0x5000 RXCSUM Register
 568         using Reg<uint32_t>::operator=;
 569         ADD_FIELD32(pcss,0,8);
 570         ADD_FIELD32(ipofld,8,1);
 571         ADD_FIELD32(tuofld,9,1);
 572     };
 573     RXCSUM rxcsum;
 574
 575     struct MANC : public Reg<uint32_t> { // 0x5820 MANC Register
 576         using Reg<uint32_t>::operator=;
 577         ADD_FIELD32(smbus,0,1);    // SMBus enabled #####
 578         ADD_FIELD32(asf,1,1);      // ASF enabled #####
 579         ADD_FIELD32(ronforce,2,1); // reset of force
 580         ADD_FIELD32(rsvd,3,5);     // reserved
 581         ADD_FIELD32(rmcp1,8,1);    // rcmp1 filtering
 582         ADD_FIELD32(rmcp2,9,1);    // rcmp2 filtering
 583         ADD_FIELD32(ipv4,10,1);     // enable ipv4
 584         ADD_FIELD32(ipv6,11,1);     // enable ipv6
 585         ADD_FIELD32(snap,12,1);     // accept snap
 586         ADD_FIELD32(arp,13,1);      // filter arp #####
 587         ADD_FIELD32(neighbor,14,1); // neighbor discovery
 588         ADD_FIELD32(arp_resp,15,1); // arp response
 589         ADD_FIELD32(tcorst,16,1);   // tco reset happened
 590         ADD_FIELD32(rcvtco,17,1);   // receive tco enabled ######
 591         ADD_FIELD32(blkphyrst,18,1);// block phy resets ########
 592         ADD_FIELD32(rcvall,19,1);   // receive all
 593         ADD_FIELD32(macaddrfltr,20,1); // mac address filtering ######
 594         ADD_FIELD32(mng2host,21,1); // mng2 host packets #######
 595         ADD_FIELD32(ipaddrfltr,22,1); // ip address filtering
 596         ADD_FIELD32(xsumfilter,23,1); // checksum filtering
 597         ADD_FIELD32(brfilter,24,1); // broadcast filtering
 598         ADD_FIELD32(smbreq,25,1);   // smb request
 599         ADD_FIELD32(smbgnt,26,1);   // smb grant
 600         ADD_FIELD32(smbclkin,27,1); // smbclkin
 601         ADD_FIELD32(smbdatain,28,1); // smbdatain
 602         ADD_FIELD32(smbdataout,29,1); // smb data out
 603         ADD_FIELD32(smbclkout,30,1); // smb clock out
 604     };
 605     MANC manc;
 606
 607     void serialize(std::ostream &os)
 608     {
 609         paramOut(os, "ctrl", ctrl._data);
 610         paramOut(os, "sts", sts._data);
 611         paramOut(os, "eecd", eecd._data);
 612         paramOut(os, "eerd", eerd._data);
 613         paramOut(os, "ctrl_ext", ctrl_ext._data);
 614         paramOut(os, "mdic", mdic._data);
 615         paramOut(os, "icr", icr._data);
 616         SERIALIZE_SCALAR(imr);
 617         paramOut(os, "itr", itr._data);
 618         SERIALIZE_SCALAR(iam);
 619         paramOut(os, "rctl", rctl._data);
 620         paramOut(os, "fcttv", fcttv._data);
 621         paramOut(os, "tctl", tctl._data);
 622         paramOut(os, "pba", pba._data);
 623         paramOut(os, "fcrtl", fcrtl._data);
 624         paramOut(os, "fcrth", fcrth._data);
 625         paramOut(os, "rdba", rdba._data);
 626         paramOut(os, "rdlen", rdlen._data);
 627         paramOut(os, "rdh", rdh._data);
 628         paramOut(os, "rdt", rdt._data);
 629         paramOut(os, "rdtr", rdtr._data);
 630         paramOut(os, "rxdctl", rxdctl._data);
 631         paramOut(os, "radv", radv._data);
 632         paramOut(os, "rsrpd", rsrpd._data);
 633         paramOut(os, "tdba", tdba._data);
 634         paramOut(os, "tdlen", tdlen._data);
 635         paramOut(os, "tdh", tdh._data);
 636         paramOut(os, "tdt", tdt._data);
 637         paramOut(os, "tidv", tidv._data);
 638         paramOut(os, "txdctl", txdctl._data);
 639         paramOut(os, "tadv", tadv._data);
 640         paramOut(os, "rxcsum", rxcsum._data);
 641         paramOut(os, "manc", manc._data);
 642     }
 643
 644     void unserialize(Checkpoint *cp, const std::string &section)
 645     {
 646         paramIn(cp, section, "ctrl", ctrl._data);
 647         paramIn(cp, section, "sts", sts._data);
 648         paramIn(cp, section, "eecd", eecd._data);
 649         paramIn(cp, section, "eerd", eerd._data);
 650         paramIn(cp, section, "ctrl_ext", ctrl_ext._data);
 651         paramIn(cp, section, "mdic", mdic._data);
 652         paramIn(cp, section, "icr", icr._data);
 653         UNSERIALIZE_SCALAR(imr);
 654         paramIn(cp, section, "itr", itr._data);
 655         UNSERIALIZE_SCALAR(iam);
 656         paramIn(cp, section, "rctl", rctl._data);
 657         paramIn(cp, section, "fcttv", fcttv._data);
 658         paramIn(cp, section, "tctl", tctl._data);
 659         paramIn(cp, section, "pba", pba._data);
 660         paramIn(cp, section, "fcrtl", fcrtl._data);
 661         paramIn(cp, section, "fcrth", fcrth._data);
 662         paramIn(cp, section, "rdba", rdba._data);
 663         paramIn(cp, section, "rdlen", rdlen._data);
 664         paramIn(cp, section, "rdh", rdh._data);
 665         paramIn(cp, section, "rdt", rdt._data);
 666         paramIn(cp, section, "rdtr", rdtr._data);
 667         paramIn(cp, section, "rxdctl", rxdctl._data);
 668         paramIn(cp, section, "radv", radv._data);
 669         paramIn(cp, section, "rsrpd", rsrpd._data);
 670         paramIn(cp, section, "tdba", tdba._data);
 671         paramIn(cp, section, "tdlen", tdlen._data);
 672         paramIn(cp, section, "tdh", tdh._data);
 673         paramIn(cp, section, "tdt", tdt._data);
 674         paramIn(cp, section, "tidv", tidv._data);
 675         paramIn(cp, section, "txdctl", txdctl._data);
 676         paramIn(cp, section, "tadv", tadv._data);
 677         paramIn(cp, section, "rxcsum", rxcsum._data);
 678         paramIn(cp, section, "manc", manc._data);
 679     }
 680 };
 681 } // iGbReg namespace