src/dev/ide_atareg.h

   1 /*      $OpenBSD: atareg.h,v 1.12 2004/09/24 07:15:22 grange Exp $      */
   2 /*      $NetBSD: atareg.h,v 1.5 1999/01/18 20:06:24 bouyer Exp $        */
   3
   4 /*
   5  * Copyright (c) 1998, 2001 Manuel Bouyer.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Manuel Bouyer.
  18  * 4. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #ifndef _DEV_ATA_ATAREG_H_
  34 #define _DEV_ATA_ATAREG_H_
  35
  36 #if defined(linux)
  37 #include <endian.h>
  38 #elif defined(__sun)
  39 #include <sys/isa_defs.h>
  40 #else
  41 #include <machine/endian.h>
  42 #endif
  43
  44 #ifdef LITTLE_ENDIAN
  45 #define ATA_BYTE_ORDER LITTLE_ENDIAN
  46 #elif defined(BIG_ENDIAN)
  47 #define ATA_BYTE_ORDER BIG_ENDIAN
  48 #elif defined(_LITTLE_ENDIAN)
  49 #define ATA_BYTE_ORDER 1
  50 #define LITTLE_ENDIAN 1
  51 #elif defined(_BIG_ENDIAN)
  52 #define ATA_BYTE_ORDER 0
  53 #define LITTLE_ENDIAN 1
  54 #else
  55 #error "No endianess defined"
  56 #endif
  57
  58 /*
  59  * Drive parameter structure for ATA/ATAPI.
  60  * Bit fields: WDC_* : common to ATA/ATAPI
  61  *             ATA_* : ATA only
  62  *             ATAPI_* : ATAPI only.
  63  */
  64 struct ataparams {
  65     /* drive info */
  66     uint16_t    atap_config;            /* 0: general configuration */
  67 #define WDC_CFG_ATAPI_MASK              0xc000
  68 #define WDC_CFG_ATAPI                   0x8000
  69 #define ATA_CFG_REMOVABLE               0x0080
  70 #define ATA_CFG_FIXED                   0x0040
  71 #define ATAPI_CFG_TYPE_MASK             0x1f00
  72 #define ATAPI_CFG_TYPE(x)               (((x) & ATAPI_CFG_TYPE_MASK) >> 8)
  73 #define ATAPI_CFG_TYPE_DIRECT           0x00
  74 #define ATAPI_CFG_TYPE_SEQUENTIAL       0x01
  75 #define ATAPI_CFG_TYPE_CDROM            0x05
  76 #define ATAPI_CFG_TYPE_OPTICAL          0x07
  77 #define ATAPI_CFG_TYPE_NODEVICE         0x1F
  78 #define ATAPI_CFG_REMOV                 0x0080
  79 #define ATAPI_CFG_DRQ_MASK              0x0060
  80 #define ATAPI_CFG_STD_DRQ               0x0000
  81 #define ATAPI_CFG_IRQ_DRQ               0x0020
  82 #define ATAPI_CFG_ACCEL_DRQ             0x0040
  83 #define ATAPI_CFG_CMD_MASK              0x0003
  84 #define ATAPI_CFG_CMD_12                0x0000
  85 #define ATAPI_CFG_CMD_16                0x0001
  86 /* words 1-9 are ATA only */
  87     uint16_t    atap_cylinders;         /* 1: # of non-removable cylinders */
  88     uint16_t    __reserved1;
  89     uint16_t    atap_heads;             /* 3: # of heads */
  90     uint16_t    __retired1[2];          /* 4-5: # of unform. bytes/track */
  91     uint16_t    atap_sectors;           /* 6: # of sectors */
  92     uint16_t    __retired2[3];
  93
  94     uint8_t     atap_serial[20];        /* 10-19: serial number */
  95     uint16_t    __retired3[2];
  96     uint16_t    __obsolete1;
  97     uint8_t     atap_revision[8];       /* 23-26: firmware revision */
  98     uint8_t     atap_model[40];         /* 27-46: model number */
  99     uint16_t    atap_multi;             /* 47: maximum sectors per irq (ATA) */
 100     uint16_t    __reserved2;
 101     uint8_t     atap_vendor;            /* 49: vendor  */
 102     uint8_t     atap_capabilities1;     /* 49: capability flags */
 103 #define WDC_CAP_IORDY   0x0800
 104 #define WDC_CAP_IORDY_DSBL 0x0400
 105 #define WDC_CAP_LBA     0x0200
 106 #define WDC_CAP_DMA     0x0100
 107 #define ATA_CAP_STBY    0x2000
 108 #define ATAPI_CAP_INTERL_DMA    0x8000
 109 #define ATAPI_CAP_CMD_QUEUE     0x4000
 110 #define ATAPI_CAP_OVERLP        0x2000
 111 #define ATAPI_CAP_ATA_RST       0x1000
 112     uint16_t    atap_capabilities2;     /* 50: capability flags (ATA) */
 113 #if ATA_BYTE_ORDER == LITTLE_ENDIAN
 114     uint8_t     __junk2;
 115     uint8_t     atap_oldpiotiming;      /* 51: old PIO timing mode */
 116     uint8_t     __junk3;
 117     uint8_t     atap_olddmatiming;      /* 52: old DMA timing mode (ATA) */
 118 #else
 119     uint8_t     atap_oldpiotiming;      /* 51: old PIO timing mode */
 120     uint8_t     __junk2;
 121     uint8_t     atap_olddmatiming;      /* 52: old DMA timing mode (ATA) */
 122     uint8_t     __junk3;
 123 #endif
 124     uint16_t    atap_extensions;        /* 53: extensions supported */
 125 #define WDC_EXT_UDMA_MODES      0x0004
 126 #define WDC_EXT_MODES           0x0002
 127 #define WDC_EXT_GEOM            0x0001
 128 /* words 54-62 are ATA only */
 129     uint16_t    atap_curcylinders;      /* 54: current logical cylinders */
 130     uint16_t    atap_curheads;          /* 55: current logical heads */
 131     uint16_t    atap_cursectors;        /* 56: current logical sectors/tracks */
 132     uint16_t    atap_curcapacity[2];    /* 57-58: current capacity */
 133     uint8_t     atap_curmulti;          /* 59: current multi-sector setting */
 134     uint8_t     atap_curmulti_valid;    /* 59: current multi-sector setting */
 135 #define WDC_MULTI_VALID 0x0100
 136 #define WDC_MULTI_MASK  0x00ff
 137     uint32_t    atap_capacity;  /* 60-61: total capacity (LBA only) */
 138     uint16_t    __retired4;
 139 #if ATA_BYTE_ORDER == LITTLE_ENDIAN
 140     uint8_t     atap_dmamode_supp;      /* 63: multiword DMA mode supported */
 141     uint8_t     atap_dmamode_act;       /*     multiword DMA mode active */
 142     uint8_t     atap_piomode_supp;      /* 64: PIO mode supported */
 143     uint8_t     __junk4;
 144 #else
 145     uint8_t     atap_dmamode_act;       /*     multiword DMA mode active */
 146     uint8_t     atap_dmamode_supp;      /* 63: multiword DMA mode supported */
 147     uint8_t     __junk4;
 148     uint8_t     atap_piomode_supp;      /* 64: PIO mode supported */
 149 #endif
 150     uint16_t    atap_dmatiming_mimi;    /* 65: minimum DMA cycle time */
 151     uint16_t    atap_dmatiming_recom;   /* 66: recommended DMA cycle time */
 152     uint16_t    atap_piotiming;         /* 67: mini PIO cycle time without FC */
 153     uint16_t    atap_piotiming_iordy;   /* 68: mini PIO cycle time with IORDY FC */
 154     uint16_t    __reserved3[2];
 155 /* words 71-72 are ATAPI only */
 156     uint16_t    atap_pkt_br;            /* 71: time (ns) to bus release */
 157     uint16_t    atap_pkt_bsyclr;        /* 72: tme to clear BSY after service */
 158     uint16_t    __reserved4[2];
 159     uint16_t    atap_queuedepth;        /* 75: */
 160 #define WDC_QUEUE_DEPTH_MASK 0x1f
 161     uint16_t    atap_sata_caps;         /* 76: SATA capabilities */
 162 #define SATA_SIGNAL_GEN1        0x0002  /* SATA Gen-1 signaling speed */
 163 #define SATA_SIGNAL_GEN2        0x0004  /* SATA Gen-2 signaling speed */
 164 #define SATA_NATIVE_CMDQ        0x0100  /* native command queuing */
 165 #define SATA_HOST_PWR_MGMT      0x0200  /* power management (host) */
 166     uint16_t    atap_sata_reserved;     /* 77: reserved */
 167     uint16_t    atap_sata_features_supp;/* 78: SATA features supported */
 168 #define SATA_NONZERO_OFFSETS    0x0002  /* non-zero buffer offsets */
 169 #define SATA_DMA_SETUP_AUTO     0x0004  /* DMA setup auto-activate */
 170 #define SATA_DRIVE_PWR_MGMT     0x0008  /* power management (device) */
 171     uint16_t    atap_sata_features_en;  /* 79: SATA features enabled */
 172     uint16_t    atap_ata_major;         /* 80: Major version number */
 173 #define WDC_VER_ATA1    0x0002
 174 #define WDC_VER_ATA2    0x0004
 175 #define WDC_VER_ATA3    0x0008
 176 #define WDC_VER_ATA4    0x0010
 177 #define WDC_VER_ATA5    0x0020
 178 #define WDC_VER_ATA6    0x0040
 179 #define WDC_VER_ATA7    0x0080
 180 #define WDC_VER_ATA8    0x0100
 181 #define WDC_VER_ATA9    0x0200
 182 #define WDC_VER_ATA10   0x0400
 183 #define WDC_VER_ATA11   0x0800
 184 #define WDC_VER_ATA12   0x1000
 185 #define WDC_VER_ATA13   0x2000
 186 #define WDC_VER_ATA14   0x4000
 187     uint16_t    atap_ata_minor;         /* 81: Minor version number */
 188     uint16_t    atap_cmd_set1;          /* 82: command set supported */
 189 #define WDC_CMD1_NOP    0x4000
 190 #define WDC_CMD1_RB     0x2000
 191 #define WDC_CMD1_WB     0x1000
 192 #define WDC_CMD1_HPA    0x0400
 193 #define WDC_CMD1_DVRST  0x0200
 194 #define WDC_CMD1_SRV    0x0100
 195 #define WDC_CMD1_RLSE   0x0080
 196 #define WDC_CMD1_AHEAD  0x0040
 197 #define WDC_CMD1_CACHE  0x0020
 198 #define WDC_CMD1_PKT    0x0010
 199 #define WDC_CMD1_PM     0x0008
 200 #define WDC_CMD1_REMOV  0x0004
 201 #define WDC_CMD1_SEC    0x0002
 202 #define WDC_CMD1_SMART  0x0001
 203     uint16_t    atap_cmd_set2;          /* 83: command set supported */
 204 #define ATAPI_CMD2_FCE  0x2000 /* Flush Cache Ext supported */
 205 #define ATAPI_CMD2_FC   0x1000 /* Flush Cache supported */
 206 #define ATAPI_CMD2_DCO  0x0800 /* Device Configuration Overlay supported */
 207 #define ATAPI_CMD2_48AD 0x0400 /* 48bit address supported */
 208 #define ATAPI_CMD2_AAM  0x0200 /* Automatic Acoustic Management supported */
 209 #define ATAPI_CMD2_SM   0x0100 /* Set Max security extension supported */
 210 #define ATAPI_CMD2_SF   0x0040 /* Set Features subcommand required */
 211 #define ATAPI_CMD2_PUIS 0x0020 /* Power up in standby supported */
 212 #define WDC_CMD2_RMSN   0x0010
 213 #define ATA_CMD2_APM    0x0008
 214 #define ATA_CMD2_CFA    0x0004
 215 #define ATA_CMD2_RWQ    0x0002
 216 #define WDC_CMD2_DM     0x0001 /* Download Microcode supported */
 217     uint16_t    atap_cmd_ext;           /* 84: command/features supp. ext. */
 218 #define ATAPI_CMDE_MSER 0x0004 /* Media serial number supported */
 219 #define ATAPI_CMDE_TEST 0x0002 /* SMART self-test supported */
 220 #define ATAPI_CMDE_SLOG 0x0001 /* SMART error logging supported */
 221     uint16_t    atap_cmd1_en;           /* 85: cmd/features enabled */
 222 /* bits are the same as atap_cmd_set1 */
 223     uint16_t    atap_cmd2_en;           /* 86: cmd/features enabled */
 224 /* bits are the same as atap_cmd_set2 */
 225     uint16_t    atap_cmd_def;           /* 87: cmd/features default */
 226 /* bits are NOT the same as atap_cmd_ext */
 227 #if ATA_BYTE_ORDER == LITTLE_ENDIAN
 228     uint8_t     atap_udmamode_supp;     /* 88: Ultra-DMA mode supported */
 229     uint8_t     atap_udmamode_act;      /*     Ultra-DMA mode active */
 230 #else
 231     uint8_t     atap_udmamode_act;      /*     Ultra-DMA mode active */
 232     uint8_t     atap_udmamode_supp;     /* 88: Ultra-DMA mode supported */
 233 #endif
 234 /* 89-92 are ATA-only */
 235     uint16_t    atap_seu_time;          /* 89: Sec. Erase Unit compl. time */
 236     uint16_t    atap_eseu_time;         /* 90: Enhanced SEU compl. time */
 237     uint16_t    atap_apm_val;           /* 91: current APM value */
 238     uint16_t    atap_mpasswd_rev;       /* 92: Master Password revision */
 239     uint16_t    atap_hwreset_res;       /* 93: Hardware reset value */
 240 #define ATA_HWRES_CBLID    0x2000  /* CBLID above Vih */
 241 #define ATA_HWRES_D1_PDIAG 0x0800  /* Device 1 PDIAG detect OK */
 242 #define ATA_HWRES_D1_CSEL  0x0400  /* Device 1 used CSEL for address */
 243 #define ATA_HWRES_D1_JUMP  0x0200  /* Device 1 jumpered to address */
 244 #define ATA_HWRES_D0_SEL   0x0040  /* Device 0 responds when Dev 1 selected */
 245 #define ATA_HWRES_D0_DASP  0x0020  /* Device 0 DASP detect OK */
 246 #define ATA_HWRES_D0_PDIAG 0x0010  /* Device 0 PDIAG detect OK */
 247 #define ATA_HWRES_D0_DIAG  0x0008  /* Device 0 diag OK */
 248 #define ATA_HWRES_D0_CSEL  0x0004  /* Device 0 used CSEL for address */
 249 #define ATA_HWRES_D0_JUMP  0x0002  /* Device 0 jumpered to address */
 250 #if ATA_BYTE_ORDER == LITTLE_ENDIAN
 251     uint8_t     atap_acoustic_val;      /* 94: Current acoustic level */
 252     uint8_t     atap_acoustic_def;      /*     recommended level */
 253 #else
 254     uint8_t     atap_acoustic_def;      /*     recommended level */
 255     uint8_t     atap_acoustic_val;      /* 94: Current acoustic level */
 256 #endif
 257     uint16_t    __reserved6[5];         /* 95-99: reserved */
 258     uint16_t    atap_max_lba[4];        /* 100-103: Max. user LBA add */
 259     uint16_t    __reserved7[23];        /* 104-126: reserved */
 260     uint16_t    atap_rmsn_supp;         /* 127: remov. media status notif. */
 261 #define WDC_RMSN_SUPP_MASK 0x0003
 262 #define WDC_RMSN_SUPP 0x0001
 263     uint16_t    atap_sec_st;            /* 128: security status */
 264 #define WDC_SEC_LEV_MAX 0x0100
 265 #define WDC_SEC_ESE_SUPP 0x0020
 266 #define WDC_SEC_EXP     0x0010
 267 #define WDC_SEC_FROZEN  0x0008
 268 #define WDC_SEC_LOCKED  0x0004
 269 #define WDC_SEC_EN      0x0002
 270 #define WDC_SEC_SUPP    0x0001
 271     uint16_t    __reserved8[31];        /* 129-159: vendor specific */
 272     uint16_t    atap_cfa_power;         /* 160: CFA powermode */
 273 #define ATAPI_CFA_MAX_MASK  0x0FFF
 274 #define ATAPI_CFA_MODE1_DIS 0x1000 /* CFA Mode 1 Disabled */
 275 #define ATAPI_CFA_MODE1_REQ 0x2000 /* CFA Mode 1 Required */
 276 #define ATAPI_CFA_WORD160   0x8000 /* Word 160 supported */
 277     uint16_t    __reserved9[15];        /* 161-175: reserved for CFA */
 278     uint8_t     atap_media_serial[60];  /* 176-205: media serial number */
 279     uint16_t    __reserved10[49];       /* 206-254: reserved */
 280 #if ATA_BYTE_ORDER == LITTLE_ENDIAN
 281     uint8_t     atap_signature;         /* 255: Signature */
 282     uint8_t     atap_checksum;          /*      Checksum */
 283 #else
 284     uint8_t     atap_checksum;          /*      Checksum */
 285     uint8_t     atap_signature;         /* 255: Signature */
 286 #endif
 287 };
 288
 289 #undef ATA_BYTE_ORDER
 290 #endif  /* !_DEV_ATA_ATAREG_H_ */