src/dev/ide_ctrl.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Andrew Schultz
  29  *          Miguel Serrano
  30  */
  31
  32 /** @file
  33  * Simple PCI IDE controller with bus mastering capability and UDMA
  34  * modeled after controller in the Intel PIIX4 chip
  35  */
  36
  37 #ifndef __IDE_CTRL_HH__
  38 #define __IDE_CTRL_HH__
  39
  40 #include "base/bitunion.hh"
  41 #include "dev/pcidev.hh"
  42 #include "dev/pcireg.h"
  43 #include "dev/io_device.hh"
  44 #include "params/IdeController.hh"
  45
  46 class IdeDisk;
  47
  48 /**
  49  * Device model for an Intel PIIX4 IDE controller
  50  */
  51
  52 class IdeController : public PciDev
  53 {
  54   private:
  55     // Bus master IDE status register bit fields
  56     BitUnion8(BMIStatusReg)
  57         Bitfield<6> dmaCap0;
  58         Bitfield<5> dmaCap1;
  59         Bitfield<2> intStatus;
  60         Bitfield<1> dmaError;
  61         Bitfield<0> active;
  62     EndBitUnion(BMIStatusReg)
  63
  64     BitUnion8(BMICommandReg)
  65         Bitfield<3> rw;
  66         Bitfield<0> startStop;
  67     EndBitUnion(BMICommandReg)
  68
  69     struct Channel
  70     {
  71         std::string _name;
  72
  73         const std::string
  74         name()
  75         {
  76             return _name;
  77         }
  78
  79         /** Command and control block registers */
  80         Addr cmdAddr, cmdSize, ctrlAddr, ctrlSize;
  81
  82         /** Registers used for bus master interface */
  83         struct BMIRegs
  84         {
  85             BMICommandReg command;
  86             uint8_t reserved0;
  87             BMIStatusReg status;
  88             uint8_t reserved1;
  89             uint32_t bmidtp;
  90         } bmiRegs;
  91
  92         /** IDE disks connected to this controller */
  93         IdeDisk *master, *slave;
  94
  95         /** Currently selected disk */
  96         IdeDisk *selected;
  97
  98         bool selectBit;
  99
 100         void
 101         select(bool selSlave)
 102         {
 103             selectBit = selSlave;
 104             selected = selectBit ? slave : master;
 105         }
 106
 107         void accessCommand(Addr offset, int size, uint8_t *data, bool read);
 108         void accessControl(Addr offset, int size, uint8_t *data, bool read);
 109         void accessBMI(Addr offset, int size, uint8_t *data, bool read);
 110
 111         Channel(std::string newName, Addr _cmdSize, Addr _ctrlSize);
 112         ~Channel();
 113
 114         void serialize(const std::string &base, std::ostream &os);
 115         void unserialize(const std::string &base, Checkpoint *cp,
 116             const std::string &section);
 117     };
 118
 119     Channel primary;
 120     Channel secondary;
 121
 122     /** Bus master interface (BMI) registers */
 123     Addr bmiAddr, bmiSize;
 124
 125     /** Registers used in device specific PCI configuration */
 126     uint16_t primaryTiming, secondaryTiming;
 127     uint8_t deviceTiming;
 128     uint8_t udmaControl;
 129     uint16_t udmaTiming;
 130     uint16_t ideConfig;
 131
 132     // Internal management variables
 133     bool ioEnabled;
 134     bool bmEnabled;
 135
 136     uint32_t ioShift, ctrlOffset;
 137
 138     void dispatchAccess(PacketPtr pkt, bool read);
 139
 140   public:
 141     typedef IdeControllerParams Params;
 142     const Params *params() const { return (const Params *)_params; }
 143     IdeController(Params *p);
 144
 145     /** See if a disk is selected based on its pointer */
 146     bool isDiskSelected(IdeDisk *diskPtr);
 147
 148     void intrPost();
 149
 150     Tick writeConfig(PacketPtr pkt);
 151     Tick readConfig(PacketPtr pkt);
 152
 153     void setDmaComplete(IdeDisk *disk);
 154
 155     Tick read(PacketPtr pkt);
 156     Tick write(PacketPtr pkt);
 157
 158     void serialize(std::ostream &os);
 159     void unserialize(Checkpoint *cp, const std::string &section);
 160 };
 161 #endif // __IDE_CTRL_HH_