2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Andrew Schultz
33 * Simple PCI IDE controller with bus mastering capability and UDMA
34 * modeled after controller in the Intel PIIX4 chip
37 #ifndef __IDE_CTRL_HH__
38 #define __IDE_CTRL_HH__
40 #include "dev/pcidev.hh"
41 #include "dev/pcireg.h"
42 #include "dev/io_device.hh"
44 #define BMIC0 0x0 // Bus master IDE command register
45 #define BMIS0 0x2 // Bus master IDE status register
46 #define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register
47 #define BMIC1 0x8 // Bus master IDE command register
48 #define BMIS1 0xa // Bus master IDE status register
49 #define BMIDTP1 0xc // Bus master IDE descriptor table pointer register
51 // Bus master IDE command register bit fields
52 #define RWCON 0x08 // Bus master read/write control
53 #define SSBM 0x01 // Start/stop bus master
55 // Bus master IDE status register bit fields
56 #define DMA1CAP 0x40 // Drive 1 DMA capable
57 #define DMA0CAP 0x20 // Drive 0 DMA capable
58 #define IDEINTS 0x04 // IDE Interrupt Status
59 #define IDEDMAE 0x02 // IDE DMA error
60 #define BMIDEA 0x01 // Bus master IDE active
62 // IDE Command byte fields
63 #define IDE_SELECT_OFFSET (6)
64 #define IDE_SELECT_DEV_BIT 0x10
66 #define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
67 #define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
69 // IDE Timing Register bit fields
70 #define IDETIM_DECODE_EN 0x8000
72 // PCI device specific register byte offsets
73 #define IDE_CTRL_CONF_START 0x40
74 #define IDE_CTRL_CONF_END ((IDE_CTRL_CONF_START) + sizeof(config_regs))
76 #define IDE_CTRL_CONF_PRIM_TIMING 0x40
77 #define IDE_CTRL_CONF_SEC_TIMING 0x42
78 #define IDE_CTRL_CONF_DEV_TIMING 0x44
79 #define IDE_CTRL_CONF_UDMA_CNTRL 0x48
80 #define IDE_CTRL_CONF_UDMA_TIMING 0x4A
81 #define IDE_CTRL_CONF_IDE_CONFIG 0x54
96 * Device model for an Intel PIIX4 IDE controller
99 class IdeController : public PciDev
101 friend class IdeDisk;
109 /** Primary command block registers */
112 /** Primary control block registers */
115 /** Secondary command block registers */
118 /** Secondary control block registers */
121 /** Bus master interface (BMI) registers */
126 /** Registers used for bus master interface */
152 /** Shadows of the device select bit */
154 /** Registers used in device specific PCI configuration */
162 uint8_t reserved_0[3];
166 uint8_t reserved_2[8];
171 // Internal management variables
174 bool cmd_in_progress[4];
177 /** IDE disks connected to controller */
181 /** Parse the access address to pass on to device */
182 void parseAddr(const Addr &addr, Addr &offset, IdeChannel &channel,
183 IdeRegType ®_type);
185 /** Select the disk based on the channel and device bit */
186 int getDisk(IdeChannel channel);
188 /** Select the disk based on a pointer */
189 int getDisk(IdeDisk *diskPtr);
192 /** See if a disk is selected based on its pointer */
193 bool isDiskSelected(IdeDisk *diskPtr);
196 struct Params : public PciDev::Params
198 /** Array of disk objects */
199 std::vector<IdeDisk *> disks;
201 const Params *params() const { return (const Params *)_params; }
204 IdeController(Params *p);
207 virtual Tick writeConfig(Packet *pkt);
208 virtual Tick readConfig(Packet *pkt);
210 void setDmaComplete(IdeDisk *disk);
213 * Read a done field for a given target.
214 * @param pkt Packet describing what is to be read
215 * @return The amount of time to complete this request
217 virtual Tick read(Packet *pkt);
220 * Write a done field for a given target.
221 * @param pkt Packet describing what is to be written
222 * @return The amount of time to complete this request
224 virtual Tick write(Packet *pkt);
227 * Serialize this object to the given output stream.
228 * @param os The stream to serialize to.
230 virtual void serialize(std::ostream &os);
233 * Reconstruct the state of this object from a checkpoint.
234 * @param cp The checkpoint use.
235 * @param section The section name of this object
237 virtual void unserialize(Checkpoint *cp, const std::string §ion);
240 #endif // __IDE_CTRL_HH_