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28 * Authors: Andrew Schultz
33 * Simple PCI IDE controller with bus mastering capability and UDMA
34 * modeled after controller in the Intel PIIX4 chip
37 #ifndef __IDE_CTRL_HH__
38 #define __IDE_CTRL_HH__
40 #include "base/bitunion.hh"
41 #include "dev/pcidev.hh"
42 #include "dev/pcireg.h"
43 #include "dev/io_device.hh"
44 #include "params/IdeController.hh"
49 * Device model for an Intel PIIX4 IDE controller
52 class IdeController : public PciDev
55 // Bus master IDE status register bit fields
56 BitUnion8(BMIStatusReg)
59 Bitfield<2> intStatus;
62 EndBitUnion(BMIStatusReg)
64 BitUnion8(BMICommandReg)
66 Bitfield<0> startStop;
67 EndBitUnion(BMICommandReg)
79 /** Command and control block registers */
80 Addr cmdAddr, cmdSize, ctrlAddr, ctrlSize;
82 /** Registers used for bus master interface */
85 BMICommandReg command;
92 /** IDE disks connected to this controller */
93 IdeDisk *master, *slave;
95 /** Currently selected disk */
101 select(bool selSlave)
103 selectBit = selSlave;
104 selected = selectBit ? slave : master;
107 void accessCommand(Addr offset, int size, uint8_t *data, bool read);
108 void accessControl(Addr offset, int size, uint8_t *data, bool read);
109 void accessBMI(Addr offset, int size, uint8_t *data, bool read);
111 Channel(std::string newName, Addr _cmdSize, Addr _ctrlSize);
114 void serialize(const std::string &base, std::ostream &os);
115 void unserialize(const std::string &base, Checkpoint *cp,
116 const std::string §ion);
122 /** Bus master interface (BMI) registers */
123 Addr bmiAddr, bmiSize;
125 /** Registers used in device specific PCI configuration */
126 uint16_t primaryTiming, secondaryTiming;
127 uint8_t deviceTiming;
132 // Internal management variables
136 void dispatchAccess(PacketPtr pkt, bool read);
139 typedef IdeControllerParams Params;
140 const Params *params() const { return (const Params *)_params; }
141 IdeController(Params *p);
143 /** See if a disk is selected based on its pointer */
144 bool isDiskSelected(IdeDisk *diskPtr);
148 Tick writeConfig(PacketPtr pkt);
149 Tick readConfig(PacketPtr pkt);
151 void setDmaComplete(IdeDisk *disk);
153 Tick read(PacketPtr pkt);
154 Tick write(PacketPtr pkt);
156 void serialize(std::ostream &os);
157 void unserialize(Checkpoint *cp, const std::string §ion);
159 #endif // __IDE_CTRL_HH_