src/dev/ide_ctrl.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Simple PCI IDE controller with bus mastering capability and UDMA
  31  * modeled after controller in the Intel PIIX4 chip
  32  */
  33
  34 #ifndef __IDE_CTRL_HH__
  35 #define __IDE_CTRL_HH__
  36
  37 #include "dev/pcidev.hh"
  38 #include "dev/pcireg.h"
  39 #include "dev/io_device.hh"
  40
  41 #define BMIC0    0x0  // Bus master IDE command register
  42 #define BMIS0    0x2  // Bus master IDE status register
  43 #define BMIDTP0  0x4  // Bus master IDE descriptor table pointer register
  44 #define BMIC1    0x8  // Bus master IDE command register
  45 #define BMIS1    0xa  // Bus master IDE status register
  46 #define BMIDTP1  0xc  // Bus master IDE descriptor table pointer register
  47
  48 // Bus master IDE command register bit fields
  49 #define RWCON 0x08 // Bus master read/write control
  50 #define SSBM  0x01 // Start/stop bus master
  51
  52 // Bus master IDE status register bit fields
  53 #define DMA1CAP 0x40 // Drive 1 DMA capable
  54 #define DMA0CAP 0x20 // Drive 0 DMA capable
  55 #define IDEINTS 0x04 // IDE Interrupt Status
  56 #define IDEDMAE 0x02 // IDE DMA error
  57 #define BMIDEA  0x01 // Bus master IDE active
  58
  59 // IDE Command byte fields
  60 #define IDE_SELECT_OFFSET       (6)
  61 #define IDE_SELECT_DEV_BIT      0x10
  62
  63 #define IDE_FEATURE_OFFSET      IDE_ERROR_OFFSET
  64 #define IDE_COMMAND_OFFSET      IDE_STATUS_OFFSET
  65
  66 // IDE Timing Register bit fields
  67 #define IDETIM_DECODE_EN 0x8000
  68
  69 // PCI device specific register byte offsets
  70 #define IDE_CTRL_CONF_START 0x40
  71 #define IDE_CTRL_CONF_END ((IDE_CTRL_CONF_START) + sizeof(config_regs))
  72
  73 #define IDE_CTRL_CONF_PRIM_TIMING   0x40
  74 #define IDE_CTRL_CONF_SEC_TIMING    0x42
  75 #define IDE_CTRL_CONF_DEV_TIMING    0x44
  76 #define IDE_CTRL_CONF_UDMA_CNTRL    0x48
  77 #define IDE_CTRL_CONF_UDMA_TIMING   0x4A
  78 #define IDE_CTRL_CONF_IDE_CONFIG    0x54
  79
  80
  81 enum IdeRegType {
  82     COMMAND_BLOCK,
  83     CONTROL_BLOCK,
  84     BMI_BLOCK
  85 };
  86
  87 class IdeDisk;
  88 class IntrControl;
  89 class PciConfigAll;
  90 class Platform;
  91
  92 /**
  93  * Device model for an Intel PIIX4 IDE controller
  94  */
  95
  96 class IdeController : public PciDev
  97 {
  98     friend class IdeDisk;
  99
 100     enum IdeChannel {
 101         PRIMARY = 0,
 102         SECONDARY = 1
 103     };
 104
 105   private:
 106     /** Primary command block registers */
 107     Addr pri_cmd_addr;
 108     Addr pri_cmd_size;
 109     /** Primary control block registers */
 110     Addr pri_ctrl_addr;
 111     Addr pri_ctrl_size;
 112     /** Secondary command block registers */
 113     Addr sec_cmd_addr;
 114     Addr sec_cmd_size;
 115     /** Secondary control block registers */
 116     Addr sec_ctrl_addr;
 117     Addr sec_ctrl_size;
 118     /** Bus master interface (BMI) registers */
 119     Addr bmi_addr;
 120     Addr bmi_size;
 121
 122   private:
 123     /** Registers used for bus master interface */
 124     union {
 125         uint8_t data[16];
 126
 127         struct {
 128             uint8_t bmic0;
 129             uint8_t reserved_0;
 130             uint8_t bmis0;
 131             uint8_t reserved_1;
 132             uint32_t bmidtp0;
 133             uint8_t bmic1;
 134             uint8_t reserved_2;
 135             uint8_t bmis1;
 136             uint8_t reserved_3;
 137             uint32_t bmidtp1;
 138         };
 139
 140         struct {
 141             uint8_t bmic;
 142             uint8_t reserved_4;
 143             uint8_t bmis;
 144             uint8_t reserved_5;
 145             uint32_t bmidtp;
 146         } chan[2];
 147
 148     } bmi_regs;
 149     /** Shadows of the device select bit */
 150     uint8_t dev[2];
 151     /** Registers used in device specific PCI configuration */
 152     union {
 153         uint8_t data[22];
 154
 155         struct {
 156             uint16_t idetim0;
 157             uint16_t idetim1;
 158             uint8_t sidetim;
 159             uint8_t reserved_0[3];
 160             uint8_t udmactl;
 161             uint8_t reserved_1;
 162             uint16_t udmatim;
 163             uint8_t reserved_2[8];
 164             uint16_t ideconfig;
 165         };
 166     } config_regs;
 167
 168     // Internal management variables
 169     bool io_enabled;
 170     bool bm_enabled;
 171     bool cmd_in_progress[4];
 172
 173   private:
 174     /** IDE disks connected to controller */
 175     IdeDisk *disks[4];
 176
 177   private:
 178     /** Parse the access address to pass on to device */
 179     void parseAddr(const Addr &addr, Addr &offset, IdeChannel &channel,
 180                    IdeRegType &reg_type);
 181
 182     /** Select the disk based on the channel and device bit */
 183     int getDisk(IdeChannel channel);
 184
 185     /** Select the disk based on a pointer */
 186     int getDisk(IdeDisk *diskPtr);
 187
 188   public:
 189     /** See if a disk is selected based on its pointer */
 190     bool isDiskSelected(IdeDisk *diskPtr);
 191
 192   public:
 193     struct Params : public PciDev::Params
 194     {
 195         /** Array of disk objects */
 196         std::vector<IdeDisk *> disks;
 197     };
 198     const Params *params() const { return (const Params *)_params; }
 199
 200   public:
 201     IdeController(Params *p);
 202     ~IdeController();
 203
 204     virtual void writeConfig(int offset, const uint8_t data);
 205     virtual void writeConfig(int offset, const uint16_t data);
 206     virtual void writeConfig(int offset, const uint32_t data);
 207     virtual void readConfig(int offset, uint8_t *data);
 208     virtual void readConfig(int offset, uint16_t *data);
 209     virtual void readConfig(int offset, uint32_t *data);
 210
 211     void setDmaComplete(IdeDisk *disk);
 212
 213     /**
 214      * Read a done field for a given target.
 215      * @param pkt Packet describing what is to be read
 216      * @return The amount of time to complete this request
 217      */
 218     virtual Tick read(Packet *pkt);
 219
 220     /**
 221      * Write a done field for a given target.
 222      * @param pkt Packet describing what is to be written
 223      * @return The amount of time to complete this request
 224      */
 225     virtual Tick write(Packet *pkt);
 226
 227     /**
 228      * Serialize this object to the given output stream.
 229      * @param os The stream to serialize to.
 230      */
 231     virtual void serialize(std::ostream &os);
 232
 233     /**
 234      * Reconstruct the state of this object from a checkpoint.
 235      * @param cp The checkpoint use.
 236      * @param section The section name of this object
 237      */
 238     virtual void unserialize(Checkpoint *cp, const std::string &section);
 239
 240 };
 241 #endif // __IDE_CTRL_HH_