src/dev/ide_ctrl.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Andrew Schultz
  29  *          Miguel Serrano
  30  */
  31
  32 /** @file
  33  * Simple PCI IDE controller with bus mastering capability and UDMA
  34  * modeled after controller in the Intel PIIX4 chip
  35  */
  36
  37 #ifndef __IDE_CTRL_HH__
  38 #define __IDE_CTRL_HH__
  39
  40 #include "dev/pcidev.hh"
  41 #include "dev/pcireg.h"
  42 #include "dev/io_device.hh"
  43 #include "params/IdeController.hh"
  44
  45 #define BMIC0    0x0  // Bus master IDE command register
  46 #define BMIS0    0x2  // Bus master IDE status register
  47 #define BMIDTP0  0x4  // Bus master IDE descriptor table pointer register
  48 #define BMIC1    0x8  // Bus master IDE command register
  49 #define BMIS1    0xa  // Bus master IDE status register
  50 #define BMIDTP1  0xc  // Bus master IDE descriptor table pointer register
  51
  52 // Bus master IDE command register bit fields
  53 #define RWCON 0x08 // Bus master read/write control
  54 #define SSBM  0x01 // Start/stop bus master
  55
  56 // Bus master IDE status register bit fields
  57 #define DMA1CAP 0x40 // Drive 1 DMA capable
  58 #define DMA0CAP 0x20 // Drive 0 DMA capable
  59 #define IDEINTS 0x04 // IDE Interrupt Status
  60 #define IDEDMAE 0x02 // IDE DMA error
  61 #define BMIDEA  0x01 // Bus master IDE active
  62
  63 // IDE Command byte fields
  64 #define IDE_SELECT_OFFSET       (6)
  65 #define IDE_SELECT_DEV_BIT      0x10
  66
  67 #define IDE_FEATURE_OFFSET      IDE_ERROR_OFFSET
  68 #define IDE_COMMAND_OFFSET      IDE_STATUS_OFFSET
  69
  70 // IDE Timing Register bit fields
  71 #define IDETIM_DECODE_EN 0x8000
  72
  73 // PCI device specific register byte offsets
  74 #define IDE_CTRL_CONF_START 0x40
  75 #define IDE_CTRL_CONF_END ((IDE_CTRL_CONF_START) + sizeof(config_regs))
  76
  77 #define IDE_CTRL_CONF_PRIM_TIMING   0x40
  78 #define IDE_CTRL_CONF_SEC_TIMING    0x42
  79 #define IDE_CTRL_CONF_DEV_TIMING    0x44
  80 #define IDE_CTRL_CONF_UDMA_CNTRL    0x48
  81 #define IDE_CTRL_CONF_UDMA_TIMING   0x4A
  82 #define IDE_CTRL_CONF_IDE_CONFIG    0x54
  83
  84
  85 enum IdeRegType {
  86     COMMAND_BLOCK,
  87     CONTROL_BLOCK,
  88     BMI_BLOCK
  89 };
  90
  91 class IdeDisk;
  92 class IntrControl;
  93 class PciConfigAll;
  94 class Platform;
  95
  96 /**
  97  * Device model for an Intel PIIX4 IDE controller
  98  */
  99
 100 class IdeController : public PciDev
 101 {
 102     friend class IdeDisk;
 103
 104     enum IdeChannel {
 105         PRIMARY = 0,
 106         SECONDARY = 1
 107     };
 108
 109   private:
 110     /** Primary command block registers */
 111     Addr pri_cmd_addr;
 112     Addr pri_cmd_size;
 113     /** Primary control block registers */
 114     Addr pri_ctrl_addr;
 115     Addr pri_ctrl_size;
 116     /** Secondary command block registers */
 117     Addr sec_cmd_addr;
 118     Addr sec_cmd_size;
 119     /** Secondary control block registers */
 120     Addr sec_ctrl_addr;
 121     Addr sec_ctrl_size;
 122     /** Bus master interface (BMI) registers */
 123     Addr bmi_addr;
 124     Addr bmi_size;
 125
 126   private:
 127     /** Registers used for bus master interface */
 128     union {
 129         uint8_t data[16];
 130
 131         struct {
 132             uint8_t bmic0;
 133             uint8_t reserved_0;
 134             uint8_t bmis0;
 135             uint8_t reserved_1;
 136             uint32_t bmidtp0;
 137             uint8_t bmic1;
 138             uint8_t reserved_2;
 139             uint8_t bmis1;
 140             uint8_t reserved_3;
 141             uint32_t bmidtp1;
 142         };
 143
 144         struct {
 145             uint8_t bmic;
 146             uint8_t reserved_4;
 147             uint8_t bmis;
 148             uint8_t reserved_5;
 149             uint32_t bmidtp;
 150         } chan[2];
 151
 152     } bmi_regs;
 153     /** Shadows of the device select bit */
 154     uint8_t dev[2];
 155     /** Registers used in device specific PCI configuration */
 156     union {
 157         uint8_t data[22];
 158
 159         struct {
 160             uint16_t idetim0;
 161             uint16_t idetim1;
 162             uint8_t sidetim;
 163             uint8_t reserved_0[3];
 164             uint8_t udmactl;
 165             uint8_t reserved_1;
 166             uint16_t udmatim;
 167             uint8_t reserved_2[8];
 168             uint16_t ideconfig;
 169         };
 170     } config_regs;
 171
 172     // Internal management variables
 173     bool io_enabled;
 174     bool bm_enabled;
 175     bool cmd_in_progress[4];
 176
 177   private:
 178     /** IDE disks connected to controller */
 179     IdeDisk *disks[4];
 180
 181   private:
 182     /** Parse the access address to pass on to device */
 183     void parseAddr(const Addr &addr, Addr &offset, IdeChannel &channel,
 184                    IdeRegType &reg_type);
 185
 186     /** Select the disk based on the channel and device bit */
 187     int getDisk(IdeChannel channel);
 188
 189     /** Select the disk based on a pointer */
 190     int getDisk(IdeDisk *diskPtr);
 191
 192   public:
 193     /** See if a disk is selected based on its pointer */
 194     bool isDiskSelected(IdeDisk *diskPtr);
 195
 196   public:
 197     typedef IdeControllerParams Params;
 198     const Params *params() const { return (const Params *)_params; }
 199     IdeController(Params *p);
 200     ~IdeController();
 201
 202     virtual Tick writeConfig(PacketPtr pkt);
 203     virtual Tick readConfig(PacketPtr pkt);
 204
 205     void setDmaComplete(IdeDisk *disk);
 206
 207     /**
 208      * Read a done field for a given target.
 209      * @param pkt Packet describing what is to be read
 210      * @return The amount of time to complete this request
 211      */
 212     virtual Tick read(PacketPtr pkt);
 213
 214     /**
 215      * Write a done field for a given target.
 216      * @param pkt Packet describing what is to be written
 217      * @return The amount of time to complete this request
 218      */
 219     virtual Tick write(PacketPtr pkt);
 220
 221     /**
 222      * Serialize this object to the given output stream.
 223      * @param os The stream to serialize to.
 224      */
 225     virtual void serialize(std::ostream &os);
 226
 227     /**
 228      * Reconstruct the state of this object from a checkpoint.
 229      * @param cp The checkpoint use.
 230      * @param section The section name of this object
 231      */
 232     virtual void unserialize(Checkpoint *cp, const std::string &section);
 233
 234 };
 235 #endif // __IDE_CTRL_HH_