83faf508eeec477f53dd04764d737a77cc0fdc7f
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Andrew Schultz
33 * Device model implementation for an IDE disk
41 #include "arch/isa_traits.hh"
42 #include "base/chunk_generator.hh"
43 #include "base/cprintf.hh" // csprintf
44 #include "base/trace.hh"
45 #include "dev/disk_image.hh"
46 #include "dev/ide_ctrl.hh"
47 #include "dev/ide_disk.hh"
48 #include "sim/core.hh"
49 #include "sim/sim_object.hh"
52 using namespace TheISA
;
54 IdeDisk::IdeDisk(const Params
*p
)
55 : SimObject(p
), ctrl(NULL
), image(p
->image
), diskDelay(p
->delay
),
56 dmaTransferEvent(this), dmaReadCG(NULL
), dmaReadWaitEvent(this),
57 dmaWriteCG(NULL
), dmaWriteWaitEvent(this), dmaPrdReadEvent(this),
58 dmaReadEvent(this), dmaWriteEvent(this)
60 // Reset the device state
63 // fill out the drive ID structure
64 memset(&driveID
, 0, sizeof(struct ataparams
));
66 // Calculate LBA and C/H/S values
71 uint32_t lba_size
= image
->size();
72 if (lba_size
>= 16383*16*63) {
82 if ((lba_size
/ sectors
) >= 16)
85 heads
= (lba_size
/ sectors
);
87 cylinders
= lba_size
/ (heads
* sectors
);
90 // Setup the model name
91 strncpy((char *)driveID
.atap_model
, "5MI EDD si k",
92 sizeof(driveID
.atap_model
));
93 // Set the maximum multisector transfer size
94 driveID
.atap_multi
= MAX_MULTSECT
;
95 // IORDY supported, IORDY disabled, LBA enabled, DMA enabled
96 driveID
.atap_capabilities1
= 0x7;
97 // UDMA support, EIDE support
98 driveID
.atap_extensions
= 0x6;
99 // Setup default C/H/S settings
100 driveID
.atap_cylinders
= cylinders
;
101 driveID
.atap_sectors
= sectors
;
102 driveID
.atap_heads
= heads
;
103 // Setup the current multisector transfer size
104 driveID
.atap_curmulti
= MAX_MULTSECT
;
105 driveID
.atap_curmulti_valid
= 0x1;
106 // Number of sectors on disk
107 driveID
.atap_capacity
= lba_size
;
108 // Multiword DMA mode 2 and below supported
109 driveID
.atap_dmamode_supp
= 0x4;
110 // Set PIO mode 4 and 3 supported
111 driveID
.atap_piomode_supp
= 0x3;
112 // Set DMA mode 4 and below supported
113 driveID
.atap_udmamode_supp
= 0x1f;
114 // Statically set hardware config word
115 driveID
.atap_hwreset_res
= 0x4001;
117 //arbitrary for now...
118 driveID
.atap_ata_major
= WDC_VER_ATA7
;
123 // destroy the data buffer
124 delete [] dataBuffer
;
128 IdeDisk::reset(int id
)
130 // initialize the data buffer and shadow registers
131 dataBuffer
= new uint8_t[MAX_DMA_SIZE
];
133 memset(dataBuffer
, 0, MAX_DMA_SIZE
);
134 memset(&cmdReg
, 0, sizeof(CommandReg_t
));
135 memset(&curPrd
.entry
, 0, sizeof(PrdEntry_t
));
145 // set the device state to idle
149 devState
= Device_Idle_S
;
151 } else if (id
== DEV1
) {
152 devState
= Device_Idle_NS
;
155 panic("Invalid device ID: %#x\n", id
);
158 // set the device ready bit
159 status
= STATUS_DRDY_BIT
;
161 /* The error register must be set to 0x1 on start-up to
162 indicate that no diagnostic error was detected */
171 IdeDisk::isDEVSelect()
173 return ctrl
->isDiskSelected(this);
177 IdeDisk::pciToDma(Addr pciAddr
)
180 return ctrl
->pciToDma(pciAddr
);
182 panic("Access to unset controller!\n");
186 // Device registers read/write
190 IdeDisk::readCommand(const Addr offset
, int size
, uint8_t *data
)
192 if (offset
== DATA_OFFSET
) {
193 if (size
== sizeof(uint16_t)) {
194 *(uint16_t *)data
= cmdReg
.data
;
195 } else if (size
== sizeof(uint32_t)) {
196 *(uint16_t *)data
= cmdReg
.data
;
197 updateState(ACT_DATA_READ_SHORT
);
198 *((uint16_t *)data
+ 1) = cmdReg
.data
;
200 panic("Data read of unsupported size %d.\n", size
);
202 updateState(ACT_DATA_READ_SHORT
);
205 assert(size
== sizeof(uint8_t));
208 *data
= cmdReg
.error
;
211 *data
= cmdReg
.sec_count
;
214 *data
= cmdReg
.sec_num
;
217 *data
= cmdReg
.cyl_low
;
220 *data
= cmdReg
.cyl_high
;
223 *data
= cmdReg
.drive
;
227 updateState(ACT_STAT_READ
);
230 panic("Invalid IDE command register offset: %#x\n", offset
);
232 DPRINTF(IdeDisk
, "Read to disk at offset: %#x data %#x\n", offset
, *data
);
236 IdeDisk::readControl(const Addr offset
, int size
, uint8_t *data
)
238 assert(size
== sizeof(uint8_t));
240 if (offset
!= ALTSTAT_OFFSET
)
241 panic("Invalid IDE control register offset: %#x\n", offset
);
242 DPRINTF(IdeDisk
, "Read to disk at offset: %#x data %#x\n", offset
, *data
);
246 IdeDisk::writeCommand(const Addr offset
, int size
, const uint8_t *data
)
248 if (offset
== DATA_OFFSET
) {
249 if (size
== sizeof(uint16_t)) {
250 cmdReg
.data
= *(const uint16_t *)data
;
251 } else if (size
== sizeof(uint32_t)) {
252 cmdReg
.data
= *(const uint16_t *)data
;
253 updateState(ACT_DATA_WRITE_SHORT
);
254 cmdReg
.data
= *((const uint16_t *)data
+ 1);
256 panic("Data write of unsupported size %d.\n", size
);
258 updateState(ACT_DATA_WRITE_SHORT
);
262 assert(size
== sizeof(uint8_t));
264 case FEATURES_OFFSET
:
267 cmdReg
.sec_count
= *data
;
270 cmdReg
.sec_num
= *data
;
273 cmdReg
.cyl_low
= *data
;
276 cmdReg
.cyl_high
= *data
;
279 cmdReg
.drive
= *data
;
280 updateState(ACT_SELECT_WRITE
);
283 cmdReg
.command
= *data
;
284 updateState(ACT_CMD_WRITE
);
287 panic("Invalid IDE command register offset: %#x\n", offset
);
289 DPRINTF(IdeDisk
, "Write to disk at offset: %#x data %#x\n", offset
,
294 IdeDisk::writeControl(const Addr offset
, int size
, const uint8_t *data
)
296 if (offset
!= CONTROL_OFFSET
)
297 panic("Invalid IDE control register offset: %#x\n", offset
);
299 if (*data
& CONTROL_RST_BIT
) {
300 // force the device into the reset state
301 devState
= Device_Srst
;
302 updateState(ACT_SRST_SET
);
303 } else if (devState
== Device_Srst
&& !(*data
& CONTROL_RST_BIT
)) {
304 updateState(ACT_SRST_CLEAR
);
307 nIENBit
= *data
& CONTROL_IEN_BIT
;
309 DPRINTF(IdeDisk
, "Write to disk at offset: %#x data %#x\n", offset
,
314 // Perform DMA transactions
318 IdeDisk::doDmaTransfer()
320 if (dmaState
!= Dma_Transfer
|| devState
!= Transfer_Data_Dma
)
321 panic("Inconsistent DMA transfer state: dmaState = %d devState = %d\n",
324 if (ctrl
->dmaPending() || ctrl
->getState() != SimObject::Running
) {
325 schedule(dmaTransferEvent
, curTick
+ DMA_BACKOFF_PERIOD
);
328 ctrl
->dmaRead(curPrdAddr
, sizeof(PrdEntry_t
), &dmaPrdReadEvent
,
329 (uint8_t*)&curPrd
.entry
);
333 IdeDisk::dmaPrdReadDone()
336 "PRD: baseAddr:%#x (%#x) byteCount:%d (%d) eot:%#x sector:%d\n",
337 curPrd
.getBaseAddr(), pciToDma(curPrd
.getBaseAddr()),
338 curPrd
.getByteCount(), (cmdBytesLeft
/SectorSize
),
339 curPrd
.getEOT(), curSector
);
341 // the prd pointer has already been translated, so just do an increment
342 curPrdAddr
= curPrdAddr
+ sizeof(PrdEntry_t
);
351 IdeDisk::doDmaDataRead()
353 /** @todo we need to figure out what the delay actually will be */
354 Tick totalDiskDelay
= diskDelay
+ (curPrd
.getByteCount() / SectorSize
);
356 DPRINTF(IdeDisk
, "doDmaRead, diskDelay: %d totalDiskDelay: %d\n",
357 diskDelay
, totalDiskDelay
);
359 schedule(dmaReadWaitEvent
, curTick
+ totalDiskDelay
);
365 using namespace Stats
;
367 .name(name() + ".dma_read_full_pages")
368 .desc("Number of full page size DMA reads (not PRD).")
371 .name(name() + ".dma_read_bytes")
372 .desc("Number of bytes transfered via DMA reads (not PRD).")
375 .name(name() + ".dma_read_txs")
376 .desc("Number of DMA read transactions (not PRD).")
380 .name(name() + ".dma_write_full_pages")
381 .desc("Number of full page size DMA writes.")
384 .name(name() + ".dma_write_bytes")
385 .desc("Number of bytes transfered via DMA writes.")
388 .name(name() + ".dma_write_txs")
389 .desc("Number of DMA write transactions.")
398 // clear out the data buffer
399 memset(dataBuffer
, 0, MAX_DMA_SIZE
);
400 dmaReadCG
= new ChunkGenerator(curPrd
.getBaseAddr(),
401 curPrd
.getByteCount(), TheISA::PageBytes
);
404 if (ctrl
->dmaPending() || ctrl
->getState() != SimObject::Running
) {
405 schedule(dmaReadWaitEvent
, curTick
+ DMA_BACKOFF_PERIOD
);
407 } else if (!dmaReadCG
->done()) {
408 assert(dmaReadCG
->complete() < MAX_DMA_SIZE
);
409 ctrl
->dmaRead(pciToDma(dmaReadCG
->addr()), dmaReadCG
->size(),
410 &dmaReadWaitEvent
, dataBuffer
+ dmaReadCG
->complete());
411 dmaReadBytes
+= dmaReadCG
->size();
413 if (dmaReadCG
->size() == TheISA::PageBytes
)
417 assert(dmaReadCG
->done());
425 IdeDisk::dmaReadDone()
428 uint32_t bytesWritten
= 0;
431 // write the data to the disk image
432 for (bytesWritten
= 0; bytesWritten
< curPrd
.getByteCount();
433 bytesWritten
+= SectorSize
) {
435 cmdBytesLeft
-= SectorSize
;
436 writeDisk(curSector
++, (uint8_t *)(dataBuffer
+ bytesWritten
));
440 if (curPrd
.getEOT()) {
441 assert(cmdBytesLeft
== 0);
443 updateState(ACT_DMA_DONE
);
450 IdeDisk::doDmaDataWrite()
452 /** @todo we need to figure out what the delay actually will be */
453 Tick totalDiskDelay
= diskDelay
+ (curPrd
.getByteCount() / SectorSize
);
454 uint32_t bytesRead
= 0;
456 DPRINTF(IdeDisk
, "doDmaWrite, diskDelay: %d totalDiskDelay: %d\n",
457 diskDelay
, totalDiskDelay
);
459 memset(dataBuffer
, 0, MAX_DMA_SIZE
);
460 assert(cmdBytesLeft
<= MAX_DMA_SIZE
);
461 while (bytesRead
< curPrd
.getByteCount()) {
462 readDisk(curSector
++, (uint8_t *)(dataBuffer
+ bytesRead
));
463 bytesRead
+= SectorSize
;
464 cmdBytesLeft
-= SectorSize
;
467 schedule(dmaWriteWaitEvent
, curTick
+ totalDiskDelay
);
471 IdeDisk::doDmaWrite()
475 // clear out the data buffer
476 dmaWriteCG
= new ChunkGenerator(curPrd
.getBaseAddr(),
477 curPrd
.getByteCount(), TheISA::PageBytes
);
479 if (ctrl
->dmaPending() || ctrl
->getState() != SimObject::Running
) {
480 schedule(dmaWriteWaitEvent
, curTick
+ DMA_BACKOFF_PERIOD
);
482 } else if (!dmaWriteCG
->done()) {
483 assert(dmaWriteCG
->complete() < MAX_DMA_SIZE
);
484 ctrl
->dmaWrite(pciToDma(dmaWriteCG
->addr()), dmaWriteCG
->size(),
485 &dmaWriteWaitEvent
, dataBuffer
+ dmaWriteCG
->complete());
486 dmaWriteBytes
+= dmaWriteCG
->size();
488 if (dmaWriteCG
->size() == TheISA::PageBytes
)
492 assert(dmaWriteCG
->done());
500 IdeDisk::dmaWriteDone()
503 if (curPrd
.getEOT()) {
504 assert(cmdBytesLeft
== 0);
506 updateState(ACT_DMA_DONE
);
513 // Disk utility routines
517 IdeDisk::readDisk(uint32_t sector
, uint8_t *data
)
519 uint32_t bytesRead
= image
->read(data
, sector
);
521 if (bytesRead
!= SectorSize
)
522 panic("Can't read from %s. Only %d of %d read. errno=%d\n",
523 name(), bytesRead
, SectorSize
, errno
);
527 IdeDisk::writeDisk(uint32_t sector
, uint8_t *data
)
529 uint32_t bytesWritten
= image
->write(data
, sector
);
531 if (bytesWritten
!= SectorSize
)
532 panic("Can't write to %s. Only %d of %d written. errno=%d\n",
533 name(), bytesWritten
, SectorSize
, errno
);
537 // Setup and handle commands
541 IdeDisk::startDma(const uint32_t &prdTableBase
)
543 if (dmaState
!= Dma_Start
)
544 panic("Inconsistent DMA state, should be in Dma_Start!\n");
546 if (devState
!= Transfer_Data_Dma
)
547 panic("Inconsistent device state for DMA start!\n");
549 // PRD base address is given by bits 31:2
550 curPrdAddr
= pciToDma((Addr
)(prdTableBase
& ~ULL(0x3)));
552 dmaState
= Dma_Transfer
;
554 // schedule dma transfer (doDmaTransfer)
555 schedule(dmaTransferEvent
, curTick
+ 1);
561 if (dmaState
== Dma_Idle
)
562 panic("Inconsistent DMA state, should be Start or Transfer!");
564 if (devState
!= Transfer_Data_Dma
&& devState
!= Prepare_Data_Dma
)
565 panic("Inconsistent device state, should be Transfer or Prepare!\n");
567 updateState(ACT_CMD_ERROR
);
571 IdeDisk::startCommand()
573 DevAction_t action
= ACT_NONE
;
578 switch (cmdReg
.command
) {
579 // Supported non-data commands
580 case WDSF_READ_NATIVE_MAX
:
581 size
= image
->size() - 1;
582 cmdReg
.sec_num
= (size
& 0xff);
583 cmdReg
.cyl_low
= ((size
& 0xff00) >> 8);
584 cmdReg
.cyl_high
= ((size
& 0xff0000) >> 16);
585 cmdReg
.head
= ((size
& 0xf000000) >> 24);
587 devState
= Command_Execution
;
588 action
= ACT_CMD_COMPLETE
;
593 case WDCC_STANDBY_IMMED
:
594 case WDCC_FLUSHCACHE
:
599 devState
= Command_Execution
;
600 action
= ACT_CMD_COMPLETE
;
603 // Supported PIO data-in commands
605 cmdBytes
= cmdBytesLeft
= sizeof(struct ataparams
);
606 devState
= Prepare_Data_In
;
607 action
= ACT_DATA_READY
;
612 if (!(cmdReg
.drive
& DRIVE_LBA_BIT
))
613 panic("Attempt to perform CHS access, only supports LBA\n");
615 if (cmdReg
.sec_count
== 0)
616 cmdBytes
= cmdBytesLeft
= (256 * SectorSize
);
618 cmdBytes
= cmdBytesLeft
= (cmdReg
.sec_count
* SectorSize
);
620 curSector
= getLBABase();
622 /** @todo make this a scheduled event to simulate disk delay */
623 devState
= Prepare_Data_In
;
624 action
= ACT_DATA_READY
;
627 // Supported PIO data-out commands
628 case WDCC_WRITEMULTI
:
630 if (!(cmdReg
.drive
& DRIVE_LBA_BIT
))
631 panic("Attempt to perform CHS access, only supports LBA\n");
633 if (cmdReg
.sec_count
== 0)
634 cmdBytes
= cmdBytesLeft
= (256 * SectorSize
);
636 cmdBytes
= cmdBytesLeft
= (cmdReg
.sec_count
* SectorSize
);
638 curSector
= getLBABase();
640 devState
= Prepare_Data_Out
;
641 action
= ACT_DATA_READY
;
644 // Supported DMA commands
646 dmaRead
= true; // a write to the disk is a DMA read from memory
648 if (!(cmdReg
.drive
& DRIVE_LBA_BIT
))
649 panic("Attempt to perform CHS access, only supports LBA\n");
651 if (cmdReg
.sec_count
== 0)
652 cmdBytes
= cmdBytesLeft
= (256 * SectorSize
);
654 cmdBytes
= cmdBytesLeft
= (cmdReg
.sec_count
* SectorSize
);
656 curSector
= getLBABase();
658 devState
= Prepare_Data_Dma
;
659 action
= ACT_DMA_READY
;
663 panic("Unsupported ATA command: %#x\n", cmdReg
.command
);
666 if (action
!= ACT_NONE
) {
668 status
|= STATUS_BSY_BIT
;
670 status
&= ~STATUS_DRQ_BIT
;
672 status
&= ~STATUS_DF_BIT
;
679 // Handle setting and clearing interrupts
685 DPRINTF(IdeDisk
, "Posting Interrupt\n");
687 panic("Attempt to post an interrupt with one pending\n");
691 // talk to controller to set interrupt
700 DPRINTF(IdeDisk
, "Clearing Interrupt\n");
702 panic("Attempt to clear a non-pending interrupt\n");
706 // talk to controller to clear interrupt
712 // Manage the device internal state machine
716 IdeDisk::updateState(DevAction_t action
)
720 if (action
== ACT_SRST_SET
) {
722 status
|= STATUS_BSY_BIT
;
723 } else if (action
== ACT_SRST_CLEAR
) {
725 status
&= ~STATUS_BSY_BIT
;
727 // reset the device state
733 if (action
== ACT_SELECT_WRITE
&& !isDEVSelect()) {
734 devState
= Device_Idle_NS
;
735 } else if (action
== ACT_CMD_WRITE
) {
742 if (action
== ACT_SELECT_WRITE
&& !isDEVSelect()) {
743 devState
= Device_Idle_NS
;
745 } else if (action
== ACT_STAT_READ
|| isIENSet()) {
746 devState
= Device_Idle_S
;
748 } else if (action
== ACT_CMD_WRITE
) {
756 if (action
== ACT_SELECT_WRITE
&& isDEVSelect()) {
757 if (!isIENSet() && intrPending
) {
758 devState
= Device_Idle_SI
;
761 if (isIENSet() || !intrPending
) {
762 devState
= Device_Idle_S
;
767 case Command_Execution
:
768 if (action
== ACT_CMD_COMPLETE
) {
773 devState
= Device_Idle_SI
;
776 devState
= Device_Idle_S
;
781 case Prepare_Data_In
:
782 if (action
== ACT_CMD_ERROR
) {
787 devState
= Device_Idle_SI
;
790 devState
= Device_Idle_S
;
792 } else if (action
== ACT_DATA_READY
) {
794 status
&= ~STATUS_BSY_BIT
;
796 status
|= STATUS_DRQ_BIT
;
798 // copy the data into the data buffer
799 if (cmdReg
.command
== WDCC_IDENTIFY
) {
800 // Reset the drqBytes for this block
801 drqBytesLeft
= sizeof(struct ataparams
);
803 memcpy((void *)dataBuffer
, (void *)&driveID
,
804 sizeof(struct ataparams
));
806 // Reset the drqBytes for this block
807 drqBytesLeft
= SectorSize
;
809 readDisk(curSector
++, dataBuffer
);
812 // put the first two bytes into the data register
813 memcpy((void *)&cmdReg
.data
, (void *)dataBuffer
,
817 devState
= Data_Ready_INTRQ_In
;
820 devState
= Transfer_Data_In
;
825 case Data_Ready_INTRQ_In
:
826 if (action
== ACT_STAT_READ
) {
827 devState
= Transfer_Data_In
;
832 case Transfer_Data_In
:
833 if (action
== ACT_DATA_READ_BYTE
|| action
== ACT_DATA_READ_SHORT
) {
834 if (action
== ACT_DATA_READ_BYTE
) {
835 panic("DEBUG: READING DATA ONE BYTE AT A TIME!\n");
840 // copy next short into data registers
842 memcpy((void *)&cmdReg
.data
,
843 (void *)&dataBuffer
[SectorSize
- drqBytesLeft
],
847 if (drqBytesLeft
== 0) {
848 if (cmdBytesLeft
== 0) {
851 devState
= Device_Idle_S
;
853 devState
= Prepare_Data_In
;
855 status
|= STATUS_BSY_BIT
;
857 status
&= ~STATUS_DRQ_BIT
;
859 /** @todo change this to a scheduled event to simulate
861 updateState(ACT_DATA_READY
);
867 case Prepare_Data_Out
:
868 if (action
== ACT_CMD_ERROR
|| cmdBytesLeft
== 0) {
873 devState
= Device_Idle_SI
;
876 devState
= Device_Idle_S
;
878 } else if (action
== ACT_DATA_READY
&& cmdBytesLeft
!= 0) {
880 status
&= ~STATUS_BSY_BIT
;
882 status
|= STATUS_DRQ_BIT
;
884 // clear the data buffer to get it ready for writes
885 memset(dataBuffer
, 0, MAX_DMA_SIZE
);
887 // reset the drqBytes for this block
888 drqBytesLeft
= SectorSize
;
890 if (cmdBytesLeft
== cmdBytes
|| isIENSet()) {
891 devState
= Transfer_Data_Out
;
893 devState
= Data_Ready_INTRQ_Out
;
899 case Data_Ready_INTRQ_Out
:
900 if (action
== ACT_STAT_READ
) {
901 devState
= Transfer_Data_Out
;
906 case Transfer_Data_Out
:
907 if (action
== ACT_DATA_WRITE_BYTE
||
908 action
== ACT_DATA_WRITE_SHORT
) {
910 if (action
== ACT_DATA_READ_BYTE
) {
911 panic("DEBUG: WRITING DATA ONE BYTE AT A TIME!\n");
913 // copy the latest short into the data buffer
914 memcpy((void *)&dataBuffer
[SectorSize
- drqBytesLeft
],
915 (void *)&cmdReg
.data
,
922 if (drqBytesLeft
== 0) {
923 // copy the block to the disk
924 writeDisk(curSector
++, dataBuffer
);
927 status
|= STATUS_BSY_BIT
;
929 status
|= STATUS_SEEK_BIT
;
931 status
&= ~STATUS_DRQ_BIT
;
933 devState
= Prepare_Data_Out
;
935 /** @todo change this to a scheduled event to simulate
937 updateState(ACT_DATA_READY
);
942 case Prepare_Data_Dma
:
943 if (action
== ACT_CMD_ERROR
) {
948 devState
= Device_Idle_SI
;
951 devState
= Device_Idle_S
;
953 } else if (action
== ACT_DMA_READY
) {
955 status
&= ~STATUS_BSY_BIT
;
957 status
|= STATUS_DRQ_BIT
;
959 devState
= Transfer_Data_Dma
;
961 if (dmaState
!= Dma_Idle
)
962 panic("Inconsistent DMA state, should be Dma_Idle\n");
964 dmaState
= Dma_Start
;
965 // wait for the write to the DMA start bit
969 case Transfer_Data_Dma
:
970 if (action
== ACT_CMD_ERROR
|| action
== ACT_DMA_DONE
) {
974 status
|= STATUS_SEEK_BIT
;
975 // clear the controller state for DMA transfer
976 ctrl
->setDmaComplete(this);
979 devState
= Device_Idle_SI
;
982 devState
= Device_Idle_S
;
988 panic("Unknown IDE device state: %#x\n", devState
);
993 IdeDisk::serialize(ostream
&os
)
995 // Check all outstanding events to see if they are scheduled
996 // these are all mutually exclusive
998 Events_t event
= None
;
1002 if (dmaTransferEvent
.scheduled()) {
1003 reschedule
= dmaTransferEvent
.when();
1007 if (dmaReadWaitEvent
.scheduled()) {
1008 reschedule
= dmaReadWaitEvent
.when();
1012 if (dmaWriteWaitEvent
.scheduled()) {
1013 reschedule
= dmaWriteWaitEvent
.when();
1017 if (dmaPrdReadEvent
.scheduled()) {
1018 reschedule
= dmaPrdReadEvent
.when();
1022 if (dmaReadEvent
.scheduled()) {
1023 reschedule
= dmaReadEvent
.when();
1027 if (dmaWriteEvent
.scheduled()) {
1028 reschedule
= dmaWriteEvent
.when();
1033 assert(eventCount
<= 1);
1035 SERIALIZE_SCALAR(reschedule
);
1036 SERIALIZE_ENUM(event
);
1038 // Serialize device registers
1039 SERIALIZE_SCALAR(cmdReg
.data
);
1040 SERIALIZE_SCALAR(cmdReg
.sec_count
);
1041 SERIALIZE_SCALAR(cmdReg
.sec_num
);
1042 SERIALIZE_SCALAR(cmdReg
.cyl_low
);
1043 SERIALIZE_SCALAR(cmdReg
.cyl_high
);
1044 SERIALIZE_SCALAR(cmdReg
.drive
);
1045 SERIALIZE_SCALAR(cmdReg
.command
);
1046 SERIALIZE_SCALAR(status
);
1047 SERIALIZE_SCALAR(nIENBit
);
1048 SERIALIZE_SCALAR(devID
);
1050 // Serialize the PRD related information
1051 SERIALIZE_SCALAR(curPrd
.entry
.baseAddr
);
1052 SERIALIZE_SCALAR(curPrd
.entry
.byteCount
);
1053 SERIALIZE_SCALAR(curPrd
.entry
.endOfTable
);
1054 SERIALIZE_SCALAR(curPrdAddr
);
1056 /** @todo need to serialized chunk generator stuff!! */
1057 // Serialize current transfer related information
1058 SERIALIZE_SCALAR(cmdBytesLeft
);
1059 SERIALIZE_SCALAR(cmdBytes
);
1060 SERIALIZE_SCALAR(drqBytesLeft
);
1061 SERIALIZE_SCALAR(curSector
);
1062 SERIALIZE_SCALAR(dmaRead
);
1063 SERIALIZE_SCALAR(intrPending
);
1064 SERIALIZE_ENUM(devState
);
1065 SERIALIZE_ENUM(dmaState
);
1066 SERIALIZE_ARRAY(dataBuffer
, MAX_DMA_SIZE
);
1070 IdeDisk::unserialize(Checkpoint
*cp
, const string
§ion
)
1072 // Reschedule events that were outstanding
1073 // these are all mutually exclusive
1074 Tick reschedule
= 0;
1075 Events_t event
= None
;
1077 UNSERIALIZE_SCALAR(reschedule
);
1078 UNSERIALIZE_ENUM(event
);
1082 case Transfer
: schedule(dmaTransferEvent
, reschedule
); break;
1083 case ReadWait
: schedule(dmaReadWaitEvent
, reschedule
); break;
1084 case WriteWait
: schedule(dmaWriteWaitEvent
, reschedule
); break;
1085 case PrdRead
: schedule(dmaPrdReadEvent
, reschedule
); break;
1086 case DmaRead
: schedule(dmaReadEvent
, reschedule
); break;
1087 case DmaWrite
: schedule(dmaWriteEvent
, reschedule
); break;
1090 // Unserialize device registers
1091 UNSERIALIZE_SCALAR(cmdReg
.data
);
1092 UNSERIALIZE_SCALAR(cmdReg
.sec_count
);
1093 UNSERIALIZE_SCALAR(cmdReg
.sec_num
);
1094 UNSERIALIZE_SCALAR(cmdReg
.cyl_low
);
1095 UNSERIALIZE_SCALAR(cmdReg
.cyl_high
);
1096 UNSERIALIZE_SCALAR(cmdReg
.drive
);
1097 UNSERIALIZE_SCALAR(cmdReg
.command
);
1098 UNSERIALIZE_SCALAR(status
);
1099 UNSERIALIZE_SCALAR(nIENBit
);
1100 UNSERIALIZE_SCALAR(devID
);
1102 // Unserialize the PRD related information
1103 UNSERIALIZE_SCALAR(curPrd
.entry
.baseAddr
);
1104 UNSERIALIZE_SCALAR(curPrd
.entry
.byteCount
);
1105 UNSERIALIZE_SCALAR(curPrd
.entry
.endOfTable
);
1106 UNSERIALIZE_SCALAR(curPrdAddr
);
1108 /** @todo need to serialized chunk generator stuff!! */
1109 // Unserialize current transfer related information
1110 UNSERIALIZE_SCALAR(cmdBytes
);
1111 UNSERIALIZE_SCALAR(cmdBytesLeft
);
1112 UNSERIALIZE_SCALAR(drqBytesLeft
);
1113 UNSERIALIZE_SCALAR(curSector
);
1114 UNSERIALIZE_SCALAR(dmaRead
);
1115 UNSERIALIZE_SCALAR(intrPending
);
1116 UNSERIALIZE_ENUM(devState
);
1117 UNSERIALIZE_ENUM(dmaState
);
1118 UNSERIALIZE_ARRAY(dataBuffer
, MAX_DMA_SIZE
);
1122 IdeDiskParams::create()
1124 return new IdeDisk(this);