src/dev/ide_disk.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Andrew Schultz
  29  */
  30
  31 /** @file
  32  * Device model for an IDE disk
  33  */
  34
  35 #ifndef __IDE_DISK_HH__
  36 #define __IDE_DISK_HH__
  37
  38 #include "base/statistics.hh"
  39 #include "dev/disk_image.hh"
  40 #include "dev/ide_atareg.h"
  41 #include "dev/ide_ctrl.hh"
  42 #include "dev/ide_wdcreg.h"
  43 #include "dev/io_device.hh"
  44 #include "sim/eventq.hh"
  45
  46 class ChunkGenerator;
  47
  48 #define DMA_BACKOFF_PERIOD 200
  49
  50 #define MAX_DMA_SIZE    (131072)  // 128K
  51 #define MAX_MULTSECT    (128)
  52
  53 #define PRD_BASE_MASK  0xfffffffe
  54 #define PRD_COUNT_MASK 0xfffe
  55 #define PRD_EOT_MASK   0x8000
  56
  57 typedef struct PrdEntry {
  58     uint32_t baseAddr;
  59     uint16_t byteCount;
  60     uint16_t endOfTable;
  61 } PrdEntry_t;
  62
  63 class PrdTableEntry {
  64   public:
  65     PrdEntry_t entry;
  66
  67     uint32_t getBaseAddr()
  68     {
  69         return (entry.baseAddr & PRD_BASE_MASK);
  70     }
  71
  72     uint32_t getByteCount()
  73     {
  74         return ((entry.byteCount == 0) ? MAX_DMA_SIZE :
  75                 (entry.byteCount & PRD_COUNT_MASK));
  76     }
  77
  78     uint16_t getEOT()
  79     {
  80         return (entry.endOfTable & PRD_EOT_MASK);
  81     }
  82 };
  83
  84 #define DATA_OFFSET     (0)
  85 #define ERROR_OFFSET    (1)
  86 #define FEATURES_OFFSET (1)
  87 #define NSECTOR_OFFSET  (2)
  88 #define SECTOR_OFFSET   (3)
  89 #define LCYL_OFFSET     (4)
  90 #define HCYL_OFFSET     (5)
  91 #define SELECT_OFFSET   (6)
  92 #define DRIVE_OFFSET    (6)
  93 #define STATUS_OFFSET   (7)
  94 #define COMMAND_OFFSET  (7)
  95
  96 #define CONTROL_OFFSET  (2)
  97 #define ALTSTAT_OFFSET  (2)
  98
  99 #define SELECT_DEV_BIT  0x10
 100 #define CONTROL_RST_BIT 0x04
 101 #define CONTROL_IEN_BIT 0x02
 102 #define STATUS_BSY_BIT  0x80
 103 #define STATUS_DRDY_BIT 0x40
 104 #define STATUS_DRQ_BIT  0x08
 105 #define STATUS_SEEK_BIT 0x10
 106 #define STATUS_DF_BIT   0x20
 107 #define DRIVE_LBA_BIT   0x40
 108
 109 #define DEV0 (0)
 110 #define DEV1 (1)
 111
 112 typedef struct CommandReg {
 113     uint16_t data;
 114     uint8_t error;
 115     uint8_t sec_count;
 116     uint8_t sec_num;
 117     uint8_t cyl_low;
 118     uint8_t cyl_high;
 119     union {
 120         uint8_t drive;
 121         uint8_t head;
 122     };
 123     uint8_t command;
 124 } CommandReg_t;
 125
 126 typedef enum Events {
 127     None = 0,
 128     Transfer,
 129     ReadWait,
 130     WriteWait,
 131     PrdRead,
 132     DmaRead,
 133     DmaWrite
 134 } Events_t;
 135
 136 typedef enum DevAction {
 137     ACT_NONE = 0,
 138     ACT_CMD_WRITE,
 139     ACT_CMD_COMPLETE,
 140     ACT_CMD_ERROR,
 141     ACT_SELECT_WRITE,
 142     ACT_STAT_READ,
 143     ACT_DATA_READY,
 144     ACT_DATA_READ_BYTE,
 145     ACT_DATA_READ_SHORT,
 146     ACT_DATA_WRITE_BYTE,
 147     ACT_DATA_WRITE_SHORT,
 148     ACT_DMA_READY,
 149     ACT_DMA_DONE,
 150     ACT_SRST_SET,
 151     ACT_SRST_CLEAR
 152 } DevAction_t;
 153
 154 typedef enum DevState {
 155     // Device idle
 156     Device_Idle_S = 0,
 157     Device_Idle_SI,
 158     Device_Idle_NS,
 159
 160     // Software reset
 161     Device_Srst,
 162
 163     // Non-data commands
 164     Command_Execution,
 165
 166     // PIO data-in (data to host)
 167     Prepare_Data_In,
 168     Data_Ready_INTRQ_In,
 169     Transfer_Data_In,
 170
 171     // PIO data-out (data from host)
 172     Prepare_Data_Out,
 173     Data_Ready_INTRQ_Out,
 174     Transfer_Data_Out,
 175
 176     // DMA protocol
 177     Prepare_Data_Dma,
 178     Transfer_Data_Dma
 179 } DevState_t;
 180
 181 typedef enum DmaState {
 182     Dma_Idle = 0,
 183     Dma_Start,
 184     Dma_Transfer
 185 } DmaState_t;
 186
 187 class PhysicalMemory;
 188 class IdeController;
 189
 190 /**
 191  * IDE Disk device model
 192  */
 193 class IdeDisk : public SimObject
 194 {
 195   protected:
 196     /** The IDE controller for this disk. */
 197     IdeController *ctrl;
 198     /** The image that contains the data of this disk. */
 199     DiskImage *image;
 200
 201   protected:
 202     /** The disk delay in microseconds. */
 203     int diskDelay;
 204
 205   private:
 206     /** Drive identification structure for this disk */
 207     struct ataparams driveID;
 208     /** Data buffer for transfers */
 209     uint8_t *dataBuffer;
 210     /** Number of bytes in command data transfer */
 211     uint32_t cmdBytes;
 212     /** Number of bytes left in command data transfer */
 213     uint32_t cmdBytesLeft;
 214     /** Number of bytes left in DRQ block */
 215     uint32_t drqBytesLeft;
 216     /** Current sector in access */
 217     uint32_t curSector;
 218     /** Command block registers */
 219     CommandReg_t cmdReg;
 220     /** Status register */
 221     uint8_t status;
 222     /** Interrupt enable bit */
 223     bool nIENBit;
 224     /** Device state */
 225     DevState_t devState;
 226     /** Dma state */
 227     DmaState_t dmaState;
 228     /** Dma transaction is a read */
 229     bool dmaRead;
 230     /** PRD table base address */
 231     uint32_t curPrdAddr;
 232     /** PRD entry */
 233     PrdTableEntry curPrd;
 234     /** Device ID (master=0/slave=1) */
 235     int devID;
 236     /** Interrupt pending */
 237     bool intrPending;
 238
 239     Stats::Scalar<> dmaReadFullPages;
 240     Stats::Scalar<> dmaReadBytes;
 241     Stats::Scalar<> dmaReadTxs;
 242     Stats::Scalar<> dmaWriteFullPages;
 243     Stats::Scalar<> dmaWriteBytes;
 244     Stats::Scalar<> dmaWriteTxs;
 245
 246   public:
 247     /**
 248      * Create and initialize this Disk.
 249      * @param name The name of this disk.
 250      * @param img The disk image of this disk.
 251      * @param id The disk ID (master=0/slave=1)
 252      * @param disk_delay The disk delay in milliseconds
 253      */
 254     IdeDisk(const std::string &name, DiskImage *img, int id, Tick disk_delay);
 255
 256     /**
 257      * Delete the data buffer.
 258      */
 259     ~IdeDisk();
 260
 261     /**
 262      * Reset the device state
 263      */
 264     void reset(int id);
 265
 266     /**
 267      * Register Statistics
 268      */
 269     void regStats();
 270
 271     /**
 272      * Set the controller for this device
 273      * @param c The IDE controller
 274      */
 275     void setController(IdeController *c) {
 276         if (ctrl) panic("Cannot change the controller once set!\n");
 277         ctrl = c;
 278     }
 279
 280     // Device register read/write
 281     void read(const Addr &offset, IdeRegType regtype, uint8_t *data);
 282     void write(const Addr &offset, IdeRegType regtype, const uint8_t *data);
 283
 284     // Start/abort functions
 285     void startDma(const uint32_t &prdTableBase);
 286     void abortDma();
 287
 288   private:
 289     void startCommand();
 290
 291     // Interrupt management
 292     void intrPost();
 293     void intrClear();
 294
 295     // DMA stuff
 296     void doDmaTransfer();
 297     friend class EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer>;
 298     EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer> dmaTransferEvent;
 299
 300     void doDmaDataRead();
 301
 302     void doDmaRead();
 303     ChunkGenerator *dmaReadCG;
 304     friend class EventWrapper<IdeDisk, &IdeDisk::doDmaRead>;
 305     EventWrapper<IdeDisk, &IdeDisk::doDmaRead> dmaReadWaitEvent;
 306
 307     void doDmaDataWrite();
 308
 309     void doDmaWrite();
 310     ChunkGenerator *dmaWriteCG;
 311     friend class EventWrapper<IdeDisk, &IdeDisk::doDmaWrite>;
 312     EventWrapper<IdeDisk, &IdeDisk::doDmaWrite> dmaWriteWaitEvent;
 313
 314     void dmaPrdReadDone();
 315     friend class EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone>;
 316     EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone> dmaPrdReadEvent;
 317
 318     void dmaReadDone();
 319     friend class EventWrapper<IdeDisk, &IdeDisk::dmaReadDone>;
 320     EventWrapper<IdeDisk, &IdeDisk::dmaReadDone> dmaReadEvent;
 321
 322     void dmaWriteDone();
 323     friend class EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone>;
 324     EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone> dmaWriteEvent;
 325
 326     // Disk image read/write
 327     void readDisk(uint32_t sector, uint8_t *data);
 328     void writeDisk(uint32_t sector, uint8_t *data);
 329
 330     // State machine management
 331     void updateState(DevAction_t action);
 332
 333     // Utility functions
 334     bool isBSYSet() { return (status & STATUS_BSY_BIT); }
 335     bool isIENSet() { return nIENBit; }
 336     bool isDEVSelect();
 337
 338     void setComplete()
 339     {
 340         // clear out the status byte
 341         status = 0;
 342         // set the DRDY bit
 343         status |= STATUS_DRDY_BIT;
 344         // set the SEEK bit
 345         status |= STATUS_SEEK_BIT;
 346     }
 347
 348     uint32_t getLBABase()
 349     {
 350         return  (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
 351                        (cmdReg.cyl_low << 8) | (cmdReg.sec_num));
 352     }
 353
 354     inline Addr pciToDma(Addr pciAddr);
 355
 356     /**
 357      * Serialize this object to the given output stream.
 358      * @param os The stream to serialize to.
 359      */
 360     void serialize(std::ostream &os);
 361
 362     /**
 363      * Reconstruct the state of this object from a checkpoint.
 364      * @param cp The checkpoint to use.
 365      * @param section The section name describing this object.
 366      */
 367     void unserialize(Checkpoint *cp, const std::string &section);
 368 };
 369
 370
 371 #endif // __IDE_DISK_HH__