2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Andrew Schultz
32 * Device model for an IDE disk
35 #ifndef __IDE_DISK_HH__
36 #define __IDE_DISK_HH__
38 #include "base/statistics.hh"
39 #include "dev/disk_image.hh"
40 #include "dev/ide_atareg.h"
41 #include "dev/ide_ctrl.hh"
42 #include "dev/ide_wdcreg.h"
43 #include "dev/io_device.hh"
44 #include "sim/eventq.hh"
45 #include "params/IdeDisk.hh"
50 #define DMA_BACKOFF_PERIOD 200
52 #define MAX_DMA_SIZE (131072) // 128K
53 #define MAX_MULTSECT (128)
55 #define PRD_BASE_MASK 0xfffffffe
56 #define PRD_COUNT_MASK 0xfffe
57 #define PRD_EOT_MASK 0x8000
59 typedef struct PrdEntry {
69 uint32_t getBaseAddr()
71 return (entry.baseAddr & PRD_BASE_MASK);
74 uint32_t getByteCount()
76 return ((entry.byteCount == 0) ? MAX_DMA_SIZE :
77 (entry.byteCount & PRD_COUNT_MASK));
82 return (entry.endOfTable & PRD_EOT_MASK);
86 #define DATA_OFFSET (0)
87 #define ERROR_OFFSET (1)
88 #define FEATURES_OFFSET (1)
89 #define NSECTOR_OFFSET (2)
90 #define SECTOR_OFFSET (3)
91 #define LCYL_OFFSET (4)
92 #define HCYL_OFFSET (5)
93 #define SELECT_OFFSET (6)
94 #define DRIVE_OFFSET (6)
95 #define STATUS_OFFSET (7)
96 #define COMMAND_OFFSET (7)
98 #define CONTROL_OFFSET (2)
99 #define ALTSTAT_OFFSET (2)
101 #define SELECT_DEV_BIT 0x10
102 #define CONTROL_RST_BIT 0x04
103 #define CONTROL_IEN_BIT 0x02
104 #define STATUS_BSY_BIT 0x80
105 #define STATUS_DRDY_BIT 0x40
106 #define STATUS_DRQ_BIT 0x08
107 #define STATUS_SEEK_BIT 0x10
108 #define STATUS_DF_BIT 0x20
109 #define DRIVE_LBA_BIT 0x40
114 typedef struct CommandReg {
128 typedef enum Events {
138 typedef enum DevAction {
149 ACT_DATA_WRITE_SHORT,
156 typedef enum DevState {
168 // PIO data-in (data to host)
173 // PIO data-out (data from host)
175 Data_Ready_INTRQ_Out,
183 typedef enum DmaState {
189 class PhysicalMemory;
193 * IDE Disk device model
195 class IdeDisk : public SimObject
198 /** The IDE controller for this disk. */
200 /** The image that contains the data of this disk. */
204 /** The disk delay in microseconds. */
208 /** Drive identification structure for this disk */
209 struct ataparams driveID;
210 /** Data buffer for transfers */
212 /** Number of bytes in command data transfer */
214 /** Number of bytes left in command data transfer */
215 uint32_t cmdBytesLeft;
216 /** Number of bytes left in DRQ block */
217 uint32_t drqBytesLeft;
218 /** Current sector in access */
220 /** Command block registers */
222 /** Status register */
224 /** Interrupt enable bit */
230 /** Dma transaction is a read */
232 /** PRD table base address */
235 PrdTableEntry curPrd;
236 /** Device ID (master=0/slave=1) */
238 /** Interrupt pending */
241 Stats::Scalar dmaReadFullPages;
242 Stats::Scalar dmaReadBytes;
243 Stats::Scalar dmaReadTxs;
244 Stats::Scalar dmaWriteFullPages;
245 Stats::Scalar dmaWriteBytes;
246 Stats::Scalar dmaWriteTxs;
247 Stats::Formula rdBandwidth;
248 Stats::Formula wrBandwidth;
249 Stats::Formula totBandwidth;
250 Stats::Formula totBytes;
253 typedef IdeDiskParams Params;
254 IdeDisk(const Params *p);
257 * Delete the data buffer.
262 * Reset the device state
267 * Register Statistics
272 * Set the controller for this device
273 * @param c The IDE controller
275 void setController(IdeController *c) {
276 if (ctrl) panic("Cannot change the controller once set!\n");
280 // Device register read/write
281 void readCommand(const Addr offset, int size, uint8_t *data);
282 void readControl(const Addr offset, int size, uint8_t *data);
283 void writeCommand(const Addr offset, int size, const uint8_t *data);
284 void writeControl(const Addr offset, int size, const uint8_t *data);
286 // Start/abort functions
287 void startDma(const uint32_t &prdTableBase);
293 // Interrupt management
298 void doDmaTransfer();
299 friend class EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer>;
300 EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer> dmaTransferEvent;
302 void doDmaDataRead();
305 ChunkGenerator *dmaReadCG;
306 friend class EventWrapper<IdeDisk, &IdeDisk::doDmaRead>;
307 EventWrapper<IdeDisk, &IdeDisk::doDmaRead> dmaReadWaitEvent;
309 void doDmaDataWrite();
312 ChunkGenerator *dmaWriteCG;
313 friend class EventWrapper<IdeDisk, &IdeDisk::doDmaWrite>;
314 EventWrapper<IdeDisk, &IdeDisk::doDmaWrite> dmaWriteWaitEvent;
316 void dmaPrdReadDone();
317 friend class EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone>;
318 EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone> dmaPrdReadEvent;
321 friend class EventWrapper<IdeDisk, &IdeDisk::dmaReadDone>;
322 EventWrapper<IdeDisk, &IdeDisk::dmaReadDone> dmaReadEvent;
325 friend class EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone>;
326 EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone> dmaWriteEvent;
328 // Disk image read/write
329 void readDisk(uint32_t sector, uint8_t *data);
330 void writeDisk(uint32_t sector, uint8_t *data);
332 // State machine management
333 void updateState(DevAction_t action);
336 bool isBSYSet() { return (status & STATUS_BSY_BIT); }
337 bool isIENSet() { return nIENBit; }
342 // clear out the status byte
345 status |= STATUS_DRDY_BIT;
347 status |= STATUS_SEEK_BIT;
350 uint32_t getLBABase()
352 return (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
353 (cmdReg.cyl_low << 8) | (cmdReg.sec_num));
356 inline Addr pciToDma(Addr pciAddr);
359 * Serialize this object to the given output stream.
360 * @param os The stream to serialize to.
362 void serialize(std::ostream &os);
365 * Reconstruct the state of this object from a checkpoint.
366 * @param cp The checkpoint to use.
367 * @param section The section name describing this object.
369 void unserialize(Checkpoint *cp, const std::string §ion);
373 #endif // __IDE_DISK_HH__