2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Andrew Schultz
32 * Device model for an IDE disk
35 #ifndef __IDE_DISK_HH__
36 #define __IDE_DISK_HH__
38 #include "base/statistics.hh"
39 #include "dev/disk_image.hh"
40 #include "dev/ide_atareg.h"
41 #include "dev/ide_ctrl.hh"
42 #include "dev/ide_wdcreg.h"
43 #include "dev/io_device.hh"
44 #include "sim/eventq.hh"
48 #define DMA_BACKOFF_PERIOD 200
50 #define MAX_DMA_SIZE (131072) // 128K
51 #define MAX_MULTSECT (128)
53 #define PRD_BASE_MASK 0xfffffffe
54 #define PRD_COUNT_MASK 0xfffe
55 #define PRD_EOT_MASK 0x8000
57 typedef struct PrdEntry {
67 uint32_t getBaseAddr()
69 return (entry.baseAddr & PRD_BASE_MASK);
72 uint32_t getByteCount()
74 return ((entry.byteCount == 0) ? MAX_DMA_SIZE :
75 (entry.byteCount & PRD_COUNT_MASK));
80 return (entry.endOfTable & PRD_EOT_MASK);
84 #define DATA_OFFSET (0)
85 #define ERROR_OFFSET (1)
86 #define FEATURES_OFFSET (1)
87 #define NSECTOR_OFFSET (2)
88 #define SECTOR_OFFSET (3)
89 #define LCYL_OFFSET (4)
90 #define HCYL_OFFSET (5)
91 #define SELECT_OFFSET (6)
92 #define DRIVE_OFFSET (6)
93 #define STATUS_OFFSET (7)
94 #define COMMAND_OFFSET (7)
96 #define CONTROL_OFFSET (2)
97 #define ALTSTAT_OFFSET (2)
99 #define SELECT_DEV_BIT 0x10
100 #define CONTROL_RST_BIT 0x04
101 #define CONTROL_IEN_BIT 0x02
102 #define STATUS_BSY_BIT 0x80
103 #define STATUS_DRDY_BIT 0x40
104 #define STATUS_DRQ_BIT 0x08
105 #define STATUS_SEEK_BIT 0x10
106 #define STATUS_DF_BIT 0x20
107 #define DRIVE_LBA_BIT 0x40
112 typedef struct CommandReg {
126 typedef enum Events {
136 typedef enum DevAction {
147 ACT_DATA_WRITE_SHORT,
154 typedef enum DevState {
166 // PIO data-in (data to host)
171 // PIO data-out (data from host)
173 Data_Ready_INTRQ_Out,
181 typedef enum DmaState {
187 class PhysicalMemory;
191 * IDE Disk device model
193 class IdeDisk : public SimObject
196 /** The IDE controller for this disk. */
198 /** The image that contains the data of this disk. */
202 /** The disk delay in microseconds. */
206 /** Drive identification structure for this disk */
207 struct ataparams driveID;
208 /** Data buffer for transfers */
210 /** Number of bytes in command data transfer */
212 /** Number of bytes left in command data transfer */
213 uint32_t cmdBytesLeft;
214 /** Number of bytes left in DRQ block */
215 uint32_t drqBytesLeft;
216 /** Current sector in access */
218 /** Command block registers */
220 /** Status register */
222 /** Interrupt enable bit */
228 /** Dma transaction is a read */
230 /** PRD table base address */
233 PrdTableEntry curPrd;
234 /** Device ID (master=0/slave=1) */
236 /** Interrupt pending */
239 Stats::Scalar<> dmaReadFullPages;
240 Stats::Scalar<> dmaReadBytes;
241 Stats::Scalar<> dmaReadTxs;
242 Stats::Scalar<> dmaWriteFullPages;
243 Stats::Scalar<> dmaWriteBytes;
244 Stats::Scalar<> dmaWriteTxs;
245 Stats::Formula rdBandwidth;
246 Stats::Formula wrBandwidth;
247 Stats::Formula totBandwidth;
248 Stats::Formula totBytes;
252 * Create and initialize this Disk.
253 * @param name The name of this disk.
254 * @param img The disk image of this disk.
255 * @param id The disk ID (master=0/slave=1)
256 * @param disk_delay The disk delay in milliseconds
258 IdeDisk(const std::string &name, DiskImage *img, int id, Tick disk_delay);
261 * Delete the data buffer.
266 * Reset the device state
271 * Register Statistics
276 * Set the controller for this device
277 * @param c The IDE controller
279 void setController(IdeController *c) {
280 if (ctrl) panic("Cannot change the controller once set!\n");
284 // Device register read/write
285 void read(const Addr &offset, IdeRegType regtype, uint8_t *data);
286 void write(const Addr &offset, IdeRegType regtype, const uint8_t *data);
288 // Start/abort functions
289 void startDma(const uint32_t &prdTableBase);
295 // Interrupt management
300 void doDmaTransfer();
301 friend class EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer>;
302 EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer> dmaTransferEvent;
304 void doDmaDataRead();
307 ChunkGenerator *dmaReadCG;
308 friend class EventWrapper<IdeDisk, &IdeDisk::doDmaRead>;
309 EventWrapper<IdeDisk, &IdeDisk::doDmaRead> dmaReadWaitEvent;
311 void doDmaDataWrite();
314 ChunkGenerator *dmaWriteCG;
315 friend class EventWrapper<IdeDisk, &IdeDisk::doDmaWrite>;
316 EventWrapper<IdeDisk, &IdeDisk::doDmaWrite> dmaWriteWaitEvent;
318 void dmaPrdReadDone();
319 friend class EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone>;
320 EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone> dmaPrdReadEvent;
323 friend class EventWrapper<IdeDisk, &IdeDisk::dmaReadDone>;
324 EventWrapper<IdeDisk, &IdeDisk::dmaReadDone> dmaReadEvent;
327 friend class EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone>;
328 EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone> dmaWriteEvent;
330 // Disk image read/write
331 void readDisk(uint32_t sector, uint8_t *data);
332 void writeDisk(uint32_t sector, uint8_t *data);
334 // State machine management
335 void updateState(DevAction_t action);
338 bool isBSYSet() { return (status & STATUS_BSY_BIT); }
339 bool isIENSet() { return nIENBit; }
344 // clear out the status byte
347 status |= STATUS_DRDY_BIT;
349 status |= STATUS_SEEK_BIT;
352 uint32_t getLBABase()
354 return (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
355 (cmdReg.cyl_low << 8) | (cmdReg.sec_num));
358 inline Addr pciToDma(Addr pciAddr);
361 * Serialize this object to the given output stream.
362 * @param os The stream to serialize to.
364 void serialize(std::ostream &os);
367 * Reconstruct the state of this object from a checkpoint.
368 * @param cp The checkpoint to use.
369 * @param section The section name describing this object.
371 void unserialize(Checkpoint *cp, const std::string §ion);
375 #endif // __IDE_DISK_HH__