src/dev/ide_disk.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Device model for an IDE disk
  31  */
  32
  33 #ifndef __IDE_DISK_HH__
  34 #define __IDE_DISK_HH__
  35
  36 #include "base/statistics.hh"
  37 #include "dev/disk_image.hh"
  38 #include "dev/ide_atareg.h"
  39 #include "dev/ide_ctrl.hh"
  40 #include "dev/ide_wdcreg.h"
  41 #include "dev/io_device.hh"
  42 #include "sim/eventq.hh"
  43
  44 #define DMA_BACKOFF_PERIOD 200
  45
  46 #define MAX_DMA_SIZE    (131072)  // 128K
  47 #define MAX_MULTSECT    (128)
  48
  49 #define PRD_BASE_MASK  0xfffffffe
  50 #define PRD_COUNT_MASK 0xfffe
  51 #define PRD_EOT_MASK   0x8000
  52
  53 typedef struct PrdEntry {
  54     uint32_t baseAddr;
  55     uint16_t byteCount;
  56     uint16_t endOfTable;
  57 } PrdEntry_t;
  58
  59 class PrdTableEntry {
  60   public:
  61     PrdEntry_t entry;
  62
  63     uint32_t getBaseAddr()
  64     {
  65         return (entry.baseAddr & PRD_BASE_MASK);
  66     }
  67
  68     uint32_t getByteCount()
  69     {
  70         return ((entry.byteCount == 0) ? MAX_DMA_SIZE :
  71                 (entry.byteCount & PRD_COUNT_MASK));
  72     }
  73
  74     uint16_t getEOT()
  75     {
  76         return (entry.endOfTable & PRD_EOT_MASK);
  77     }
  78 };
  79
  80 #define DATA_OFFSET     (0)
  81 #define ERROR_OFFSET    (1)
  82 #define FEATURES_OFFSET (1)
  83 #define NSECTOR_OFFSET  (2)
  84 #define SECTOR_OFFSET   (3)
  85 #define LCYL_OFFSET     (4)
  86 #define HCYL_OFFSET     (5)
  87 #define SELECT_OFFSET   (6)
  88 #define DRIVE_OFFSET    (6)
  89 #define STATUS_OFFSET   (7)
  90 #define COMMAND_OFFSET  (7)
  91
  92 #define CONTROL_OFFSET  (2)
  93 #define ALTSTAT_OFFSET  (2)
  94
  95 #define SELECT_DEV_BIT  0x10
  96 #define CONTROL_RST_BIT 0x04
  97 #define CONTROL_IEN_BIT 0x02
  98 #define STATUS_BSY_BIT  0x80
  99 #define STATUS_DRDY_BIT 0x40
 100 #define STATUS_DRQ_BIT  0x08
 101 #define STATUS_SEEK_BIT 0x10
 102 #define STATUS_DF_BIT   0x20
 103 #define DRIVE_LBA_BIT   0x40
 104
 105 #define DEV0 (0)
 106 #define DEV1 (1)
 107
 108 typedef struct CommandReg {
 109     uint16_t data;
 110     uint8_t error;
 111     uint8_t sec_count;
 112     uint8_t sec_num;
 113     uint8_t cyl_low;
 114     uint8_t cyl_high;
 115     union {
 116         uint8_t drive;
 117         uint8_t head;
 118     };
 119     uint8_t command;
 120 } CommandReg_t;
 121
 122 typedef enum Events {
 123     None = 0,
 124     Transfer,
 125     ReadWait,
 126     WriteWait,
 127     PrdRead,
 128     DmaRead,
 129     DmaWrite
 130 } Events_t;
 131
 132 typedef enum DevAction {
 133     ACT_NONE = 0,
 134     ACT_CMD_WRITE,
 135     ACT_CMD_COMPLETE,
 136     ACT_CMD_ERROR,
 137     ACT_SELECT_WRITE,
 138     ACT_STAT_READ,
 139     ACT_DATA_READY,
 140     ACT_DATA_READ_BYTE,
 141     ACT_DATA_READ_SHORT,
 142     ACT_DATA_WRITE_BYTE,
 143     ACT_DATA_WRITE_SHORT,
 144     ACT_DMA_READY,
 145     ACT_DMA_DONE,
 146     ACT_SRST_SET,
 147     ACT_SRST_CLEAR
 148 } DevAction_t;
 149
 150 typedef enum DevState {
 151     // Device idle
 152     Device_Idle_S = 0,
 153     Device_Idle_SI,
 154     Device_Idle_NS,
 155
 156     // Software reset
 157     Device_Srst,
 158
 159     // Non-data commands
 160     Command_Execution,
 161
 162     // PIO data-in (data to host)
 163     Prepare_Data_In,
 164     Data_Ready_INTRQ_In,
 165     Transfer_Data_In,
 166
 167     // PIO data-out (data from host)
 168     Prepare_Data_Out,
 169     Data_Ready_INTRQ_Out,
 170     Transfer_Data_Out,
 171
 172     // DMA protocol
 173     Prepare_Data_Dma,
 174     Transfer_Data_Dma
 175 } DevState_t;
 176
 177 typedef enum DmaState {
 178     Dma_Idle = 0,
 179     Dma_Start,
 180     Dma_Transfer
 181 } DmaState_t;
 182
 183 class PhysicalMemory;
 184 class IdeController;
 185
 186 /**
 187  * IDE Disk device model
 188  */
 189 class IdeDisk : public SimObject
 190 {
 191   protected:
 192     /** The IDE controller for this disk. */
 193     IdeController *ctrl;
 194     /** The image that contains the data of this disk. */
 195     DiskImage *image;
 196
 197   protected:
 198     /** The disk delay in microseconds. */
 199     int diskDelay;
 200
 201   private:
 202     /** Drive identification structure for this disk */
 203     struct ataparams driveID;
 204     /** Data buffer for transfers */
 205     uint8_t *dataBuffer;
 206     /** Number of bytes in command data transfer */
 207     uint32_t cmdBytes;
 208     /** Number of bytes left in command data transfer */
 209     uint32_t cmdBytesLeft;
 210     /** Number of bytes left in DRQ block */
 211     uint32_t drqBytesLeft;
 212     /** Current sector in access */
 213     uint32_t curSector;
 214     /** Command block registers */
 215     CommandReg_t cmdReg;
 216     /** Status register */
 217     uint8_t status;
 218     /** Interrupt enable bit */
 219     bool nIENBit;
 220     /** Device state */
 221     DevState_t devState;
 222     /** Dma state */
 223     DmaState_t dmaState;
 224     /** Dma transaction is a read */
 225     bool dmaRead;
 226     /** PRD table base address */
 227     uint32_t curPrdAddr;
 228     /** PRD entry */
 229     PrdTableEntry curPrd;
 230     /** Device ID (master=0/slave=1) */
 231     int devID;
 232     /** Interrupt pending */
 233     bool intrPending;
 234
 235     Stats::Scalar<> dmaReadFullPages;
 236     Stats::Scalar<> dmaReadBytes;
 237     Stats::Scalar<> dmaReadTxs;
 238     Stats::Scalar<> dmaWriteFullPages;
 239     Stats::Scalar<> dmaWriteBytes;
 240     Stats::Scalar<> dmaWriteTxs;
 241
 242   public:
 243     /**
 244      * Create and initialize this Disk.
 245      * @param name The name of this disk.
 246      * @param img The disk image of this disk.
 247      * @param id The disk ID (master=0/slave=1)
 248      * @param disk_delay The disk delay in milliseconds
 249      */
 250     IdeDisk(const std::string &name, DiskImage *img, int id, Tick disk_delay);
 251
 252     /**
 253      * Delete the data buffer.
 254      */
 255     ~IdeDisk();
 256
 257     /**
 258      * Reset the device state
 259      */
 260     void reset(int id);
 261
 262     /**
 263      * Register Statistics
 264      */
 265     void regStats();
 266
 267     /**
 268      * Set the controller for this device
 269      * @param c The IDE controller
 270      */
 271     void setController(IdeController *c) {
 272         if (ctrl) panic("Cannot change the controller once set!\n");
 273         ctrl = c;
 274     }
 275
 276     // Device register read/write
 277     void read(const Addr &offset, IdeRegType regtype, uint8_t *data);
 278     void write(const Addr &offset, IdeRegType regtype, const uint8_t *data);
 279
 280     // Start/abort functions
 281     void startDma(const uint32_t &prdTableBase);
 282     void abortDma();
 283
 284   private:
 285     void startCommand();
 286
 287     // Interrupt management
 288     void intrPost();
 289     void intrClear();
 290
 291     // DMA stuff
 292     void doDmaTransfer();
 293     friend class EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer>;
 294     EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer> dmaTransferEvent;
 295
 296     void doDmaDataRead();
 297
 298     void doDmaRead();
 299     ChunkGenerator *dmaReadCG;
 300     friend class EventWrapper<IdeDisk, &IdeDisk::doDmaRead>;
 301     EventWrapper<IdeDisk, &IdeDisk::doDmaRead> dmaReadWaitEvent;
 302
 303     void doDmaDataWrite();
 304
 305     void doDmaWrite();
 306     ChunkGenerator *dmaWriteCG;
 307     friend class EventWrapper<IdeDisk, &IdeDisk::doDmaWrite>;
 308     EventWrapper<IdeDisk, &IdeDisk::doDmaWrite> dmaWriteWaitEvent;
 309
 310     void dmaPrdReadDone();
 311     friend class EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone>;
 312     EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone> dmaPrdReadEvent;
 313
 314     void dmaReadDone();
 315     friend class EventWrapper<IdeDisk, &IdeDisk::dmaReadDone>;
 316     EventWrapper<IdeDisk, &IdeDisk::dmaReadDone> dmaReadEvent;
 317
 318     void dmaWriteDone();
 319     friend class EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone>;
 320     EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone> dmaWriteEvent;
 321
 322     // Disk image read/write
 323     void readDisk(uint32_t sector, uint8_t *data);
 324     void writeDisk(uint32_t sector, uint8_t *data);
 325
 326     // State machine management
 327     void updateState(DevAction_t action);
 328
 329     // Utility functions
 330     bool isBSYSet() { return (status & STATUS_BSY_BIT); }
 331     bool isIENSet() { return nIENBit; }
 332     bool isDEVSelect();
 333
 334     void setComplete()
 335     {
 336         // clear out the status byte
 337         status = 0;
 338         // set the DRDY bit
 339         status |= STATUS_DRDY_BIT;
 340         // set the SEEK bit
 341         status |= STATUS_SEEK_BIT;
 342     }
 343
 344     uint32_t getLBABase()
 345     {
 346         return  (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
 347                        (cmdReg.cyl_low << 8) | (cmdReg.sec_num));
 348     }
 349
 350     inline Addr pciToDma(Addr pciAddr);
 351
 352     /**
 353      * Serialize this object to the given output stream.
 354      * @param os The stream to serialize to.
 355      */
 356     void serialize(std::ostream &os);
 357
 358     /**
 359      * Reconstruct the state of this object from a checkpoint.
 360      * @param cp The checkpoint to use.
 361      * @param section The section name describing this object.
 362      */
 363     void unserialize(Checkpoint *cp, const std::string &section);
 364 };
 365
 366
 367 #endif // __IDE_DISK_HH__