src/dev/ide_disk.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Andrew Schultz
  29  */
  30
  31 /** @file
  32  * Device model for an IDE disk
  33  */
  34
  35 #ifndef __IDE_DISK_HH__
  36 #define __IDE_DISK_HH__
  37
  38 #include "base/statistics.hh"
  39 #include "dev/disk_image.hh"
  40 #include "dev/ide_atareg.h"
  41 #include "dev/ide_ctrl.hh"
  42 #include "dev/ide_wdcreg.h"
  43 #include "dev/io_device.hh"
  44 #include "params/IdeDisk.hh"
  45 #include "sim/eventq.hh"
  46
  47 class ChunkGenerator;
  48
  49 #define DMA_BACKOFF_PERIOD      200
  50
  51 #define MAX_DMA_SIZE            0x20000  // 128K
  52 #define MAX_SINGLE_DMA_SIZE     0x10000
  53 #define MAX_MULTSECT            (128)
  54
  55 #define PRD_BASE_MASK  0xfffffffe
  56 #define PRD_COUNT_MASK 0xfffe
  57 #define PRD_EOT_MASK   0x8000
  58
  59 typedef struct PrdEntry {
  60     uint32_t baseAddr;
  61     uint16_t byteCount;
  62     uint16_t endOfTable;
  63 } PrdEntry_t;
  64
  65 class PrdTableEntry {
  66   public:
  67     PrdEntry_t entry;
  68
  69     uint32_t getBaseAddr()
  70     {
  71         return (entry.baseAddr & PRD_BASE_MASK);
  72     }
  73
  74     uint32_t getByteCount()
  75     {
  76         return ((entry.byteCount == 0) ? MAX_SINGLE_DMA_SIZE :
  77                 (entry.byteCount & PRD_COUNT_MASK));
  78     }
  79
  80     uint16_t getEOT()
  81     {
  82         return (entry.endOfTable & PRD_EOT_MASK);
  83     }
  84 };
  85
  86 #define DATA_OFFSET     (0)
  87 #define ERROR_OFFSET    (1)
  88 #define FEATURES_OFFSET (1)
  89 #define NSECTOR_OFFSET  (2)
  90 #define SECTOR_OFFSET   (3)
  91 #define LCYL_OFFSET     (4)
  92 #define HCYL_OFFSET     (5)
  93 #define SELECT_OFFSET   (6)
  94 #define DRIVE_OFFSET    (6)
  95 #define STATUS_OFFSET   (7)
  96 #define COMMAND_OFFSET  (7)
  97
  98 #define CONTROL_OFFSET  (2)
  99 #define ALTSTAT_OFFSET  (2)
 100
 101 #define SELECT_DEV_BIT  0x10
 102 #define CONTROL_RST_BIT 0x04
 103 #define CONTROL_IEN_BIT 0x02
 104 #define STATUS_BSY_BIT  0x80
 105 #define STATUS_DRDY_BIT 0x40
 106 #define STATUS_DRQ_BIT  0x08
 107 #define STATUS_SEEK_BIT 0x10
 108 #define STATUS_DF_BIT   0x20
 109 #define DRIVE_LBA_BIT   0x40
 110
 111 #define DEV0 (0)
 112 #define DEV1 (1)
 113
 114 typedef struct CommandReg {
 115     uint16_t data;
 116     uint8_t error;
 117     uint8_t sec_count;
 118     uint8_t sec_num;
 119     uint8_t cyl_low;
 120     uint8_t cyl_high;
 121     union {
 122         uint8_t drive;
 123         uint8_t head;
 124     };
 125     uint8_t command;
 126 } CommandReg_t;
 127
 128 typedef enum Events {
 129     None = 0,
 130     Transfer,
 131     ReadWait,
 132     WriteWait,
 133     PrdRead,
 134     DmaRead,
 135     DmaWrite
 136 } Events_t;
 137
 138 typedef enum DevAction {
 139     ACT_NONE = 0,
 140     ACT_CMD_WRITE,
 141     ACT_CMD_COMPLETE,
 142     ACT_CMD_ERROR,
 143     ACT_SELECT_WRITE,
 144     ACT_STAT_READ,
 145     ACT_DATA_READY,
 146     ACT_DATA_READ_BYTE,
 147     ACT_DATA_READ_SHORT,
 148     ACT_DATA_WRITE_BYTE,
 149     ACT_DATA_WRITE_SHORT,
 150     ACT_DMA_READY,
 151     ACT_DMA_DONE,
 152     ACT_SRST_SET,
 153     ACT_SRST_CLEAR
 154 } DevAction_t;
 155
 156 typedef enum DevState {
 157     // Device idle
 158     Device_Idle_S = 0,
 159     Device_Idle_SI,
 160     Device_Idle_NS,
 161
 162     // Software reset
 163     Device_Srst,
 164
 165     // Non-data commands
 166     Command_Execution,
 167
 168     // PIO data-in (data to host)
 169     Prepare_Data_In,
 170     Data_Ready_INTRQ_In,
 171     Transfer_Data_In,
 172
 173     // PIO data-out (data from host)
 174     Prepare_Data_Out,
 175     Data_Ready_INTRQ_Out,
 176     Transfer_Data_Out,
 177
 178     // DMA protocol
 179     Prepare_Data_Dma,
 180     Transfer_Data_Dma
 181 } DevState_t;
 182
 183 typedef enum DmaState {
 184     Dma_Idle = 0,
 185     Dma_Start,
 186     Dma_Transfer
 187 } DmaState_t;
 188
 189 class IdeController;
 190
 191 /**
 192  * IDE Disk device model
 193  */
 194 class IdeDisk : public SimObject
 195 {
 196   protected:
 197     /** The IDE controller for this disk. */
 198     IdeController *ctrl;
 199     /** The image that contains the data of this disk. */
 200     DiskImage *image;
 201
 202   protected:
 203     /** The disk delay in microseconds. */
 204     int diskDelay;
 205
 206   private:
 207     /** Drive identification structure for this disk */
 208     struct ataparams driveID;
 209     /** Data buffer for transfers */
 210     uint8_t *dataBuffer;
 211     /** Number of bytes in command data transfer */
 212     uint32_t cmdBytes;
 213     /** Number of bytes left in command data transfer */
 214     uint32_t cmdBytesLeft;
 215     /** Number of bytes left in DRQ block */
 216     uint32_t drqBytesLeft;
 217     /** Current sector in access */
 218     uint32_t curSector;
 219     /** Command block registers */
 220     CommandReg_t cmdReg;
 221     /** Status register */
 222     uint8_t status;
 223     /** Interrupt enable bit */
 224     bool nIENBit;
 225     /** Device state */
 226     DevState_t devState;
 227     /** Dma state */
 228     DmaState_t dmaState;
 229     /** Dma transaction is a read */
 230     bool dmaRead;
 231     /** PRD table base address */
 232     uint32_t curPrdAddr;
 233     /** PRD entry */
 234     PrdTableEntry curPrd;
 235     /** Device ID (master=0/slave=1) */
 236     int devID;
 237     /** Interrupt pending */
 238     bool intrPending;
 239
 240     Stats::Scalar dmaReadFullPages;
 241     Stats::Scalar dmaReadBytes;
 242     Stats::Scalar dmaReadTxs;
 243     Stats::Scalar dmaWriteFullPages;
 244     Stats::Scalar dmaWriteBytes;
 245     Stats::Scalar dmaWriteTxs;
 246
 247   public:
 248     typedef IdeDiskParams Params;
 249     IdeDisk(const Params *p);
 250
 251     /**
 252      * Delete the data buffer.
 253      */
 254     ~IdeDisk();
 255
 256     /**
 257      * Reset the device state
 258      */
 259     void reset(int id);
 260
 261     /**
 262      * Register Statistics
 263      */
 264     void regStats();
 265
 266     /**
 267      * Set the controller for this device
 268      * @param c The IDE controller
 269      */
 270     void setController(IdeController *c) {
 271         if (ctrl) panic("Cannot change the controller once set!\n");
 272         ctrl = c;
 273     }
 274
 275     // Device register read/write
 276     void readCommand(const Addr offset, int size, uint8_t *data);
 277     void readControl(const Addr offset, int size, uint8_t *data);
 278     void writeCommand(const Addr offset, int size, const uint8_t *data);
 279     void writeControl(const Addr offset, int size, const uint8_t *data);
 280
 281     // Start/abort functions
 282     void startDma(const uint32_t &prdTableBase);
 283     void abortDma();
 284
 285   private:
 286     void startCommand();
 287
 288     // Interrupt management
 289     void intrPost();
 290     void intrClear();
 291
 292     // DMA stuff
 293     void doDmaTransfer();
 294     friend class EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer>;
 295     EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer> dmaTransferEvent;
 296
 297     void doDmaDataRead();
 298
 299     void doDmaRead();
 300     ChunkGenerator *dmaReadCG;
 301     friend class EventWrapper<IdeDisk, &IdeDisk::doDmaRead>;
 302     EventWrapper<IdeDisk, &IdeDisk::doDmaRead> dmaReadWaitEvent;
 303
 304     void doDmaDataWrite();
 305
 306     void doDmaWrite();
 307     ChunkGenerator *dmaWriteCG;
 308     friend class EventWrapper<IdeDisk, &IdeDisk::doDmaWrite>;
 309     EventWrapper<IdeDisk, &IdeDisk::doDmaWrite> dmaWriteWaitEvent;
 310
 311     void dmaPrdReadDone();
 312     friend class EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone>;
 313     EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone> dmaPrdReadEvent;
 314
 315     void dmaReadDone();
 316     friend class EventWrapper<IdeDisk, &IdeDisk::dmaReadDone>;
 317     EventWrapper<IdeDisk, &IdeDisk::dmaReadDone> dmaReadEvent;
 318
 319     void dmaWriteDone();
 320     friend class EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone>;
 321     EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone> dmaWriteEvent;
 322
 323     // Disk image read/write
 324     void readDisk(uint32_t sector, uint8_t *data);
 325     void writeDisk(uint32_t sector, uint8_t *data);
 326
 327     // State machine management
 328     void updateState(DevAction_t action);
 329
 330     // Utility functions
 331     bool isBSYSet() { return (status & STATUS_BSY_BIT); }
 332     bool isIENSet() { return nIENBit; }
 333     bool isDEVSelect();
 334
 335     void setComplete()
 336     {
 337         // clear out the status byte
 338         status = 0;
 339         // set the DRDY bit
 340         status |= STATUS_DRDY_BIT;
 341         // set the SEEK bit
 342         status |= STATUS_SEEK_BIT;
 343     }
 344
 345     uint32_t getLBABase()
 346     {
 347         return  (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
 348                        (cmdReg.cyl_low << 8) | (cmdReg.sec_num));
 349     }
 350
 351     inline Addr pciToDma(Addr pciAddr);
 352
 353     /**
 354      * Serialize this object to the given output stream.
 355      * @param os The stream to serialize to.
 356      */
 357     void serialize(std::ostream &os);
 358
 359     /**
 360      * Reconstruct the state of this object from a checkpoint.
 361      * @param cp The checkpoint to use.
 362      * @param section The section name describing this object.
 363      */
 364     void unserialize(Checkpoint *cp, const std::string &section);
 365 };
 366
 367
 368 #endif // __IDE_DISK_HH__