src/dev/ide_disk.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Andrew Schultz
  29  */
  30
  31 /** @file
  32  * Device model for an IDE disk
  33  */
  34
  35 #ifndef __IDE_DISK_HH__
  36 #define __IDE_DISK_HH__
  37
  38 #include "base/statistics.hh"
  39 #include "dev/disk_image.hh"
  40 #include "dev/ide_atareg.h"
  41 #include "dev/ide_ctrl.hh"
  42 #include "dev/ide_wdcreg.h"
  43 #include "dev/io_device.hh"
  44 #include "sim/eventq.hh"
  45
  46 #define DMA_BACKOFF_PERIOD 200
  47
  48 #define MAX_DMA_SIZE    (131072)  // 128K
  49 #define MAX_MULTSECT    (128)
  50
  51 #define PRD_BASE_MASK  0xfffffffe
  52 #define PRD_COUNT_MASK 0xfffe
  53 #define PRD_EOT_MASK   0x8000
  54
  55 typedef struct PrdEntry {
  56     uint32_t baseAddr;
  57     uint16_t byteCount;
  58     uint16_t endOfTable;
  59 } PrdEntry_t;
  60
  61 class PrdTableEntry {
  62   public:
  63     PrdEntry_t entry;
  64
  65     uint32_t getBaseAddr()
  66     {
  67         return (entry.baseAddr & PRD_BASE_MASK);
  68     }
  69
  70     uint32_t getByteCount()
  71     {
  72         return ((entry.byteCount == 0) ? MAX_DMA_SIZE :
  73                 (entry.byteCount & PRD_COUNT_MASK));
  74     }
  75
  76     uint16_t getEOT()
  77     {
  78         return (entry.endOfTable & PRD_EOT_MASK);
  79     }
  80 };
  81
  82 #define DATA_OFFSET     (0)
  83 #define ERROR_OFFSET    (1)
  84 #define FEATURES_OFFSET (1)
  85 #define NSECTOR_OFFSET  (2)
  86 #define SECTOR_OFFSET   (3)
  87 #define LCYL_OFFSET     (4)
  88 #define HCYL_OFFSET     (5)
  89 #define SELECT_OFFSET   (6)
  90 #define DRIVE_OFFSET    (6)
  91 #define STATUS_OFFSET   (7)
  92 #define COMMAND_OFFSET  (7)
  93
  94 #define CONTROL_OFFSET  (2)
  95 #define ALTSTAT_OFFSET  (2)
  96
  97 #define SELECT_DEV_BIT  0x10
  98 #define CONTROL_RST_BIT 0x04
  99 #define CONTROL_IEN_BIT 0x02
 100 #define STATUS_BSY_BIT  0x80
 101 #define STATUS_DRDY_BIT 0x40
 102 #define STATUS_DRQ_BIT  0x08
 103 #define STATUS_SEEK_BIT 0x10
 104 #define STATUS_DF_BIT   0x20
 105 #define DRIVE_LBA_BIT   0x40
 106
 107 #define DEV0 (0)
 108 #define DEV1 (1)
 109
 110 typedef struct CommandReg {
 111     uint16_t data;
 112     uint8_t error;
 113     uint8_t sec_count;
 114     uint8_t sec_num;
 115     uint8_t cyl_low;
 116     uint8_t cyl_high;
 117     union {
 118         uint8_t drive;
 119         uint8_t head;
 120     };
 121     uint8_t command;
 122 } CommandReg_t;
 123
 124 typedef enum Events {
 125     None = 0,
 126     Transfer,
 127     ReadWait,
 128     WriteWait,
 129     PrdRead,
 130     DmaRead,
 131     DmaWrite
 132 } Events_t;
 133
 134 typedef enum DevAction {
 135     ACT_NONE = 0,
 136     ACT_CMD_WRITE,
 137     ACT_CMD_COMPLETE,
 138     ACT_CMD_ERROR,
 139     ACT_SELECT_WRITE,
 140     ACT_STAT_READ,
 141     ACT_DATA_READY,
 142     ACT_DATA_READ_BYTE,
 143     ACT_DATA_READ_SHORT,
 144     ACT_DATA_WRITE_BYTE,
 145     ACT_DATA_WRITE_SHORT,
 146     ACT_DMA_READY,
 147     ACT_DMA_DONE,
 148     ACT_SRST_SET,
 149     ACT_SRST_CLEAR
 150 } DevAction_t;
 151
 152 typedef enum DevState {
 153     // Device idle
 154     Device_Idle_S = 0,
 155     Device_Idle_SI,
 156     Device_Idle_NS,
 157
 158     // Software reset
 159     Device_Srst,
 160
 161     // Non-data commands
 162     Command_Execution,
 163
 164     // PIO data-in (data to host)
 165     Prepare_Data_In,
 166     Data_Ready_INTRQ_In,
 167     Transfer_Data_In,
 168
 169     // PIO data-out (data from host)
 170     Prepare_Data_Out,
 171     Data_Ready_INTRQ_Out,
 172     Transfer_Data_Out,
 173
 174     // DMA protocol
 175     Prepare_Data_Dma,
 176     Transfer_Data_Dma
 177 } DevState_t;
 178
 179 typedef enum DmaState {
 180     Dma_Idle = 0,
 181     Dma_Start,
 182     Dma_Transfer
 183 } DmaState_t;
 184
 185 class PhysicalMemory;
 186 class IdeController;
 187
 188 /**
 189  * IDE Disk device model
 190  */
 191 class IdeDisk : public SimObject
 192 {
 193   protected:
 194     /** The IDE controller for this disk. */
 195     IdeController *ctrl;
 196     /** The image that contains the data of this disk. */
 197     DiskImage *image;
 198
 199   protected:
 200     /** The disk delay in microseconds. */
 201     int diskDelay;
 202
 203   private:
 204     /** Drive identification structure for this disk */
 205     struct ataparams driveID;
 206     /** Data buffer for transfers */
 207     uint8_t *dataBuffer;
 208     /** Number of bytes in command data transfer */
 209     uint32_t cmdBytes;
 210     /** Number of bytes left in command data transfer */
 211     uint32_t cmdBytesLeft;
 212     /** Number of bytes left in DRQ block */
 213     uint32_t drqBytesLeft;
 214     /** Current sector in access */
 215     uint32_t curSector;
 216     /** Command block registers */
 217     CommandReg_t cmdReg;
 218     /** Status register */
 219     uint8_t status;
 220     /** Interrupt enable bit */
 221     bool nIENBit;
 222     /** Device state */
 223     DevState_t devState;
 224     /** Dma state */
 225     DmaState_t dmaState;
 226     /** Dma transaction is a read */
 227     bool dmaRead;
 228     /** PRD table base address */
 229     uint32_t curPrdAddr;
 230     /** PRD entry */
 231     PrdTableEntry curPrd;
 232     /** Device ID (master=0/slave=1) */
 233     int devID;
 234     /** Interrupt pending */
 235     bool intrPending;
 236
 237     Stats::Scalar<> dmaReadFullPages;
 238     Stats::Scalar<> dmaReadBytes;
 239     Stats::Scalar<> dmaReadTxs;
 240     Stats::Scalar<> dmaWriteFullPages;
 241     Stats::Scalar<> dmaWriteBytes;
 242     Stats::Scalar<> dmaWriteTxs;
 243
 244   public:
 245     /**
 246      * Create and initialize this Disk.
 247      * @param name The name of this disk.
 248      * @param img The disk image of this disk.
 249      * @param id The disk ID (master=0/slave=1)
 250      * @param disk_delay The disk delay in milliseconds
 251      */
 252     IdeDisk(const std::string &name, DiskImage *img, int id, Tick disk_delay);
 253
 254     /**
 255      * Delete the data buffer.
 256      */
 257     ~IdeDisk();
 258
 259     /**
 260      * Reset the device state
 261      */
 262     void reset(int id);
 263
 264     /**
 265      * Register Statistics
 266      */
 267     void regStats();
 268
 269     /**
 270      * Set the controller for this device
 271      * @param c The IDE controller
 272      */
 273     void setController(IdeController *c) {
 274         if (ctrl) panic("Cannot change the controller once set!\n");
 275         ctrl = c;
 276     }
 277
 278     // Device register read/write
 279     void read(const Addr &offset, IdeRegType regtype, uint8_t *data);
 280     void write(const Addr &offset, IdeRegType regtype, const uint8_t *data);
 281
 282     // Start/abort functions
 283     void startDma(const uint32_t &prdTableBase);
 284     void abortDma();
 285
 286   private:
 287     void startCommand();
 288
 289     // Interrupt management
 290     void intrPost();
 291     void intrClear();
 292
 293     // DMA stuff
 294     void doDmaTransfer();
 295     friend class EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer>;
 296     EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer> dmaTransferEvent;
 297
 298     void doDmaDataRead();
 299
 300     void doDmaRead();
 301     ChunkGenerator *dmaReadCG;
 302     friend class EventWrapper<IdeDisk, &IdeDisk::doDmaRead>;
 303     EventWrapper<IdeDisk, &IdeDisk::doDmaRead> dmaReadWaitEvent;
 304
 305     void doDmaDataWrite();
 306
 307     void doDmaWrite();
 308     ChunkGenerator *dmaWriteCG;
 309     friend class EventWrapper<IdeDisk, &IdeDisk::doDmaWrite>;
 310     EventWrapper<IdeDisk, &IdeDisk::doDmaWrite> dmaWriteWaitEvent;
 311
 312     void dmaPrdReadDone();
 313     friend class EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone>;
 314     EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone> dmaPrdReadEvent;
 315
 316     void dmaReadDone();
 317     friend class EventWrapper<IdeDisk, &IdeDisk::dmaReadDone>;
 318     EventWrapper<IdeDisk, &IdeDisk::dmaReadDone> dmaReadEvent;
 319
 320     void dmaWriteDone();
 321     friend class EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone>;
 322     EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone> dmaWriteEvent;
 323
 324     // Disk image read/write
 325     void readDisk(uint32_t sector, uint8_t *data);
 326     void writeDisk(uint32_t sector, uint8_t *data);
 327
 328     // State machine management
 329     void updateState(DevAction_t action);
 330
 331     // Utility functions
 332     bool isBSYSet() { return (status & STATUS_BSY_BIT); }
 333     bool isIENSet() { return nIENBit; }
 334     bool isDEVSelect();
 335
 336     void setComplete()
 337     {
 338         // clear out the status byte
 339         status = 0;
 340         // set the DRDY bit
 341         status |= STATUS_DRDY_BIT;
 342         // set the SEEK bit
 343         status |= STATUS_SEEK_BIT;
 344     }
 345
 346     uint32_t getLBABase()
 347     {
 348         return  (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
 349                        (cmdReg.cyl_low << 8) | (cmdReg.sec_num));
 350     }
 351
 352     inline Addr pciToDma(Addr pciAddr);
 353
 354     /**
 355      * Serialize this object to the given output stream.
 356      * @param os The stream to serialize to.
 357      */
 358     void serialize(std::ostream &os);
 359
 360     /**
 361      * Reconstruct the state of this object from a checkpoint.
 362      * @param cp The checkpoint to use.
 363      * @param section The section name describing this object.
 364      */
 365     void unserialize(Checkpoint *cp, const std::string &section);
 366 };
 367
 368
 369 #endif // __IDE_DISK_HH__