src/dev/isa_fake.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Isa Fake Device implementation
  31  */
  32
  33 #include "dev/isa_fake.hh"
  34
  35 #include "base/trace.hh"
  36 #include "debug/IsaFake.hh"
  37 #include "mem/packet.hh"
  38 #include "mem/packet_access.hh"
  39 #include "sim/system.hh"
  40
  41 IsaFake::IsaFake(const Params &p)
  42     : BasicPioDevice(p, p.ret_bad_addr ? 0 : p.pio_size)
  43 {
  44     retData8 = p.ret_data8;
  45     retData16 = p.ret_data16;
  46     retData32 = p.ret_data32;
  47     retData64 = p.ret_data64;
  48 }
  49
  50 Tick
  51 IsaFake::read(PacketPtr pkt)
  52 {
  53     pkt->makeAtomicResponse();
  54
  55     if (params().warn_access != "")
  56         warn("Device %s accessed by read to address %#x size=%d\n",
  57                 name(), pkt->getAddr(), pkt->getSize());
  58     if (params().ret_bad_addr) {
  59         DPRINTF(IsaFake, "read to bad address va=%#x size=%d\n",
  60                 pkt->getAddr(), pkt->getSize());
  61         pkt->setBadAddress();
  62     } else {
  63         assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
  64         DPRINTF(IsaFake, "read  va=%#x size=%d\n",
  65                 pkt->getAddr(), pkt->getSize());
  66         switch (pkt->getSize()) {
  67           case sizeof(uint64_t):
  68              pkt->setLE(retData64);
  69              break;
  70           case sizeof(uint32_t):
  71              pkt->setLE(retData32);
  72              break;
  73           case sizeof(uint16_t):
  74              pkt->setLE(retData16);
  75              break;
  76           case sizeof(uint8_t):
  77              pkt->setLE(retData8);
  78              break;
  79           default:
  80              if (params().fake_mem)
  81                  std::memset(pkt->getPtr<uint8_t>(), 0, pkt->getSize());
  82              else
  83                  panic("invalid access size! Device being accessed by cache?\n");
  84         }
  85     }
  86     return pioDelay;
  87 }
  88
  89 Tick
  90 IsaFake::write(PacketPtr pkt)
  91 {
  92     pkt->makeAtomicResponse();
  93     if (params().warn_access != "") {
  94         uint64_t data;
  95         switch (pkt->getSize()) {
  96           case sizeof(uint64_t):
  97             data = pkt->getLE<uint64_t>();
  98             break;
  99           case sizeof(uint32_t):
 100             data = pkt->getLE<uint32_t>();
 101             break;
 102           case sizeof(uint16_t):
 103             data = pkt->getLE<uint16_t>();
 104             break;
 105           case sizeof(uint8_t):
 106             data = pkt->getLE<uint8_t>();
 107             break;
 108           default:
 109             panic("invalid access size: %u\n", pkt->getSize());
 110         }
 111         warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
 112                 name(), pkt->getAddr(), pkt->getSize(), data);
 113     }
 114     if (params().ret_bad_addr) {
 115         DPRINTF(IsaFake, "write to bad address va=%#x size=%d \n",
 116                 pkt->getAddr(), pkt->getSize());
 117         pkt->setBadAddress();
 118     } else {
 119         DPRINTF(IsaFake, "write - va=%#x size=%d \n",
 120                 pkt->getAddr(), pkt->getSize());
 121
 122         if (params().update_data) {
 123             switch (pkt->getSize()) {
 124               case sizeof(uint64_t):
 125                 retData64 = pkt->getLE<uint64_t>();
 126                 break;
 127               case sizeof(uint32_t):
 128                 retData32 = pkt->getLE<uint32_t>();
 129                 break;
 130               case sizeof(uint16_t):
 131                 retData16 = pkt->getLE<uint16_t>();
 132                 break;
 133               case sizeof(uint8_t):
 134                 retData8 = pkt->getLE<uint8_t>();
 135                 break;
 136               default:
 137                 panic("invalid access size!\n");
 138             }
 139         }
 140     }
 141     return pioDelay;
 142 }