src/dev/isa_fake.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Isa Fake Device implementation
  31  */
  32
  33 #include "dev/isa_fake.hh"
  34
  35 #include "base/trace.hh"
  36 #include "debug/IsaFake.hh"
  37 #include "mem/packet.hh"
  38 #include "mem/packet_access.hh"
  39 #include "sim/system.hh"
  40
  41 using namespace std;
  42
  43 IsaFake::IsaFake(Params *p)
  44     : BasicPioDevice(p, p->ret_bad_addr ? 0 : p->pio_size)
  45 {
  46     retData8 = p->ret_data8;
  47     retData16 = p->ret_data16;
  48     retData32 = p->ret_data32;
  49     retData64 = p->ret_data64;
  50 }
  51
  52 Tick
  53 IsaFake::read(PacketPtr pkt)
  54 {
  55     pkt->makeAtomicResponse();
  56
  57     if (params()->warn_access != "")
  58         warn("Device %s accessed by read to address %#x size=%d\n",
  59                 name(), pkt->getAddr(), pkt->getSize());
  60     if (params()->ret_bad_addr) {
  61         DPRINTF(IsaFake, "read to bad address va=%#x size=%d\n",
  62                 pkt->getAddr(), pkt->getSize());
  63         pkt->setBadAddress();
  64     } else {
  65         assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
  66         DPRINTF(IsaFake, "read  va=%#x size=%d\n",
  67                 pkt->getAddr(), pkt->getSize());
  68         switch (pkt->getSize()) {
  69           case sizeof(uint64_t):
  70              pkt->setLE(retData64);
  71              break;
  72           case sizeof(uint32_t):
  73              pkt->setLE(retData32);
  74              break;
  75           case sizeof(uint16_t):
  76              pkt->setLE(retData16);
  77              break;
  78           case sizeof(uint8_t):
  79              pkt->setLE(retData8);
  80              break;
  81           default:
  82              if (params()->fake_mem)
  83                  std::memset(pkt->getPtr<uint8_t>(), 0, pkt->getSize());
  84              else
  85                  panic("invalid access size! Device being accessed by cache?\n");
  86         }
  87     }
  88     return pioDelay;
  89 }
  90
  91 Tick
  92 IsaFake::write(PacketPtr pkt)
  93 {
  94     pkt->makeAtomicResponse();
  95     if (params()->warn_access != "") {
  96         uint64_t data;
  97         switch (pkt->getSize()) {
  98           case sizeof(uint64_t):
  99             data = pkt->getLE<uint64_t>();
 100             break;
 101           case sizeof(uint32_t):
 102             data = pkt->getLE<uint32_t>();
 103             break;
 104           case sizeof(uint16_t):
 105             data = pkt->getLE<uint16_t>();
 106             break;
 107           case sizeof(uint8_t):
 108             data = pkt->getLE<uint8_t>();
 109             break;
 110           default:
 111             panic("invalid access size: %u\n", pkt->getSize());
 112         }
 113         warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
 114                 name(), pkt->getAddr(), pkt->getSize(), data);
 115     }
 116     if (params()->ret_bad_addr) {
 117         DPRINTF(IsaFake, "write to bad address va=%#x size=%d \n",
 118                 pkt->getAddr(), pkt->getSize());
 119         pkt->setBadAddress();
 120     } else {
 121         DPRINTF(IsaFake, "write - va=%#x size=%d \n",
 122                 pkt->getAddr(), pkt->getSize());
 123
 124         if (params()->update_data) {
 125             switch (pkt->getSize()) {
 126               case sizeof(uint64_t):
 127                 retData64 = pkt->getLE<uint64_t>();
 128                 break;
 129               case sizeof(uint32_t):
 130                 retData32 = pkt->getLE<uint32_t>();
 131                 break;
 132               case sizeof(uint16_t):
 133                 retData16 = pkt->getLE<uint16_t>();
 134                 break;
 135               case sizeof(uint8_t):
 136                 retData8 = pkt->getLE<uint8_t>();
 137                 break;
 138               default:
 139                 panic("invalid access size!\n");
 140             }
 141         }
 142     }
 143     return pioDelay;
 144 }
 145
 146 IsaFake *
 147 IsaFakeParams::create()
 148 {
 149     return new IsaFake(this);
 150 }