2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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33 * Emulation of the Malta CChip CSRs
36 #include "dev/mips/malta_cchip.hh"
42 #include "base/trace.hh"
43 #include "config/the_isa.hh"
44 #include "cpu/intr_control.hh"
45 #include "cpu/thread_context.hh"
46 #include "debug/Malta.hh"
47 #include "dev/mips/malta.hh"
48 #include "dev/mips/maltareg.h"
49 #include "mem/packet.hh"
50 #include "mem/packet_access.hh"
51 #include "mem/port.hh"
52 #include "params/MaltaCChip.hh"
53 #include "sim/system.hh"
56 using namespace TheISA
;
58 MaltaCChip::MaltaCChip(Params
*p
)
59 : BasicPioDevice(p
, 0xfffffff), malta(p
->malta
)
61 warn("MaltaCCHIP::MaltaCChip() not implemented.");
63 //Put back pointer in malta
69 MaltaCChip::read(PacketPtr pkt
)
71 panic("MaltaCCHIP::read() not implemented.");
74 DPRINTF(Malta, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
76 assert(pkt->result == Packet::Unknown);
77 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
79 Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
80 Addr daddr = (pkt->getAddr() - pioAddr);
82 switch (pkt->getSize()) {
84 case sizeof(uint64_t):
85 if (daddr & TSDEV_CC_BDIMS)
87 pkt->set(dim[(daddr >> 4) & 0x3F]);
91 if (daddr & TSDEV_CC_BDIRS)
93 pkt->set(dir[(daddr >> 4) & 0x3F]);
102 panic("TSDEV_CC_MTR not implemeted\n");
105 pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
106 (pkt->req->contextId() & 0x3));
142 panic("TSDEV_CC_PRBEN not implemented\n");
148 panic("TSDEV_CC_IICx not implemented\n");
154 panic("TSDEV_CC_MPRx not implemented\n");
163 panic("default in cchip read reached, accessing 0x%x\n");
167 case sizeof(uint32_t):
168 case sizeof(uint16_t):
169 case sizeof(uint8_t):
171 panic("invalid access size(?) for malta register!\n");
173 DPRINTF(Malta, "Malta CChip: read regnum=%#x size=%d data=%lld\n",
174 regnum, pkt->getSize(), pkt->get<uint64_t>());
176 pkt->result = Packet::Success;
182 MaltaCChip::write(PacketPtr pkt
)
184 panic("MaltaCCHIP::write() not implemented.");
187 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
188 Addr daddr = pkt->getAddr() - pioAddr;
189 Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
192 assert(pkt->getSize() == sizeof(uint64_t));
194 DPRINTF(Malta, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
196 bool supportedWrite = false;
199 if (daddr & TSDEV_CC_BDIMS)
201 int number = (daddr >> 4) & 0x3F;
207 olddim = dim[number];
208 olddir = dir[number];
209 dim[number] = pkt->get<uint64_t>();
210 dir[number] = dim[number] & drir;
211 for (int x = 0; x < Malta::Max_CPUs; x++)
213 bitvector = ULL(1) << x;
214 // Figure out which bits have changed
215 if ((dim[number] & bitvector) != (olddim & bitvector))
217 // The bit is now set and it wasn't before (set)
218 if ((dim[number] & bitvector) && (dir[number] & bitvector))
220 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
221 DPRINTF(Malta, "dim write resulting in posting dir"
222 " interrupt to cpu %d\n", number);
224 else if ((olddir & bitvector) &&
225 !(dir[number] & bitvector))
227 // The bit was set and now its now clear and
228 // we were interrupting on that bit before
229 malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
230 DPRINTF(Malta, "dim write resulting in clear"
231 " dir interrupt to cpu %d\n", number);
241 panic("TSDEV_CC_CSR write\n");
243 panic("TSDEV_CC_MTR write not implemented\n");
246 ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
247 //If it is bit 12-15, this is an IPI post
250 supportedWrite = true;
253 //If it is bit 8-11, this is an IPI clear
255 ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
258 supportedWrite = true;
261 //If it is the 4-7th bit, clear the RTC interrupt
263 itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
266 supportedWrite = true;
270 if (pkt->get<uint64_t>() & 0x10000000)
271 supportedWrite = true;
274 panic("TSDEV_CC_MISC write not implemented\n");
281 panic("TSDEV_CC_AARx write not implemeted\n");
287 if (regnum == TSDEV_CC_DIM0)
289 else if (regnum == TSDEV_CC_DIM1)
291 else if (regnum == TSDEV_CC_DIM2)
300 olddim = dim[number];
301 olddir = dir[number];
302 dim[number] = pkt->get<uint64_t>();
303 dir[number] = dim[number] & drir;
304 for (int x = 0; x < 64; x++)
306 bitvector = ULL(1) << x;
307 // Figure out which bits have changed
308 if ((dim[number] & bitvector) != (olddim & bitvector))
310 // The bit is now set and it wasn't before (set)
311 if ((dim[number] & bitvector) && (dir[number] & bitvector))
313 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
314 DPRINTF(Malta, "posting dir interrupt to cpu 0\n");
316 else if ((olddir & bitvector) &&
317 !(dir[number] & bitvector))
319 // The bit was set and now its now clear and
320 // we were interrupting on that bit before
321 malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
322 DPRINTF(Malta, "dim write resulting in clear"
323 " dir interrupt to cpu %d\n",
336 panic("TSDEV_CC_DIR write not implemented\n");
338 panic("TSDEV_CC_DRIR write not implemented\n");
340 panic("TSDEV_CC_PRBEN write not implemented\n");
345 panic("TSDEV_CC_IICx write not implemented\n");
350 panic("TSDEV_CC_MPRx write not implemented\n");
352 clearIPI(pkt->get<uint64_t>());
355 clearITI(pkt->get<uint64_t>());
358 reqIPI(pkt->get<uint64_t>());
361 panic("default in cchip read reached, accessing 0x%x\n");
363 } // not BIG_TSUNAMI write
364 pkt->result = Packet::Success;
370 MaltaCChip::clearIPI(uint64_t ipintr
)
372 panic("MaltaCCHIP::clear() not implemented.");
374 int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
375 assert(numcpus <= Malta::Max_CPUs);
378 for (int cpunum=0; cpunum < numcpus; cpunum++) {
379 // Check each cpu bit
380 uint64_t cpumask = ULL(1) << cpunum;
381 if (ipintr & cpumask) {
382 // Check if there is a pending ipi
383 if (ipint & cpumask) {
385 malta->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
386 DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
389 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
394 panic("Big IPI Clear, but not processors indicated\n");
399 MaltaCChip::clearITI(uint64_t itintr
)
401 panic("MaltaCCHIP::clearITI() not implemented.");
403 int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
404 assert(numcpus <= Malta::Max_CPUs);
407 for (int i=0; i < numcpus; i++) {
408 uint64_t cpumask = ULL(1) << i;
409 if (itintr & cpumask & itint) {
410 malta->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
412 DPRINTF(Malta, "clearing rtc interrupt to cpu=%d\n", i);
417 panic("Big ITI Clear, but not processors indicated\n");
422 MaltaCChip::reqIPI(uint64_t ipreq
)
424 panic("MaltaCCHIP::reqIPI() not implemented.");
427 int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
428 assert(numcpus <= Malta::Max_CPUs);
431 for (int cpunum=0; cpunum < numcpus; cpunum++) {
432 // Check each cpu bit
433 uint64_t cpumask = ULL(1) << cpunum;
434 if (ipreq & cpumask) {
435 // Check if there is already an ipi (bits 8:11)
436 if (!(ipint & cpumask)) {
438 malta->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
439 DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
442 warn("post IPI for CPU=%d, but IPI already\n", cpunum);
447 panic("Big IPI Request, but not processors indicated\n");
454 MaltaCChip::postRTC()
456 panic("MaltaCCHIP::postRTC() not implemented.");
459 int size = malta->intrctrl->cpu->system->threadContexts.size();
460 assert(size <= Malta::Max_CPUs);
462 for (int i = 0; i < size; i++) {
463 uint64_t cpumask = ULL(1) << i;
464 if (!(cpumask & itint)) {
466 malta->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
467 DPRINTF(Malta, "Posting RTC interrupt to cpu=%d", i);
475 MaltaCChip::postIntr(uint32_t interrupt
)
477 uint64_t size
= sys
->threadContexts
.size();
478 assert(size
<= Malta::Max_CPUs
);
480 for (int i
=0; i
< size
; i
++) {
481 //Note: Malta does not use index, but this was added to use the pre-existing implementation
482 malta
->intrctrl
->post(i
, interrupt
, 0);
483 DPRINTF(Malta
, "posting interrupt to cpu %d,"
484 "interrupt %d\n",i
, interrupt
);
490 MaltaCChip::clearIntr(uint32_t interrupt
)
492 uint64_t size
= sys
->threadContexts
.size();
493 assert(size
<= Malta::Max_CPUs
);
495 for (int i
=0; i
< size
; i
++) {
496 //Note: Malta does not use index, but this was added to use the pre-existing implementation
497 malta
->intrctrl
->clear(i
, interrupt
, 0);
498 DPRINTF(Malta
, "clearing interrupt to cpu %d,"
499 "interrupt %d\n",i
, interrupt
);
505 MaltaCChip::serialize(CheckpointOut
&cp
) const
507 // SERIALIZE_ARRAY(dim, Malta::Max_CPUs);
508 //SERIALIZE_ARRAY(dir, Malta::Max_CPUs);
509 //SERIALIZE_SCALAR(ipint);
510 //SERIALIZE_SCALAR(itint);
511 //SERIALIZE_SCALAR(drir);
515 MaltaCChip::unserialize(CheckpointIn
&cp
)
517 //UNSERIALIZE_ARRAY(dim, Malta::Max_CPUs);
518 //UNSERIALIZE_ARRAY(dir, Malta::Max_CPUs);
519 //UNSERIALIZE_SCALAR(ipint);
520 //UNSERIALIZE_SCALAR(itint);
521 //UNSERIALIZE_SCALAR(drir);
525 MaltaCChipParams::create()
527 return new MaltaCChip(this);