2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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33 * Emulation of the Malta CChip CSRs
40 #include "base/trace.hh"
41 #include "config/the_isa.hh"
42 #include "cpu/intr_control.hh"
43 #include "cpu/thread_context.hh"
44 #include "debug/Malta.hh"
45 #include "dev/mips/malta.hh"
46 #include "dev/mips/malta_cchip.hh"
47 #include "dev/mips/maltareg.h"
48 #include "mem/packet.hh"
49 #include "mem/packet_access.hh"
50 #include "mem/port.hh"
51 #include "params/MaltaCChip.hh"
52 #include "sim/system.hh"
55 using namespace TheISA
;
57 MaltaCChip::MaltaCChip(Params
*p
)
58 : BasicPioDevice(p
, 0xfffffff), malta(p
->malta
)
60 warn("MaltaCCHIP::MaltaCChip() not implemented.");
62 //Put back pointer in malta
68 MaltaCChip::read(PacketPtr pkt
)
70 panic("MaltaCCHIP::read() not implemented.");
73 DPRINTF(Malta, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
75 assert(pkt->result == Packet::Unknown);
76 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
78 Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
79 Addr daddr = (pkt->getAddr() - pioAddr);
81 switch (pkt->getSize()) {
83 case sizeof(uint64_t):
84 if (daddr & TSDEV_CC_BDIMS)
86 pkt->set(dim[(daddr >> 4) & 0x3F]);
90 if (daddr & TSDEV_CC_BDIRS)
92 pkt->set(dir[(daddr >> 4) & 0x3F]);
101 panic("TSDEV_CC_MTR not implemeted\n");
104 pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
105 (pkt->req->contextId() & 0x3));
141 panic("TSDEV_CC_PRBEN not implemented\n");
147 panic("TSDEV_CC_IICx not implemented\n");
153 panic("TSDEV_CC_MPRx not implemented\n");
162 panic("default in cchip read reached, accessing 0x%x\n");
166 case sizeof(uint32_t):
167 case sizeof(uint16_t):
168 case sizeof(uint8_t):
170 panic("invalid access size(?) for malta register!\n");
172 DPRINTF(Malta, "Malta CChip: read regnum=%#x size=%d data=%lld\n",
173 regnum, pkt->getSize(), pkt->get<uint64_t>());
175 pkt->result = Packet::Success;
181 MaltaCChip::write(PacketPtr pkt
)
183 panic("MaltaCCHIP::write() not implemented.");
186 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
187 Addr daddr = pkt->getAddr() - pioAddr;
188 Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
191 assert(pkt->getSize() == sizeof(uint64_t));
193 DPRINTF(Malta, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
195 bool supportedWrite = false;
198 if (daddr & TSDEV_CC_BDIMS)
200 int number = (daddr >> 4) & 0x3F;
206 olddim = dim[number];
207 olddir = dir[number];
208 dim[number] = pkt->get<uint64_t>();
209 dir[number] = dim[number] & drir;
210 for (int x = 0; x < Malta::Max_CPUs; x++)
212 bitvector = ULL(1) << x;
213 // Figure out which bits have changed
214 if ((dim[number] & bitvector) != (olddim & bitvector))
216 // The bit is now set and it wasn't before (set)
217 if ((dim[number] & bitvector) && (dir[number] & bitvector))
219 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
220 DPRINTF(Malta, "dim write resulting in posting dir"
221 " interrupt to cpu %d\n", number);
223 else if ((olddir & bitvector) &&
224 !(dir[number] & bitvector))
226 // The bit was set and now its now clear and
227 // we were interrupting on that bit before
228 malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
229 DPRINTF(Malta, "dim write resulting in clear"
230 " dir interrupt to cpu %d\n", number);
240 panic("TSDEV_CC_CSR write\n");
242 panic("TSDEV_CC_MTR write not implemented\n");
245 ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
246 //If it is bit 12-15, this is an IPI post
249 supportedWrite = true;
252 //If it is bit 8-11, this is an IPI clear
254 ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
257 supportedWrite = true;
260 //If it is the 4-7th bit, clear the RTC interrupt
262 itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
265 supportedWrite = true;
269 if (pkt->get<uint64_t>() & 0x10000000)
270 supportedWrite = true;
273 panic("TSDEV_CC_MISC write not implemented\n");
280 panic("TSDEV_CC_AARx write not implemeted\n");
286 if (regnum == TSDEV_CC_DIM0)
288 else if (regnum == TSDEV_CC_DIM1)
290 else if (regnum == TSDEV_CC_DIM2)
299 olddim = dim[number];
300 olddir = dir[number];
301 dim[number] = pkt->get<uint64_t>();
302 dir[number] = dim[number] & drir;
303 for (int x = 0; x < 64; x++)
305 bitvector = ULL(1) << x;
306 // Figure out which bits have changed
307 if ((dim[number] & bitvector) != (olddim & bitvector))
309 // The bit is now set and it wasn't before (set)
310 if ((dim[number] & bitvector) && (dir[number] & bitvector))
312 malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
313 DPRINTF(Malta, "posting dir interrupt to cpu 0\n");
315 else if ((olddir & bitvector) &&
316 !(dir[number] & bitvector))
318 // The bit was set and now its now clear and
319 // we were interrupting on that bit before
320 malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
321 DPRINTF(Malta, "dim write resulting in clear"
322 " dir interrupt to cpu %d\n",
335 panic("TSDEV_CC_DIR write not implemented\n");
337 panic("TSDEV_CC_DRIR write not implemented\n");
339 panic("TSDEV_CC_PRBEN write not implemented\n");
344 panic("TSDEV_CC_IICx write not implemented\n");
349 panic("TSDEV_CC_MPRx write not implemented\n");
351 clearIPI(pkt->get<uint64_t>());
354 clearITI(pkt->get<uint64_t>());
357 reqIPI(pkt->get<uint64_t>());
360 panic("default in cchip read reached, accessing 0x%x\n");
362 } // not BIG_TSUNAMI write
363 pkt->result = Packet::Success;
369 MaltaCChip::clearIPI(uint64_t ipintr
)
371 panic("MaltaCCHIP::clear() not implemented.");
373 int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
374 assert(numcpus <= Malta::Max_CPUs);
377 for (int cpunum=0; cpunum < numcpus; cpunum++) {
378 // Check each cpu bit
379 uint64_t cpumask = ULL(1) << cpunum;
380 if (ipintr & cpumask) {
381 // Check if there is a pending ipi
382 if (ipint & cpumask) {
384 malta->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
385 DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
388 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
393 panic("Big IPI Clear, but not processors indicated\n");
398 MaltaCChip::clearITI(uint64_t itintr
)
400 panic("MaltaCCHIP::clearITI() not implemented.");
402 int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
403 assert(numcpus <= Malta::Max_CPUs);
406 for (int i=0; i < numcpus; i++) {
407 uint64_t cpumask = ULL(1) << i;
408 if (itintr & cpumask & itint) {
409 malta->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
411 DPRINTF(Malta, "clearing rtc interrupt to cpu=%d\n", i);
416 panic("Big ITI Clear, but not processors indicated\n");
421 MaltaCChip::reqIPI(uint64_t ipreq
)
423 panic("MaltaCCHIP::reqIPI() not implemented.");
426 int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
427 assert(numcpus <= Malta::Max_CPUs);
430 for (int cpunum=0; cpunum < numcpus; cpunum++) {
431 // Check each cpu bit
432 uint64_t cpumask = ULL(1) << cpunum;
433 if (ipreq & cpumask) {
434 // Check if there is already an ipi (bits 8:11)
435 if (!(ipint & cpumask)) {
437 malta->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
438 DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
441 warn("post IPI for CPU=%d, but IPI already\n", cpunum);
446 panic("Big IPI Request, but not processors indicated\n");
453 MaltaCChip::postRTC()
455 panic("MaltaCCHIP::postRTC() not implemented.");
458 int size = malta->intrctrl->cpu->system->threadContexts.size();
459 assert(size <= Malta::Max_CPUs);
461 for (int i = 0; i < size; i++) {
462 uint64_t cpumask = ULL(1) << i;
463 if (!(cpumask & itint)) {
465 malta->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
466 DPRINTF(Malta, "Posting RTC interrupt to cpu=%d", i);
474 MaltaCChip::postIntr(uint32_t interrupt
)
476 uint64_t size
= sys
->threadContexts
.size();
477 assert(size
<= Malta::Max_CPUs
);
479 for (int i
=0; i
< size
; i
++) {
480 //Note: Malta does not use index, but this was added to use the pre-existing implementation
481 malta
->intrctrl
->post(i
, interrupt
, 0);
482 DPRINTF(Malta
, "posting interrupt to cpu %d,"
483 "interrupt %d\n",i
, interrupt
);
489 MaltaCChip::clearIntr(uint32_t interrupt
)
491 uint64_t size
= sys
->threadContexts
.size();
492 assert(size
<= Malta::Max_CPUs
);
494 for (int i
=0; i
< size
; i
++) {
495 //Note: Malta does not use index, but this was added to use the pre-existing implementation
496 malta
->intrctrl
->clear(i
, interrupt
, 0);
497 DPRINTF(Malta
, "clearing interrupt to cpu %d,"
498 "interrupt %d\n",i
, interrupt
);
504 MaltaCChip::serialize(CheckpointOut
&cp
) const
506 // SERIALIZE_ARRAY(dim, Malta::Max_CPUs);
507 //SERIALIZE_ARRAY(dir, Malta::Max_CPUs);
508 //SERIALIZE_SCALAR(ipint);
509 //SERIALIZE_SCALAR(itint);
510 //SERIALIZE_SCALAR(drir);
514 MaltaCChip::unserialize(CheckpointIn
&cp
)
516 //UNSERIALIZE_ARRAY(dim, Malta::Max_CPUs);
517 //UNSERIALIZE_ARRAY(dir, Malta::Max_CPUs);
518 //UNSERIALIZE_SCALAR(ipint);
519 //UNSERIALIZE_SCALAR(itint);
520 //UNSERIALIZE_SCALAR(drir);
524 MaltaCChipParams::create()
526 return new MaltaCChip(this);