src/dev/mips/malta_cchip.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Ali Saidi
  29  *          Rick Strong
  30  */
  31
  32 /** @file
  33  * Emulation of the Malta CChip CSRs
  34  */
  35
  36 #include <deque>
  37 #include <string>
  38 #include <vector>
  39
  40 #include "arch/mips/mips_core_specific.hh"
  41 #include "base/trace.hh"
  42 #include "config/the_isa.hh"
  43 #include "cpu/intr_control.hh"
  44 #include "cpu/thread_context.hh"
  45 #include "dev/mips/malta.hh"
  46 #include "dev/mips/malta_cchip.hh"
  47 #include "dev/mips/maltareg.h"
  48 #include "mem/packet.hh"
  49 #include "mem/packet_access.hh"
  50 #include "mem/port.hh"
  51 #include "params/MaltaCChip.hh"
  52 #include "sim/system.hh"
  53
  54 using namespace std;
  55 using namespace TheISA;
  56
  57 MaltaCChip::MaltaCChip(Params *p)
  58     : BasicPioDevice(p), malta(p->malta)
  59 {
  60     warn("MaltaCCHIP::MaltaCChip() not implemented.");
  61
  62     pioSize = 0xfffffff;
  63     //Put back pointer in malta
  64     malta->cchip = this;
  65
  66 }
  67
  68 Tick
  69 MaltaCChip::read(PacketPtr pkt)
  70 {
  71                 panic("MaltaCCHIP::read() not implemented.");
  72                 return pioDelay;
  73                 /*
  74     DPRINTF(Malta, "read  va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
  75
  76     assert(pkt->result == Packet::Unknown);
  77     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
  78
  79     Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
  80     Addr daddr = (pkt->getAddr() - pioAddr);
  81
  82     pkt->allocate();
  83     switch (pkt->getSize()) {
  84
  85       case sizeof(uint64_t):
  86           if (daddr & TSDEV_CC_BDIMS)
  87           {
  88               pkt->set(dim[(daddr >> 4) & 0x3F]);
  89               break;
  90           }
  91
  92           if (daddr & TSDEV_CC_BDIRS)
  93           {
  94               pkt->set(dir[(daddr >> 4) & 0x3F]);
  95               break;
  96           }
  97
  98           switch(regnum) {
  99               case TSDEV_CC_CSR:
 100                   pkt->set(0x0);
 101                   break;
 102               case TSDEV_CC_MTR:
 103                   panic("TSDEV_CC_MTR not implemeted\n");
 104                    break;
 105               case TSDEV_CC_MISC:
 106                   pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
 107                                      (pkt->req->contextId() & 0x3));
 108                   break;
 109               case TSDEV_CC_AAR0:
 110               case TSDEV_CC_AAR1:
 111               case TSDEV_CC_AAR2:
 112               case TSDEV_CC_AAR3:
 113                   pkt->set(0);
 114                   break;
 115               case TSDEV_CC_DIM0:
 116                   pkt->set(dim[0]);
 117                   break;
 118               case TSDEV_CC_DIM1:
 119                   pkt->set(dim[1]);
 120                   break;
 121               case TSDEV_CC_DIM2:
 122                   pkt->set(dim[2]);
 123                   break;
 124               case TSDEV_CC_DIM3:
 125                   pkt->set(dim[3]);
 126                   break;
 127               case TSDEV_CC_DIR0:
 128                   pkt->set(dir[0]);
 129                   break;
 130               case TSDEV_CC_DIR1:
 131                   pkt->set(dir[1]);
 132                   break;
 133               case TSDEV_CC_DIR2:
 134                   pkt->set(dir[2]);
 135                   break;
 136               case TSDEV_CC_DIR3:
 137                   pkt->set(dir[3]);
 138                   break;
 139               case TSDEV_CC_DRIR:
 140                   pkt->set(drir);
 141                   break;
 142               case TSDEV_CC_PRBEN:
 143                   panic("TSDEV_CC_PRBEN not implemented\n");
 144                   break;
 145               case TSDEV_CC_IIC0:
 146               case TSDEV_CC_IIC1:
 147               case TSDEV_CC_IIC2:
 148               case TSDEV_CC_IIC3:
 149                   panic("TSDEV_CC_IICx not implemented\n");
 150                   break;
 151               case TSDEV_CC_MPR0:
 152               case TSDEV_CC_MPR1:
 153               case TSDEV_CC_MPR2:
 154               case TSDEV_CC_MPR3:
 155                   panic("TSDEV_CC_MPRx not implemented\n");
 156                   break;
 157               case TSDEV_CC_IPIR:
 158                   pkt->set(ipint);
 159                   break;
 160               case TSDEV_CC_ITIR:
 161                   pkt->set(itint);
 162                   break;
 163               default:
 164                   panic("default in cchip read reached, accessing 0x%x\n");
 165            } // uint64_t
 166
 167       break;
 168       case sizeof(uint32_t):
 169       case sizeof(uint16_t):
 170       case sizeof(uint8_t):
 171       default:
 172         panic("invalid access size(?) for malta register!\n");
 173     }
 174     DPRINTF(Malta, "Malta CChip: read  regnum=%#x size=%d data=%lld\n",
 175             regnum, pkt->getSize(), pkt->get<uint64_t>());
 176
 177     pkt->result = Packet::Success;
 178     return pioDelay;
 179     */
 180 }
 181
 182 Tick
 183 MaltaCChip::write(PacketPtr pkt)
 184 {
 185                 panic("MaltaCCHIP::write() not implemented.");
 186                 return pioDelay;
 187                 /*
 188     assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
 189     Addr daddr = pkt->getAddr() - pioAddr;
 190     Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
 191
 192
 193     assert(pkt->getSize() == sizeof(uint64_t));
 194
 195     DPRINTF(Malta, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
 196
 197     bool supportedWrite = false;
 198
 199
 200     if (daddr & TSDEV_CC_BDIMS)
 201     {
 202         int number = (daddr >> 4) & 0x3F;
 203
 204         uint64_t bitvector;
 205         uint64_t olddim;
 206         uint64_t olddir;
 207
 208         olddim = dim[number];
 209         olddir = dir[number];
 210         dim[number] = pkt->get<uint64_t>();
 211         dir[number] = dim[number] & drir;
 212         for(int x = 0; x < Malta::Max_CPUs; x++)
 213         {
 214             bitvector = ULL(1) << x;
 215             // Figure out which bits have changed
 216             if ((dim[number] & bitvector) != (olddim & bitvector))
 217             {
 218                 // The bit is now set and it wasn't before (set)
 219                 if((dim[number] & bitvector) && (dir[number] & bitvector))
 220                 {
 221                     malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
 222                     DPRINTF(Malta, "dim write resulting in posting dir"
 223                             " interrupt to cpu %d\n", number);
 224                 }
 225                 else if ((olddir & bitvector) &&
 226                         !(dir[number] & bitvector))
 227                 {
 228                     // The bit was set and now its now clear and
 229                     // we were interrupting on that bit before
 230                     malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
 231                     DPRINTF(Malta, "dim write resulting in clear"
 232                             " dir interrupt to cpu %d\n", number);
 233
 234                 }
 235
 236
 237             }
 238         }
 239     } else {
 240         switch(regnum) {
 241           case TSDEV_CC_CSR:
 242               panic("TSDEV_CC_CSR write\n");
 243           case TSDEV_CC_MTR:
 244               panic("TSDEV_CC_MTR write not implemented\n");
 245           case TSDEV_CC_MISC:
 246             uint64_t ipreq;
 247             ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
 248             //If it is bit 12-15, this is an IPI post
 249             if (ipreq) {
 250                 reqIPI(ipreq);
 251                 supportedWrite = true;
 252             }
 253
 254             //If it is bit 8-11, this is an IPI clear
 255             uint64_t ipintr;
 256             ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
 257             if (ipintr) {
 258                 clearIPI(ipintr);
 259                 supportedWrite = true;
 260             }
 261
 262             //If it is the 4-7th bit, clear the RTC interrupt
 263             uint64_t itintr;
 264               itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
 265             if (itintr) {
 266                   clearITI(itintr);
 267                 supportedWrite = true;
 268             }
 269
 270               // ignore NXMs
 271               if (pkt->get<uint64_t>() & 0x10000000)
 272                   supportedWrite = true;
 273
 274             if(!supportedWrite)
 275                   panic("TSDEV_CC_MISC write not implemented\n");
 276
 277             break;
 278             case TSDEV_CC_AAR0:
 279             case TSDEV_CC_AAR1:
 280             case TSDEV_CC_AAR2:
 281             case TSDEV_CC_AAR3:
 282                 panic("TSDEV_CC_AARx write not implemeted\n");
 283             case TSDEV_CC_DIM0:
 284             case TSDEV_CC_DIM1:
 285             case TSDEV_CC_DIM2:
 286             case TSDEV_CC_DIM3:
 287                 int number;
 288                 if(regnum == TSDEV_CC_DIM0)
 289                     number = 0;
 290                 else if(regnum == TSDEV_CC_DIM1)
 291                     number = 1;
 292                 else if(regnum == TSDEV_CC_DIM2)
 293                     number = 2;
 294                 else
 295                     number = 3;
 296
 297                 uint64_t bitvector;
 298                 uint64_t olddim;
 299                 uint64_t olddir;
 300
 301                 olddim = dim[number];
 302                 olddir = dir[number];
 303                 dim[number] = pkt->get<uint64_t>();
 304                 dir[number] = dim[number] & drir;
 305                 for(int x = 0; x < 64; x++)
 306                 {
 307                     bitvector = ULL(1) << x;
 308                     // Figure out which bits have changed
 309                     if ((dim[number] & bitvector) != (olddim & bitvector))
 310                     {
 311                         // The bit is now set and it wasn't before (set)
 312                         if((dim[number] & bitvector) && (dir[number] & bitvector))
 313                         {
 314                           malta->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
 315                           DPRINTF(Malta, "posting dir interrupt to cpu 0\n");
 316                         }
 317                         else if ((olddir & bitvector) &&
 318                                 !(dir[number] & bitvector))
 319                         {
 320                             // The bit was set and now its now clear and
 321                             // we were interrupting on that bit before
 322                             malta->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
 323                           DPRINTF(Malta, "dim write resulting in clear"
 324                                     " dir interrupt to cpu %d\n",
 325                                     x);
 326
 327                         }
 328
 329
 330                     }
 331                 }
 332                 break;
 333             case TSDEV_CC_DIR0:
 334             case TSDEV_CC_DIR1:
 335             case TSDEV_CC_DIR2:
 336             case TSDEV_CC_DIR3:
 337                 panic("TSDEV_CC_DIR write not implemented\n");
 338             case TSDEV_CC_DRIR:
 339                 panic("TSDEV_CC_DRIR write not implemented\n");
 340             case TSDEV_CC_PRBEN:
 341                 panic("TSDEV_CC_PRBEN write not implemented\n");
 342             case TSDEV_CC_IIC0:
 343             case TSDEV_CC_IIC1:
 344             case TSDEV_CC_IIC2:
 345             case TSDEV_CC_IIC3:
 346                 panic("TSDEV_CC_IICx write not implemented\n");
 347             case TSDEV_CC_MPR0:
 348             case TSDEV_CC_MPR1:
 349             case TSDEV_CC_MPR2:
 350             case TSDEV_CC_MPR3:
 351                 panic("TSDEV_CC_MPRx write not implemented\n");
 352             case TSDEV_CC_IPIR:
 353                 clearIPI(pkt->get<uint64_t>());
 354                 break;
 355             case TSDEV_CC_ITIR:
 356                 clearITI(pkt->get<uint64_t>());
 357                 break;
 358             case TSDEV_CC_IPIQ:
 359                 reqIPI(pkt->get<uint64_t>());
 360                 break;
 361             default:
 362               panic("default in cchip read reached, accessing 0x%x\n");
 363         }  // swtich(regnum)
 364     } // not BIG_TSUNAMI write
 365     pkt->result = Packet::Success;
 366     return pioDelay;
 367     */
 368 }
 369
 370 void
 371 MaltaCChip::clearIPI(uint64_t ipintr)
 372 {
 373                 panic("MaltaCCHIP::clear() not implemented.");
 374                 /*
 375     int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
 376     assert(numcpus <= Malta::Max_CPUs);
 377
 378     if (ipintr) {
 379         for (int cpunum=0; cpunum < numcpus; cpunum++) {
 380             // Check each cpu bit
 381             uint64_t cpumask = ULL(1) << cpunum;
 382             if (ipintr & cpumask) {
 383                 // Check if there is a pending ipi
 384                 if (ipint & cpumask) {
 385                     ipint &= ~cpumask;
 386                     malta->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
 387                     DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
 388                 }
 389                 else
 390                     warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
 391             }
 392         }
 393     }
 394     else
 395         panic("Big IPI Clear, but not processors indicated\n");
 396         */
 397 }
 398
 399 void
 400 MaltaCChip::clearITI(uint64_t itintr)
 401 {
 402                 panic("MaltaCCHIP::clearITI() not implemented.");
 403                 /*
 404     int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
 405     assert(numcpus <= Malta::Max_CPUs);
 406
 407     if (itintr) {
 408         for (int i=0; i < numcpus; i++) {
 409             uint64_t cpumask = ULL(1) << i;
 410             if (itintr & cpumask & itint) {
 411                 malta->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
 412                 itint &= ~cpumask;
 413                 DPRINTF(Malta, "clearing rtc interrupt to cpu=%d\n", i);
 414             }
 415         }
 416     }
 417     else
 418         panic("Big ITI Clear, but not processors indicated\n");
 419     */
 420 }
 421
 422 void
 423 MaltaCChip::reqIPI(uint64_t ipreq)
 424 {
 425                 panic("MaltaCCHIP::reqIPI() not implemented.");
 426
 427                 /*
 428     int numcpus = malta->intrctrl->cpu->system->threadContexts.size();
 429     assert(numcpus <= Malta::Max_CPUs);
 430
 431     if (ipreq) {
 432         for (int cpunum=0; cpunum < numcpus; cpunum++) {
 433             // Check each cpu bit
 434             uint64_t cpumask = ULL(1) << cpunum;
 435             if (ipreq & cpumask) {
 436                 // Check if there is already an ipi (bits 8:11)
 437                 if (!(ipint & cpumask)) {
 438                     ipint  |= cpumask;
 439                     malta->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
 440                     DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
 441                 }
 442                 else
 443                     warn("post IPI for CPU=%d, but IPI already\n", cpunum);
 444             }
 445         }
 446     }
 447     else
 448         panic("Big IPI Request, but not processors indicated\n");
 449    */
 450
 451 }
 452
 453
 454 void
 455 MaltaCChip::postRTC()
 456 {
 457                 panic("MaltaCCHIP::postRTC() not implemented.");
 458
 459                 /*
 460     int size = malta->intrctrl->cpu->system->threadContexts.size();
 461     assert(size <= Malta::Max_CPUs);
 462
 463     for (int i = 0; i < size; i++) {
 464         uint64_t cpumask = ULL(1) << i;
 465        if (!(cpumask & itint)) {
 466            itint |= cpumask;
 467            malta->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
 468            DPRINTF(Malta, "Posting RTC interrupt to cpu=%d", i);
 469        }
 470     }
 471     */
 472
 473 }
 474
 475 void
 476 MaltaCChip::postIntr(uint32_t interrupt)
 477 {
 478     uint64_t size = sys->threadContexts.size();
 479     assert(size <= Malta::Max_CPUs);
 480
 481     for(int i=0; i < size; i++) {
 482                                         //Note: Malta does not use index, but this was added to use the pre-existing implementation
 483               malta->intrctrl->post(i, interrupt, 0);
 484               DPRINTF(Malta, "posting  interrupt to cpu %d,"
 485                         "interrupt %d\n",i, interrupt);
 486    }
 487
 488 }
 489
 490 void
 491 MaltaCChip::clearIntr(uint32_t interrupt)
 492 {
 493     uint64_t size = sys->threadContexts.size();
 494     assert(size <= Malta::Max_CPUs);
 495
 496     for(int i=0; i < size; i++) {
 497                                         //Note: Malta does not use index, but this was added to use the pre-existing implementation
 498               malta->intrctrl->clear(i, interrupt, 0);
 499               DPRINTF(Malta, "clearing interrupt to cpu %d,"
 500                         "interrupt %d\n",i, interrupt);
 501    }
 502 }
 503
 504
 505 void
 506 MaltaCChip::serialize(std::ostream &os)
 507 {
 508    // SERIALIZE_ARRAY(dim, Malta::Max_CPUs);
 509     //SERIALIZE_ARRAY(dir, Malta::Max_CPUs);
 510     //SERIALIZE_SCALAR(ipint);
 511     //SERIALIZE_SCALAR(itint);
 512     //SERIALIZE_SCALAR(drir);
 513 }
 514
 515 void
 516 MaltaCChip::unserialize(Checkpoint *cp, const std::string &section)
 517 {
 518     //UNSERIALIZE_ARRAY(dim, Malta::Max_CPUs);
 519     //UNSERIALIZE_ARRAY(dir, Malta::Max_CPUs);
 520     //UNSERIALIZE_SCALAR(ipint);
 521     //UNSERIALIZE_SCALAR(itint);
 522     //UNSERIALIZE_SCALAR(drir);
 523 }
 524
 525 MaltaCChip *
 526 MaltaCChipParams::create()
 527 {
 528     return new MaltaCChip(this);
 529 }
 530