2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * Malta I/O including PIC, PIT, RTC, DMA
43 #include "base/trace.hh"
44 #include "dev/pitreg.h"
45 #include "dev/rtcreg.h"
46 #include "dev/mips/malta_cchip.hh"
47 #include "dev/mips/malta.hh"
48 #include "dev/mips/malta_io.hh"
49 #include "dev/mips/maltareg.h"
50 #include "mem/packet.hh"
51 #include "mem/packet_access.hh"
52 #include "mem/port.hh"
53 #include "params/MaltaIO.hh"
54 #include "sim/system.hh"
57 using namespace TheISA
;
59 MaltaIO::RTC::RTC(const string
&name
, Malta
* t
, Tick i
)
60 : _name(name
), event(t
, i
), addr(0)
62 memset(clock_data
, 0, sizeof(clock_data
));
63 stat_regA
= RTCA_32768HZ
| RTCA_1024HZ
;
64 stat_regB
= RTCB_PRDC_IE
|RTCB_BIN
| RTCB_24HR
;
68 MaltaIO::RTC::set_time(time_t t
)
76 wday
= tm
.tm_wday
+ 1;
81 DPRINTFN("Real-time clock set to %s", asctime(&tm
));
85 MaltaIO::RTC::writeAddr(const uint8_t data
)
87 panic("MaltaIO::RTC::writeAddr has not been implemented for malta");
89 if (data <= RTC_STAT_REGD)
92 panic("RTC addresses over 0xD are not implemented.\n");
97 MaltaIO::RTC::writeData(const uint8_t data
)
99 panic("MaltaIO::RTC::writeData has not been implemented for malta");
101 if (addr < RTC_STAT_REGA)
102 clock_data[addr] = data;
106 if (data != (RTCA_32768HZ | RTCA_1024HZ))
107 panic("Unimplemented RTC register A value write!\n");
111 if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != (RTCB_BIN | RTCB_24HR))
112 panic("Write to RTC reg B bits that are not implemented!\n");
114 if (data & RTCB_PRDC_IE) {
115 if (!event.scheduled())
116 event.scheduleIntr();
118 if (event.scheduled())
125 panic("RTC status registers C and D are not implemented.\n");
134 MaltaIO::RTC::readData()
136 panic("MaltaIO::RTC::readData() has not been implemented for malta");
138 if (addr < RTC_STAT_REGA)
139 return clock_data[addr];
143 // toggle UIP bit for linux
144 stat_regA ^= RTCA_UIP;
155 panic("Shouldn't be here");
162 MaltaIO::RTC::serialize(const string
&base
, ostream
&os
)
164 paramOut(os
, base
+ ".addr", addr
);
165 arrayParamOut(os
, base
+ ".clock_data", clock_data
, sizeof(clock_data
));
166 paramOut(os
, base
+ ".stat_regA", stat_regA
);
167 paramOut(os
, base
+ ".stat_regB", stat_regB
);
171 MaltaIO::RTC::unserialize(const string
&base
, Checkpoint
*cp
,
172 const string
§ion
)
174 paramIn(cp
, section
, base
+ ".addr", addr
);
175 arrayParamIn(cp
, section
, base
+ ".clock_data", clock_data
,
177 paramIn(cp
, section
, base
+ ".stat_regA", stat_regA
);
178 paramIn(cp
, section
, base
+ ".stat_regB", stat_regB
);
180 // We're not unserializing the event here, but we need to
181 // rescehedule the event since curTick was moved forward by the
183 event
.reschedule(curTick
+ event
.interval
);
186 MaltaIO::RTC::RTCEvent::RTCEvent(Malta
*t
, Tick i
)
187 : Event(&mainEventQueue
), malta(t
), interval(i
)
189 DPRINTF(MC146818
, "RTC Event Initilizing\n");
190 warn("MaltaIO::RTC::RTCEvent::process() RTC interrupt has been disabled.");
191 //schedule(curTick + interval);
195 MaltaIO::RTC::RTCEvent::scheduleIntr()
197 panic("MaltaIO::RTC::RTCEvent::scheduleIntr() has not been implemented for malta");
198 //schedule(curTick + interval);
202 MaltaIO::RTC::RTCEvent::process()
204 DPRINTF(MC146818
, "RTC Timer Interrupt\n");
205 schedule(curTick
+ interval
);
206 //Actually interrupt the processor here
207 malta
->cchip
->postRTC();
211 MaltaIO::RTC::RTCEvent::description() const
213 return "malta RTC interrupt";
216 MaltaIO::PITimer::PITimer(const string
&name
)
217 : _name(name
), counter0(name
+ ".counter0"), counter1(name
+ ".counter1"),
218 counter2(name
+ ".counter2")
220 counter
[0] = &counter0
;
221 counter
[1] = &counter0
;
222 counter
[2] = &counter0
;
226 MaltaIO::PITimer::writeControl(const uint8_t data
)
228 panic("MaltoIO::PITimer::writeControl(data) not implemented inside malta_io.cc");
233 sel = GET_CTRL_SEL(data);
235 if (sel == PIT_READ_BACK)
236 panic("PITimer Read-Back Command is not implemented.\n");
238 rw = GET_CTRL_RW(data);
240 if (rw == PIT_RW_LATCH_COMMAND)
241 counter[sel]->latchCount();
243 counter[sel]->setRW(rw);
244 counter[sel]->setMode(GET_CTRL_MODE(data));
245 counter[sel]->setBCD(GET_CTRL_BCD(data));
251 MaltaIO::PITimer::serialize(const string
&base
, ostream
&os
)
253 // serialize the counters
254 counter0
.serialize(base
+ ".counter0", os
);
255 counter1
.serialize(base
+ ".counter1", os
);
256 counter2
.serialize(base
+ ".counter2", os
);
260 MaltaIO::PITimer::unserialize(const string
&base
, Checkpoint
*cp
,
261 const string
§ion
)
263 // unserialze the counters
264 counter0
.unserialize(base
+ ".counter0", cp
, section
);
265 counter1
.unserialize(base
+ ".counter1", cp
, section
);
266 counter2
.unserialize(base
+ ".counter2", cp
, section
);
269 MaltaIO::PITimer::Counter::Counter(const string
&name
)
270 : _name(name
), event(this), count(0), latched_count(0), period(0),
271 mode(0), output_high(false), latch_on(false), read_byte(LSB
),
278 MaltaIO::PITimer::Counter::latchCount()
280 panic("MaltoIO::PITimer::latchCount(...) not implemented inside malta_io.cc");
281 // behave like a real latch
286 latched_count = count;
292 MaltaIO::PITimer::Counter::read()
294 panic("MaltoIO::PITimer::Count::read(...) not implemented inside malta_io.cc");
301 return (uint8_t)latched_count;
306 return latched_count >> 8;
309 panic("Shouldn't be here");
315 return (uint8_t)count;
322 panic("Shouldn't be here");
329 MaltaIO::PITimer::Counter::write(const uint8_t data
)
331 panic("MaltoIO::PITimer::Counter::write(...) not implemented inside malta_io.cc");
333 switch (write_byte) {
335 count = (count & 0xFF00) | data;
337 if (event.scheduled())
344 count = (count & 0x00FF) | (data << 8);
348 DPRINTF(Malta, "Timer set to curTick + %d\n",
349 count * event.interval);
350 event.schedule(curTick + count * event.interval);
359 MaltaIO::PITimer::Counter::setRW(int rw_val
)
361 panic("MaltoIO::PITimer::Counter::setRW(...) not implemented inside malta_io.cc");
363 if (rw_val != PIT_RW_16BIT)
364 panic("Only LSB/MSB read/write is implemented.\n");
369 MaltaIO::PITimer::Counter::setMode(int mode_val
)
371 panic("MaltoIO::PITimer::Counter::setMode(...) not implemented inside malta_io.cc");
373 if(mode_val != PIT_MODE_INTTC && mode_val != PIT_MODE_RATEGEN &&
374 mode_val != PIT_MODE_SQWAVE)
375 panic("PIT mode %#x is not implemented: \n", mode_val);
382 MaltaIO::PITimer::Counter::setBCD(int bcd_val
)
384 panic("MaltoIO::PITimer::Counter::setBCD(...) not implemented inside malta_io.cc");
386 if (bcd_val != PIT_BCD_FALSE)
387 panic("PITimer does not implement BCD counts.\n");
392 MaltaIO::PITimer::Counter::outputHigh()
394 panic("MaltoIO::PITimer::Counter::outputHigh(...) not implemented inside malta_io.cc");
402 MaltaIO::PITimer::Counter::serialize(const string
&base
, ostream
&os
)
404 paramOut(os
, base
+ ".count", count
);
405 paramOut(os
, base
+ ".latched_count", latched_count
);
406 paramOut(os
, base
+ ".period", period
);
407 paramOut(os
, base
+ ".mode", mode
);
408 paramOut(os
, base
+ ".output_high", output_high
);
409 paramOut(os
, base
+ ".latch_on", latch_on
);
410 paramOut(os
, base
+ ".read_byte", read_byte
);
411 paramOut(os
, base
+ ".write_byte", write_byte
);
414 if (event
.scheduled())
415 event_tick
= event
.when();
416 paramOut(os
, base
+ ".event_tick", event_tick
);
420 MaltaIO::PITimer::Counter::unserialize(const string
&base
, Checkpoint
*cp
,
421 const string
§ion
)
423 paramIn(cp
, section
, base
+ ".count", count
);
424 paramIn(cp
, section
, base
+ ".latched_count", latched_count
);
425 paramIn(cp
, section
, base
+ ".period", period
);
426 paramIn(cp
, section
, base
+ ".mode", mode
);
427 paramIn(cp
, section
, base
+ ".output_high", output_high
);
428 paramIn(cp
, section
, base
+ ".latch_on", latch_on
);
429 paramIn(cp
, section
, base
+ ".read_byte", read_byte
);
430 paramIn(cp
, section
, base
+ ".write_byte", write_byte
);
433 paramIn(cp
, section
, base
+ ".event_tick", event_tick
);
435 event
.schedule(event_tick
);
438 MaltaIO::PITimer::Counter::CounterEvent::CounterEvent(Counter
* c_ptr
)
439 : Event(&mainEventQueue
)
441 interval
= (Tick
)(Clock::Float::s
/ 1193180.0);
446 MaltaIO::PITimer::Counter::CounterEvent::process()
448 panic("MaltaIO::PITimer::Counter::CounterEvent::process(...) not implemented inside malta_io.cc");
450 DPRINTF(Malta, "Timer Interrupt\n");
451 switch (counter->mode) {
453 counter->output_high = true;
454 case PIT_MODE_RATEGEN:
455 case PIT_MODE_SQWAVE:
458 panic("Unimplemented PITimer mode.\n");
464 MaltaIO::PITimer::Counter::CounterEvent::description() const
466 return "malta 8254 Interval timer";
469 MaltaIO::MaltaIO(Params
*p
)
470 : BasicPioDevice(p
), malta(p
->malta
), pitimer(p
->name
+ "pitimer"),
471 rtc(p
->name
+ ".rtc", p
->malta
, p
->frequency
)
475 // set the back pointer from malta to myself
480 picInterrupting
= false;
484 MaltaIO::frequency() const
486 return Clock::Frequency
/ params()->frequency
;
490 MaltaIO::read(PacketPtr pkt
)
492 panic("MaltaIO::read(...) not implemented inside malta_io.cc");
495 assert(pkt->result == Packet::Unknown);
496 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
498 Addr daddr = pkt->getAddr() - pioAddr;
500 DPRINTF(Malta, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(),
501 pkt->getSize(), daddr);
505 if (pkt->getSize() == sizeof(uint8_t)) {
508 case TSDEV_PIC1_MASK:
511 case TSDEV_PIC2_MASK:
515 // !!! If this is modified 64bit case needs to be too
516 // Pal code has to do a 64 bit physical read because there is
517 // no load physical byte instruction
521 // PIC2 not implemnted... just return 0
524 case TSDEV_TMR0_DATA:
525 pkt->set(pitimer.counter0.read());
527 case TSDEV_TMR1_DATA:
528 pkt->set(pitimer.counter1.read());
530 case TSDEV_TMR2_DATA:
531 pkt->set(pitimer.counter2.read());
534 pkt->set(rtc.readData());
536 case TSDEV_CTRL_PORTB:
537 if (pitimer.counter2.outputHigh())
538 pkt->set(PORTB_SPKR_HIGH);
543 panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize());
545 } else if (pkt->getSize() == sizeof(uint64_t)) {
546 if (daddr == TSDEV_PIC1_ISR)
547 pkt->set<uint64_t>(picr);
549 panic("I/O Read - invalid addr - va %#x size %d\n",
550 pkt->getAddr(), pkt->getSize());
552 panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
554 pkt->result = Packet::Success;
560 MaltaIO::write(PacketPtr pkt
)
562 panic("MaltaIO::write(...) not implemented inside malta_io.cc");
565 assert(pkt->result == Packet::Unknown);
566 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
567 Addr daddr = pkt->getAddr() - pioAddr;
569 DPRINTF(Malta, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
570 pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>());
572 assert(pkt->getSize() == sizeof(uint8_t));
573 warn ("GOT HERE daddr=0x%x\n", daddr);
575 case TSDEV_PIC1_MASK:
576 mask1 = ~(pkt->get<uint8_t>());
577 if ((picr & mask1) && !picInterrupting) {
578 picInterrupting = true;
579 malta->cchip->postDRIR(55);
580 DPRINTF(Malta, "posting pic interrupt to cchip\n");
582 if ((!(picr & mask1)) && picInterrupting) {
583 picInterrupting = false;
584 malta->cchip->clearDRIR(55);
585 DPRINTF(Malta, "clearing pic interrupt\n");
588 case TSDEV_PIC2_MASK:
589 mask2 = pkt->get<uint8_t>();
590 //PIC2 Not implemented to interrupt
593 // clear the interrupt on the PIC
594 picr &= ~(1 << (pkt->get<uint8_t>() & 0xF));
596 malta->cchip->clearDRIR(55);
598 case TSDEV_DMA1_MODE:
599 mode1 = pkt->get<uint8_t>();
601 case TSDEV_DMA2_MODE:
602 mode2 = pkt->get<uint8_t>();
604 case TSDEV_TMR0_DATA:
605 pitimer.counter0.write(pkt->get<uint8_t>());
607 case TSDEV_TMR1_DATA:
608 pitimer.counter1.write(pkt->get<uint8_t>());
610 case TSDEV_TMR2_DATA:
611 pitimer.counter2.write(pkt->get<uint8_t>());
614 pitimer.writeControl(pkt->get<uint8_t>());
617 rtc.writeAddr(pkt->get<uint8_t>());
620 rtc.writeData(pkt->get<uint8_t>());
623 case TSDEV_DMA1_CMND:
624 case TSDEV_DMA2_CMND:
625 case TSDEV_DMA1_MMASK:
626 case TSDEV_DMA2_MMASK:
628 case TSDEV_DMA1_RESET:
629 case TSDEV_DMA2_RESET:
630 case TSDEV_DMA1_MASK:
631 case TSDEV_DMA2_MASK:
632 case TSDEV_CTRL_PORTB:
635 panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>());
638 pkt->result = Packet::Success;
644 MaltaIO::postIntr(uint8_t interrupt
)
646 malta
->cchip
->postIntr(interrupt
);
647 DPRINTF(Malta
, "posting pic interrupt to cchip\n");
651 MaltaIO::clearIntr(uint8_t interrupt
)
653 malta
->cchip
->clearIntr(interrupt
);
654 DPRINTF(Malta
, "posting pic interrupt to cchip\n");
658 MaltaIO::serialize(ostream
&os
)
660 SERIALIZE_SCALAR(timerData
);
661 SERIALIZE_SCALAR(mask1
);
662 SERIALIZE_SCALAR(mask2
);
663 SERIALIZE_SCALAR(mode1
);
664 SERIALIZE_SCALAR(mode2
);
665 SERIALIZE_SCALAR(picr
);
666 SERIALIZE_SCALAR(picInterrupting
);
668 // Serialize the timers
669 pitimer
.serialize("pitimer", os
);
670 rtc
.serialize("rtc", os
);
674 MaltaIO::unserialize(Checkpoint
*cp
, const string
§ion
)
676 UNSERIALIZE_SCALAR(timerData
);
677 UNSERIALIZE_SCALAR(mask1
);
678 UNSERIALIZE_SCALAR(mask2
);
679 UNSERIALIZE_SCALAR(mode1
);
680 UNSERIALIZE_SCALAR(mode2
);
681 UNSERIALIZE_SCALAR(picr
);
682 UNSERIALIZE_SCALAR(picInterrupting
);
684 // Unserialize the timers
685 pitimer
.unserialize("pitimer", cp
, section
);
686 rtc
.unserialize("rtc", cp
, section
);
690 MaltaIOParams::create()
692 return new MaltaIO(this);