2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
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13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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40 #include "base/trace.hh"
41 #include "config/the_isa.hh"
42 #include "dev/mips/malta_pchip.hh"
43 #include "dev/mips/maltareg.h"
44 #include "dev/mips/malta.hh"
45 #include "mem/packet.hh"
46 #include "mem/packet_access.hh"
47 #include "sim/system.hh"
50 using namespace TheISA
;
52 MaltaPChip::MaltaPChip(const Params
*p
)
57 for (int i
= 0; i
< 4; i
++) {
63 // initialize pchip control register
64 pctl
= (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
66 //Set back pointer in malta
67 p
->malta
->pchip
= this;
71 MaltaPChip::read(PacketPtr pkt
)
73 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
76 Addr daddr
= (pkt
->getAddr() - pioAddr
) >> 6;;
77 assert(pkt
->getSize() == sizeof(uint64_t));
80 DPRINTF(Malta
, "read va=%#x size=%d\n", pkt
->getAddr(), pkt
->getSize());
123 panic("PC_PLAT not implemented\n");
125 panic("PC_RES not implemented\n");
126 case TSDEV_PC_PERROR
:
127 pkt
->set((uint64_t)0x00);
129 case TSDEV_PC_PERRMASK
:
130 pkt
->set((uint64_t)0x00);
132 case TSDEV_PC_PERRSET
:
133 panic("PC_PERRSET not implemented\n");
135 panic("PC_TLBIV not implemented\n");
137 pkt
->set((uint64_t)0x00); // shouldn't be readable, but linux
139 case TSDEV_PC_PMONCTL
:
140 panic("PC_PMONCTL not implemented\n");
141 case TSDEV_PC_PMONCNT
:
142 panic("PC_PMONCTN not implemented\n");
144 panic("Default in PChip Read reached reading 0x%x\n", daddr
);
146 pkt
->makeAtomicResponse();
152 MaltaPChip::write(PacketPtr pkt
)
154 assert(pkt
->getAddr() >= pioAddr
&& pkt
->getAddr() < pioAddr
+ pioSize
);
155 Addr daddr
= (pkt
->getAddr() - pioAddr
) >> 6;
157 assert(pkt
->getSize() == sizeof(uint64_t));
159 DPRINTF(Malta
, "write - va=%#x size=%d \n", pkt
->getAddr(), pkt
->getSize());
163 wsba
[0] = pkt
->get
<uint64_t>();
166 wsba
[1] = pkt
->get
<uint64_t>();
169 wsba
[2] = pkt
->get
<uint64_t>();
172 wsba
[3] = pkt
->get
<uint64_t>();
175 wsm
[0] = pkt
->get
<uint64_t>();
178 wsm
[1] = pkt
->get
<uint64_t>();
181 wsm
[2] = pkt
->get
<uint64_t>();
184 wsm
[3] = pkt
->get
<uint64_t>();
187 tba
[0] = pkt
->get
<uint64_t>();
190 tba
[1] = pkt
->get
<uint64_t>();
193 tba
[2] = pkt
->get
<uint64_t>();
196 tba
[3] = pkt
->get
<uint64_t>();
199 pctl
= pkt
->get
<uint64_t>();
202 panic("PC_PLAT not implemented\n");
204 panic("PC_RES not implemented\n");
205 case TSDEV_PC_PERROR
:
207 case TSDEV_PC_PERRMASK
:
208 panic("PC_PERRMASK not implemented\n");
209 case TSDEV_PC_PERRSET
:
210 panic("PC_PERRSET not implemented\n");
212 panic("PC_TLBIV not implemented\n");
214 break; // value ignored, supposted to invalidate SG TLB
215 case TSDEV_PC_PMONCTL
:
216 panic("PC_PMONCTL not implemented\n");
217 case TSDEV_PC_PMONCNT
:
218 panic("PC_PMONCTN not implemented\n");
220 panic("Default in PChip write reached reading 0x%x\n", daddr
);
224 pkt
->makeAtomicResponse();
228 #define DMA_ADDR_MASK ULL(0x3ffffffff)
231 MaltaPChip::translatePciToDma(Addr busAddr
)
233 // compare the address to the window base registers
234 uint64_t tbaMask
= 0;
237 uint64_t windowMask
= 0;
238 uint64_t windowBase
= 0;
240 uint64_t pteEntry
= 0;
246 DPRINTF(IdeDisk
, "Translation for bus address: %#x\n", busAddr
);
247 for (int i
= 0; i
< 4; i
++) {
248 DPRINTF(IdeDisk
, "(%d) base:%#x mask:%#x\n",
251 windowBase
= wsba
[i
];
252 windowMask
= ~wsm
[i
] & (ULL(0xfff) << 20);
254 if ((busAddr
& windowMask
) == (windowBase
& windowMask
)) {
255 DPRINTF(IdeDisk
, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
256 i
, windowBase
, windowMask
, (busAddr
& windowMask
),
257 (windowBase
& windowMask
));
262 for (int i
= 0; i
< 4; i
++) {
264 windowBase
= wsba
[i
];
265 windowMask
= ~wsm
[i
] & (ULL(0xfff) << 20);
267 if ((busAddr
& windowMask
) == (windowBase
& windowMask
)) {
269 if (wsba
[i
] & 0x1) { // see if enabled
270 if (wsba
[i
] & 0x2) { // see if SG bit is set
272 This currently is faked by just doing a direct
273 read from memory, however, to be realistic, this
274 needs to actually do a bus transaction. The process
275 is explained in the malta documentation on page
276 10-12 and basically munges the address to look up a
277 PTE from a table in memory and then uses that mapping
278 to create an address for the SG page
281 tbaMask
= ~(((wsm
[i
] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
282 baMask
= (wsm
[i
] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
283 pteAddr
= (tba
[i
] & tbaMask
) | ((busAddr
& baMask
) >> 10);
285 pioPort
->readBlob(pteAddr
, (uint8_t*)&pteEntry
, sizeof(uint64_t));
287 dmaAddr
= ((pteEntry
& ~ULL(0x1)) << 12) | (busAddr
& ULL(0x1fff));
290 baMask
= (wsm
[i
] & (ULL(0xfff) << 20)) | ULL(0xfffff);
292 dmaAddr
= (tba
[i
] & tbaMask
) | (busAddr
& baMask
);
295 return (dmaAddr
& DMA_ADDR_MASK
);
300 // if no match was found, then return the original address
304 MaltaPChip::calcConfigAddr(int bus
, int dev
, int func
)
310 return MaltaPciBus0Config
| (func
<< 8) | (dev
<< 11);
316 MaltaPChip::serialize(std::ostream
&os
)
318 SERIALIZE_SCALAR(pctl
);
319 SERIALIZE_ARRAY(wsba
, 4);
320 SERIALIZE_ARRAY(wsm
, 4);
321 SERIALIZE_ARRAY(tba
, 4);
325 MaltaPChip::unserialize(Checkpoint
*cp
, const std::string
§ion
)
327 UNSERIALIZE_SCALAR(pctl
);
328 UNSERIALIZE_ARRAY(wsba
, 4);
329 UNSERIALIZE_ARRAY(wsm
, 4);
330 UNSERIALIZE_ARRAY(tba
, 4);
335 MaltaPChipParams::create()
337 return new MaltaPChip(this);