1 # Copyright (c) 2015 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
22 # documentation and/or other materials provided with the distribution;
23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 # Authors: Nathan Binkert
41 from m5
.defines
import buildEnv
42 from m5
.SimObject
import SimObject
43 from m5
.params
import *
44 from m5
.proxy
import *
45 from PciDevice
import PciDevice
47 class EtherObject(SimObject
):
50 cxx_header
= "dev/net/etherobject.hh"
52 class EtherLink(EtherObject
):
54 cxx_header
= "dev/net/etherlink.hh"
55 int0
= SlavePort("interface 0")
56 int1
= SlavePort("interface 1")
57 delay
= Param
.Latency('0us', "packet transmit delay")
58 delay_var
= Param
.Latency('0ns', "packet transmit delay variability")
59 speed
= Param
.NetworkBandwidth('1Gbps', "link speed")
60 dump
= Param
.EtherDump(NULL
, "dump object")
62 class DistEtherLink(EtherObject
):
63 type = 'DistEtherLink'
64 cxx_header
= "dev/net/dist_etherlink.hh"
65 int0
= SlavePort("interface 0")
66 delay
= Param
.Latency('0us', "packet transmit delay")
67 delay_var
= Param
.Latency('0ns', "packet transmit delay variability")
68 speed
= Param
.NetworkBandwidth('1Gbps', "link speed")
69 dump
= Param
.EtherDump(NULL
, "dump object")
70 dist_rank
= Param
.UInt32('0', "Rank of this gem5 process (dist run)")
71 dist_size
= Param
.UInt32('1', "Number of gem5 processes (dist run)")
72 sync_start
= Param
.Latency('5200000000000t', "first dist sync barrier")
73 sync_repeat
= Param
.Latency('10us', "dist sync barrier repeat")
74 server_name
= Param
.String('localhost', "Message server name")
75 server_port
= Param
.UInt32('2200', "Message server port")
76 is_switch
= Param
.Bool(False, "true if this a link in etherswitch")
77 dist_sync_on_pseudo_op
= Param
.Bool(False, "Start sync with pseudo_op")
78 num_nodes
= Param
.UInt32('2', "Number of simulate nodes")
80 class EtherBus(EtherObject
):
82 cxx_header
= "dev/net/etherbus.hh"
83 loopback
= Param
.Bool(True, "send packet back to the sending interface")
84 dump
= Param
.EtherDump(NULL
, "dump object")
85 speed
= Param
.NetworkBandwidth('100Mbps', "bus speed in bits per second")
87 class EtherSwitch(EtherObject
):
89 cxx_header
= "dev/net/etherswitch.hh"
90 dump
= Param
.EtherDump(NULL
, "dump object")
91 fabric_speed
= Param
.NetworkBandwidth('10Gbps', "switch fabric speed in bits "
93 interface
= VectorMasterPort("Ethernet Interface")
94 output_buffer_size
= Param
.MemorySize('1MB', "size of output port buffers")
95 delay
= Param
.Latency('0us', "packet transmit delay")
96 delay_var
= Param
.Latency('0ns', "packet transmit delay variability")
97 time_to_live
= Param
.Latency('10ms', "time to live of MAC address maping")
99 class EtherTapBase(EtherObject
):
100 type = 'EtherTapBase'
102 cxx_header
= "dev/net/ethertap.hh"
103 bufsz
= Param
.Int(10000, "tap buffer size")
104 dump
= Param
.EtherDump(NULL
, "dump object")
105 tap
= SlavePort("Ethernet interface to connect to gem5's network")
107 if buildEnv
['USE_TUNTAP']:
108 class EtherTap(EtherTapBase
):
110 cxx_header
= "dev/net/ethertap.hh"
111 tun_clone_device
= Param
.String('/dev/net/tun',
112 "Path to the tun clone device node")
113 tap_device_name
= Param
.String('gem5-tap', "Tap device name")
115 class EtherTapStub(EtherTapBase
):
116 type = 'EtherTapStub'
117 cxx_header
= "dev/net/ethertap.hh"
118 port
= Param
.UInt16(3500, "Port helper should send packets to")
120 class EtherDump(SimObject
):
122 cxx_header
= "dev/net/etherdump.hh"
123 file = Param
.String("dump file")
124 maxlen
= Param
.Int(96, "max portion of packet data to dump")
126 class EtherDevice(PciDevice
):
129 cxx_header
= "dev/net/etherdevice.hh"
130 interface
= MasterPort("Ethernet Interface")
132 class IGbE(EtherDevice
):
133 # Base class for two IGbE adapters listed above
135 cxx_header
= "dev/net/i8254xGBe.hh"
136 hardware_address
= Param
.EthernetAddr(NextEthernetAddr
,
137 "Ethernet Hardware Address")
138 rx_fifo_size
= Param
.MemorySize('384kB', "Size of the rx FIFO")
139 tx_fifo_size
= Param
.MemorySize('384kB', "Size of the tx FIFO")
140 rx_desc_cache_size
= Param
.Int(64,
141 "Number of enteries in the rx descriptor cache")
142 tx_desc_cache_size
= Param
.Int(64,
143 "Number of enteries in the rx descriptor cache")
146 SubsystemVendorID
= 0x8086
157 MaximumLatency
= 0x00
162 wb_delay
= Param
.Latency('10ns', "delay before desc writeback occurs")
163 fetch_delay
= Param
.Latency('10ns', "delay before desc fetch occurs")
164 fetch_comp_delay
= Param
.Latency('10ns', "delay after desc fetch occurs")
165 wb_comp_delay
= Param
.Latency('10ns', "delay after desc wb occurs")
166 tx_read_delay
= Param
.Latency('0ns', "delay after tx dma read")
167 rx_write_delay
= Param
.Latency('0ns', "delay after rx dma read")
168 phy_pid
= Param
.UInt16("Phy PID that corresponds to device ID")
169 phy_epid
= Param
.UInt16("Phy EPID that corresponds to device ID")
171 class IGbE_e1000(IGbE
):
172 # Older Intel 8254x based gigabit ethernet adapter
173 # Uses Intel e1000 driver
178 class IGbE_igb(IGbE
):
179 # Newer Intel 8257x based gigabit ethernet adapter
180 # Uses Intel igb driver and in theory supports packet splitting and LRO
185 class EtherDevBase(EtherDevice
):
186 type = 'EtherDevBase'
188 cxx_header
= "dev/net/etherdevice.hh"
190 hardware_address
= Param
.EthernetAddr(NextEthernetAddr
,
191 "Ethernet Hardware Address")
193 dma_read_delay
= Param
.Latency('0us', "fixed delay for dma reads")
194 dma_read_factor
= Param
.Latency('0us', "multiplier for dma reads")
195 dma_write_delay
= Param
.Latency('0us', "fixed delay for dma writes")
196 dma_write_factor
= Param
.Latency('0us', "multiplier for dma writes")
198 rx_delay
= Param
.Latency('1us', "Receive Delay")
199 tx_delay
= Param
.Latency('1us', "Transmit Delay")
200 rx_fifo_size
= Param
.MemorySize('512kB', "max size of rx fifo")
201 tx_fifo_size
= Param
.MemorySize('512kB', "max size of tx fifo")
203 rx_filter
= Param
.Bool(True, "Enable Receive Filter")
204 intr_delay
= Param
.Latency('10us', "Interrupt propagation delay")
205 rx_thread
= Param
.Bool(False, "dedicated kernel thread for transmit")
206 tx_thread
= Param
.Bool(False, "dedicated kernel threads for receive")
207 rss
= Param
.Bool(False, "Receive Side Scaling")
209 class NSGigE(EtherDevBase
):
211 cxx_header
= "dev/net/ns_gige.hh"
213 dma_data_free
= Param
.Bool(False, "DMA of Data is free")
214 dma_desc_free
= Param
.Bool(False, "DMA of Descriptors is free")
215 dma_no_allocate
= Param
.Bool(True, "Should we allocate cache on read")
229 MaximumLatency
= 0x34
238 class Sinic(EtherDevBase
):
240 cxx_class
= 'Sinic::Device'
241 cxx_header
= "dev/net/sinic.hh"
243 rx_max_copy
= Param
.MemorySize('1514B', "rx max copy")
244 tx_max_copy
= Param
.MemorySize('16kB', "tx max copy")
245 rx_max_intr
= Param
.UInt32(10, "max rx packets per interrupt")
246 rx_fifo_threshold
= Param
.MemorySize('384kB', "rx fifo high threshold")
247 rx_fifo_low_mark
= Param
.MemorySize('128kB', "rx fifo low threshold")
248 tx_fifo_high_mark
= Param
.MemorySize('384kB', "tx fifo high threshold")
249 tx_fifo_threshold
= Param
.MemorySize('128kB', "tx fifo low threshold")
250 virtual_count
= Param
.UInt32(1, "Virtualized SINIC")
251 zero_copy_size
= Param
.UInt32(64, "Bytes to copy if below threshold")
252 zero_copy_threshold
= Param
.UInt32(256,
253 "Only zero copy above this threshold")
254 zero_copy
= Param
.Bool(False, "Zero copy receive")
255 delay_copy
= Param
.Bool(False, "Delayed copy transmit")
256 virtual_addr
= Param
.Bool(False, "Virtual addressing")
270 MaximumLatency
= 0x34