dd878e2955c8f8b8190917674fbf5d9016180ac0
1 # Copyright (c) 2015 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
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13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
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25 # this software without specific prior written permission.
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39 from m5
.defines
import buildEnv
40 from m5
.SimObject
import SimObject
41 from m5
.params
import *
42 from m5
.proxy
import *
43 from m5
.objects
.PciDevice
import PciDevice
, PciIoBar
, PciMemBar
45 ETHERNET_ROLE
= 'ETHERNET'
46 Port
.compat(ETHERNET_ROLE
, ETHERNET_ROLE
)
49 def __init__(self
, desc
):
50 super(EtherInt
, self
).__init
__(ETHERNET_ROLE
, desc
)
52 class VectorEtherInt(VectorPort
):
53 def __init__(self
, desc
):
54 super(VectorEtherInt
, self
).__init
__(ETHERNET_ROLE
, desc
)
56 class EtherLink(SimObject
):
58 cxx_header
= "dev/net/etherlink.hh"
59 int0
= EtherInt("interface 0")
60 int1
= EtherInt("interface 1")
61 delay
= Param
.Latency('0us', "packet transmit delay")
62 delay_var
= Param
.Latency('0ns', "packet transmit delay variability")
63 speed
= Param
.NetworkBandwidth('1Gbps', "link speed")
64 dump
= Param
.EtherDump(NULL
, "dump object")
66 class DistEtherLink(SimObject
):
67 type = 'DistEtherLink'
68 cxx_header
= "dev/net/dist_etherlink.hh"
69 int0
= EtherInt("interface 0")
70 delay
= Param
.Latency('0us', "packet transmit delay")
71 delay_var
= Param
.Latency('0ns', "packet transmit delay variability")
72 speed
= Param
.NetworkBandwidth('1Gbps', "link speed")
73 dump
= Param
.EtherDump(NULL
, "dump object")
74 dist_rank
= Param
.UInt32('0', "Rank of this gem5 process (dist run)")
75 dist_size
= Param
.UInt32('1', "Number of gem5 processes (dist run)")
76 sync_start
= Param
.Latency('5200000000000t', "first dist sync barrier")
77 sync_repeat
= Param
.Latency('10us', "dist sync barrier repeat")
78 server_name
= Param
.String('localhost', "Message server name")
79 server_port
= Param
.UInt32('2200', "Message server port")
80 is_switch
= Param
.Bool(False, "true if this a link in etherswitch")
81 dist_sync_on_pseudo_op
= Param
.Bool(False, "Start sync with pseudo_op")
82 num_nodes
= Param
.UInt32('2', "Number of simulate nodes")
84 class EtherBus(SimObject
):
86 cxx_header
= "dev/net/etherbus.hh"
87 loopback
= Param
.Bool(True, "send packet back to the sending interface")
88 dump
= Param
.EtherDump(NULL
, "dump object")
89 speed
= Param
.NetworkBandwidth('100Mbps', "bus speed in bits per second")
91 class EtherSwitch(SimObject
):
93 cxx_header
= "dev/net/etherswitch.hh"
94 dump
= Param
.EtherDump(NULL
, "dump object")
95 fabric_speed
= Param
.NetworkBandwidth('10Gbps', "switch fabric speed in bits "
97 interface
= VectorEtherInt("Ethernet Interface")
98 output_buffer_size
= Param
.MemorySize('1MB', "size of output port buffers")
99 delay
= Param
.Latency('0us', "packet transmit delay")
100 delay_var
= Param
.Latency('0ns', "packet transmit delay variability")
101 time_to_live
= Param
.Latency('10ms', "time to live of MAC address maping")
103 class EtherTapBase(SimObject
):
104 type = 'EtherTapBase'
106 cxx_header
= "dev/net/ethertap.hh"
107 bufsz
= Param
.Int(10000, "tap buffer size")
108 dump
= Param
.EtherDump(NULL
, "dump object")
109 tap
= EtherInt("Ethernet interface to connect to gem5's network")
111 if buildEnv
['USE_TUNTAP']:
112 class EtherTap(EtherTapBase
):
114 cxx_header
= "dev/net/ethertap.hh"
115 tun_clone_device
= Param
.String('/dev/net/tun',
116 "Path to the tun clone device node")
117 tap_device_name
= Param
.String('gem5-tap', "Tap device name")
119 class EtherTapStub(EtherTapBase
):
120 type = 'EtherTapStub'
121 cxx_header
= "dev/net/ethertap.hh"
122 port
= Param
.UInt16(3500, "Port helper should send packets to")
124 class EtherDump(SimObject
):
126 cxx_header
= "dev/net/etherdump.hh"
127 file = Param
.String("dump file")
128 maxlen
= Param
.Int(96, "max portion of packet data to dump")
130 class EtherDevice(PciDevice
):
133 cxx_header
= "dev/net/etherdevice.hh"
134 interface
= EtherInt("Ethernet Interface")
136 class IGbE(EtherDevice
):
137 # Base class for two IGbE adapters listed above
139 cxx_header
= "dev/net/i8254xGBe.hh"
140 hardware_address
= Param
.EthernetAddr(NextEthernetAddr
,
141 "Ethernet Hardware Address")
142 rx_fifo_size
= Param
.MemorySize('384kB', "Size of the rx FIFO")
143 tx_fifo_size
= Param
.MemorySize('384kB', "Size of the tx FIFO")
144 rx_desc_cache_size
= Param
.Int(64,
145 "Number of enteries in the rx descriptor cache")
146 tx_desc_cache_size
= Param
.Int(64,
147 "Number of enteries in the rx descriptor cache")
150 SubsystemVendorID
= 0x8086
155 BAR0
= PciMemBar(size
='128kB')
156 MaximumLatency
= 0x00
160 wb_delay
= Param
.Latency('10ns', "delay before desc writeback occurs")
161 fetch_delay
= Param
.Latency('10ns', "delay before desc fetch occurs")
162 fetch_comp_delay
= Param
.Latency('10ns', "delay after desc fetch occurs")
163 wb_comp_delay
= Param
.Latency('10ns', "delay after desc wb occurs")
164 tx_read_delay
= Param
.Latency('0ns', "delay after tx dma read")
165 rx_write_delay
= Param
.Latency('0ns', "delay after rx dma read")
166 phy_pid
= Param
.UInt16("Phy PID that corresponds to device ID")
167 phy_epid
= Param
.UInt16("Phy EPID that corresponds to device ID")
169 class IGbE_e1000(IGbE
):
170 # Older Intel 8254x based gigabit ethernet adapter
171 # Uses Intel e1000 driver
176 class IGbE_igb(IGbE
):
177 # Newer Intel 8257x based gigabit ethernet adapter
178 # Uses Intel igb driver and in theory supports packet splitting and LRO
183 class EtherDevBase(EtherDevice
):
184 type = 'EtherDevBase'
186 cxx_header
= "dev/net/etherdevice.hh"
188 hardware_address
= Param
.EthernetAddr(NextEthernetAddr
,
189 "Ethernet Hardware Address")
191 dma_read_delay
= Param
.Latency('0us', "fixed delay for dma reads")
192 dma_read_factor
= Param
.Latency('0us', "multiplier for dma reads")
193 dma_write_delay
= Param
.Latency('0us', "fixed delay for dma writes")
194 dma_write_factor
= Param
.Latency('0us', "multiplier for dma writes")
196 rx_delay
= Param
.Latency('1us', "Receive Delay")
197 tx_delay
= Param
.Latency('1us', "Transmit Delay")
198 rx_fifo_size
= Param
.MemorySize('512kB', "max size of rx fifo")
199 tx_fifo_size
= Param
.MemorySize('512kB', "max size of tx fifo")
201 rx_filter
= Param
.Bool(True, "Enable Receive Filter")
202 intr_delay
= Param
.Latency('10us', "Interrupt propagation delay")
203 rx_thread
= Param
.Bool(False, "dedicated kernel thread for transmit")
204 tx_thread
= Param
.Bool(False, "dedicated kernel threads for receive")
205 rss
= Param
.Bool(False, "Receive Side Scaling")
207 class NSGigE(EtherDevBase
):
209 cxx_header
= "dev/net/ns_gige.hh"
211 dma_data_free
= Param
.Bool(False, "DMA of Data is free")
212 dma_desc_free
= Param
.Bool(False, "DMA of Descriptors is free")
213 dma_no_allocate
= Param
.Bool(True, "Should we allocate cache on read")
221 BARs
= (PciIoBar(size
='256B'), PciMemBar(size
='4kB'))
222 MaximumLatency
= 0x34
229 class Sinic(EtherDevBase
):
231 cxx_class
= 'Sinic::Device'
232 cxx_header
= "dev/net/sinic.hh"
234 rx_max_copy
= Param
.MemorySize('1514B', "rx max copy")
235 tx_max_copy
= Param
.MemorySize('16kB', "tx max copy")
236 rx_max_intr
= Param
.UInt32(10, "max rx packets per interrupt")
237 rx_fifo_threshold
= Param
.MemorySize('384kB', "rx fifo high threshold")
238 rx_fifo_low_mark
= Param
.MemorySize('128kB', "rx fifo low threshold")
239 tx_fifo_high_mark
= Param
.MemorySize('384kB', "tx fifo high threshold")
240 tx_fifo_threshold
= Param
.MemorySize('128kB', "tx fifo low threshold")
241 virtual_count
= Param
.UInt32(1, "Virtualized SINIC")
242 zero_copy_size
= Param
.UInt32(64, "Bytes to copy if below threshold")
243 zero_copy_threshold
= Param
.UInt32(256,
244 "Only zero copy above this threshold")
245 zero_copy
= Param
.Bool(False, "Zero copy receive")
246 delay_copy
= Param
.Bool(False, "Delayed copy transmit")
247 virtual_addr
= Param
.Bool(False, "Virtual addressing")
255 BARs
= PciMemBar(size
='64kB')
256 MaximumLatency
= 0x34