dev: Consistently use ISO prefixes
[gem5.git] / src / dev / net / Ethernet.py
1 # Copyright (c) 2015 ARM Limited
2 # All rights reserved.
3 #
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
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13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
14 # All rights reserved.
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38
39 from m5.defines import buildEnv
40 from m5.SimObject import SimObject
41 from m5.params import *
42 from m5.proxy import *
43 from m5.objects.PciDevice import PciDevice, PciIoBar, PciMemBar
44
45 ETHERNET_ROLE = 'ETHERNET'
46 Port.compat(ETHERNET_ROLE, ETHERNET_ROLE)
47
48 class EtherInt(Port):
49 def __init__(self, desc):
50 super(EtherInt, self).__init__(ETHERNET_ROLE, desc)
51
52 class VectorEtherInt(VectorPort):
53 def __init__(self, desc):
54 super(VectorEtherInt, self).__init__(ETHERNET_ROLE, desc)
55
56 class EtherLink(SimObject):
57 type = 'EtherLink'
58 cxx_header = "dev/net/etherlink.hh"
59 int0 = EtherInt("interface 0")
60 int1 = EtherInt("interface 1")
61 delay = Param.Latency('0us', "packet transmit delay")
62 delay_var = Param.Latency('0ns', "packet transmit delay variability")
63 speed = Param.NetworkBandwidth('1Gbps', "link speed")
64 dump = Param.EtherDump(NULL, "dump object")
65
66 class DistEtherLink(SimObject):
67 type = 'DistEtherLink'
68 cxx_header = "dev/net/dist_etherlink.hh"
69 int0 = EtherInt("interface 0")
70 delay = Param.Latency('0us', "packet transmit delay")
71 delay_var = Param.Latency('0ns', "packet transmit delay variability")
72 speed = Param.NetworkBandwidth('1Gbps', "link speed")
73 dump = Param.EtherDump(NULL, "dump object")
74 dist_rank = Param.UInt32('0', "Rank of this gem5 process (dist run)")
75 dist_size = Param.UInt32('1', "Number of gem5 processes (dist run)")
76 sync_start = Param.Latency('5200000000000t', "first dist sync barrier")
77 sync_repeat = Param.Latency('10us', "dist sync barrier repeat")
78 server_name = Param.String('localhost', "Message server name")
79 server_port = Param.UInt32('2200', "Message server port")
80 is_switch = Param.Bool(False, "true if this a link in etherswitch")
81 dist_sync_on_pseudo_op = Param.Bool(False, "Start sync with pseudo_op")
82 num_nodes = Param.UInt32('2', "Number of simulate nodes")
83
84 class EtherBus(SimObject):
85 type = 'EtherBus'
86 cxx_header = "dev/net/etherbus.hh"
87 loopback = Param.Bool(True, "send packet back to the sending interface")
88 dump = Param.EtherDump(NULL, "dump object")
89 speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
90
91 class EtherSwitch(SimObject):
92 type = 'EtherSwitch'
93 cxx_header = "dev/net/etherswitch.hh"
94 dump = Param.EtherDump(NULL, "dump object")
95 fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed in "
96 "bits per second")
97 interface = VectorEtherInt("Ethernet Interface")
98 output_buffer_size = Param.MemorySize('1MiB',
99 "size of output port buffers")
100 delay = Param.Latency('0us', "packet transmit delay")
101 delay_var = Param.Latency('0ns', "packet transmit delay variability")
102 time_to_live = Param.Latency('10ms', "time to live of MAC address maping")
103
104 class EtherTapBase(SimObject):
105 type = 'EtherTapBase'
106 abstract = True
107 cxx_header = "dev/net/ethertap.hh"
108 bufsz = Param.Int(10000, "tap buffer size")
109 dump = Param.EtherDump(NULL, "dump object")
110 tap = EtherInt("Ethernet interface to connect to gem5's network")
111
112 if buildEnv['USE_TUNTAP']:
113 class EtherTap(EtherTapBase):
114 type = 'EtherTap'
115 cxx_header = "dev/net/ethertap.hh"
116 tun_clone_device = Param.String('/dev/net/tun',
117 "Path to the tun clone device node")
118 tap_device_name = Param.String('gem5-tap', "Tap device name")
119
120 class EtherTapStub(EtherTapBase):
121 type = 'EtherTapStub'
122 cxx_header = "dev/net/ethertap.hh"
123 port = Param.UInt16(3500, "Port helper should send packets to")
124
125 class EtherDump(SimObject):
126 type = 'EtherDump'
127 cxx_header = "dev/net/etherdump.hh"
128 file = Param.String("dump file")
129 maxlen = Param.Int(96, "max portion of packet data to dump")
130
131 class EtherDevice(PciDevice):
132 type = 'EtherDevice'
133 abstract = True
134 cxx_header = "dev/net/etherdevice.hh"
135 interface = EtherInt("Ethernet Interface")
136
137 class IGbE(EtherDevice):
138 # Base class for two IGbE adapters listed above
139 type = 'IGbE'
140 cxx_header = "dev/net/i8254xGBe.hh"
141 hardware_address = Param.EthernetAddr(NextEthernetAddr,
142 "Ethernet Hardware Address")
143 rx_fifo_size = Param.MemorySize('384KiB', "Size of the rx FIFO")
144 tx_fifo_size = Param.MemorySize('384KiB', "Size of the tx FIFO")
145 rx_desc_cache_size = Param.Int(64,
146 "Number of enteries in the rx descriptor cache")
147 tx_desc_cache_size = Param.Int(64,
148 "Number of enteries in the rx descriptor cache")
149 VendorID = 0x8086
150 SubsystemID = 0x1008
151 SubsystemVendorID = 0x8086
152 Status = 0x0000
153 SubClassCode = 0x00
154 ClassCode = 0x02
155 ProgIF = 0x00
156 BAR0 = PciMemBar(size='128KiB')
157 MaximumLatency = 0x00
158 MinimumGrant = 0xff
159 InterruptLine = 0x1e
160 InterruptPin = 0x01
161 wb_delay = Param.Latency('10ns', "delay before desc writeback occurs")
162 fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs")
163 fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs")
164 wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
165 tx_read_delay = Param.Latency('0ns', "delay after tx dma read")
166 rx_write_delay = Param.Latency('0ns', "delay after rx dma read")
167 phy_pid = Param.UInt16("Phy PID that corresponds to device ID")
168 phy_epid = Param.UInt16("Phy EPID that corresponds to device ID")
169
170 class IGbE_e1000(IGbE):
171 # Older Intel 8254x based gigabit ethernet adapter
172 # Uses Intel e1000 driver
173 DeviceID = 0x1075
174 phy_pid = 0x02A8
175 phy_epid = 0x0380
176
177 class IGbE_igb(IGbE):
178 # Newer Intel 8257x based gigabit ethernet adapter
179 # Uses Intel igb driver and in theory supports packet splitting and LRO
180 DeviceID = 0x10C9
181 phy_pid = 0x0141
182 phy_epid = 0x0CC0
183
184 class EtherDevBase(EtherDevice):
185 type = 'EtherDevBase'
186 abstract = True
187 cxx_header = "dev/net/etherdevice.hh"
188
189 hardware_address = Param.EthernetAddr(NextEthernetAddr,
190 "Ethernet Hardware Address")
191
192 dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
193 dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
194 dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
195 dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
196
197 rx_delay = Param.Latency('1us', "Receive Delay")
198 tx_delay = Param.Latency('1us', "Transmit Delay")
199 rx_fifo_size = Param.MemorySize('512KiB', "max size of rx fifo")
200 tx_fifo_size = Param.MemorySize('512KiB', "max size of tx fifo")
201
202 rx_filter = Param.Bool(True, "Enable Receive Filter")
203 intr_delay = Param.Latency('10us', "Interrupt propagation delay")
204 rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
205 tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
206 rss = Param.Bool(False, "Receive Side Scaling")
207
208 class NSGigE(EtherDevBase):
209 type = 'NSGigE'
210 cxx_header = "dev/net/ns_gige.hh"
211
212 dma_data_free = Param.Bool(False, "DMA of Data is free")
213 dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
214 dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
215
216 VendorID = 0x100B
217 DeviceID = 0x0022
218 Status = 0x0290
219 SubClassCode = 0x00
220 ClassCode = 0x02
221 ProgIF = 0x00
222 BARs = (PciIoBar(size='256B'), PciMemBar(size='4KiB'))
223 MaximumLatency = 0x34
224 MinimumGrant = 0xb0
225 InterruptLine = 0x1e
226 InterruptPin = 0x01
227
228
229
230 class Sinic(EtherDevBase):
231 type = 'Sinic'
232 cxx_class = 'Sinic::Device'
233 cxx_header = "dev/net/sinic.hh"
234
235 rx_max_copy = Param.MemorySize('1514B', "rx max copy")
236 tx_max_copy = Param.MemorySize('16KiB', "tx max copy")
237 rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
238 rx_fifo_threshold = Param.MemorySize('384KiB', "rx fifo high threshold")
239 rx_fifo_low_mark = Param.MemorySize('128KiB', "rx fifo low threshold")
240 tx_fifo_high_mark = Param.MemorySize('384KiB', "tx fifo high threshold")
241 tx_fifo_threshold = Param.MemorySize('128KiB', "tx fifo low threshold")
242 virtual_count = Param.UInt32(1, "Virtualized SINIC")
243 zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
244 zero_copy_threshold = Param.UInt32(256,
245 "Only zero copy above this threshold")
246 zero_copy = Param.Bool(False, "Zero copy receive")
247 delay_copy = Param.Bool(False, "Delayed copy transmit")
248 virtual_addr = Param.Bool(False, "Virtual addressing")
249
250 VendorID = 0x1291
251 DeviceID = 0x1293
252 Status = 0x0290
253 SubClassCode = 0x00
254 ClassCode = 0x02
255 ProgIF = 0x00
256 BARs = PciMemBar(size='64KiB')
257 MaximumLatency = 0x34
258 MinimumGrant = 0xb0
259 InterruptLine = 0x1e
260 InterruptPin = 0x01