1 # Copyright (c) 2015 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
22 # documentation and/or other materials provided with the distribution;
23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 from m5
.defines
import buildEnv
40 from m5
.SimObject
import SimObject
41 from m5
.params
import *
42 from m5
.proxy
import *
43 from m5
.objects
.PciDevice
import PciDevice
, PciIoBar
, PciMemBar
45 ETHERNET_ROLE
= 'ETHERNET'
46 Port
.compat(ETHERNET_ROLE
, ETHERNET_ROLE
)
49 def __init__(self
, desc
):
50 super(EtherInt
, self
).__init
__(ETHERNET_ROLE
, desc
)
52 class VectorEtherInt(VectorPort
):
53 def __init__(self
, desc
):
54 super(VectorEtherInt
, self
).__init
__(ETHERNET_ROLE
, desc
)
56 class EtherLink(SimObject
):
58 cxx_header
= "dev/net/etherlink.hh"
59 int0
= EtherInt("interface 0")
60 int1
= EtherInt("interface 1")
61 delay
= Param
.Latency('0us', "packet transmit delay")
62 delay_var
= Param
.Latency('0ns', "packet transmit delay variability")
63 speed
= Param
.NetworkBandwidth('1Gbps', "link speed")
64 dump
= Param
.EtherDump(NULL
, "dump object")
66 class DistEtherLink(SimObject
):
67 type = 'DistEtherLink'
68 cxx_header
= "dev/net/dist_etherlink.hh"
69 int0
= EtherInt("interface 0")
70 delay
= Param
.Latency('0us', "packet transmit delay")
71 delay_var
= Param
.Latency('0ns', "packet transmit delay variability")
72 speed
= Param
.NetworkBandwidth('1Gbps', "link speed")
73 dump
= Param
.EtherDump(NULL
, "dump object")
74 dist_rank
= Param
.UInt32('0', "Rank of this gem5 process (dist run)")
75 dist_size
= Param
.UInt32('1', "Number of gem5 processes (dist run)")
76 sync_start
= Param
.Latency('5200000000000t', "first dist sync barrier")
77 sync_repeat
= Param
.Latency('10us', "dist sync barrier repeat")
78 server_name
= Param
.String('localhost', "Message server name")
79 server_port
= Param
.UInt32('2200', "Message server port")
80 is_switch
= Param
.Bool(False, "true if this a link in etherswitch")
81 dist_sync_on_pseudo_op
= Param
.Bool(False, "Start sync with pseudo_op")
82 num_nodes
= Param
.UInt32('2', "Number of simulate nodes")
84 class EtherBus(SimObject
):
86 cxx_header
= "dev/net/etherbus.hh"
87 loopback
= Param
.Bool(True, "send packet back to the sending interface")
88 dump
= Param
.EtherDump(NULL
, "dump object")
89 speed
= Param
.NetworkBandwidth('100Mbps', "bus speed in bits per second")
91 class EtherSwitch(SimObject
):
93 cxx_header
= "dev/net/etherswitch.hh"
94 dump
= Param
.EtherDump(NULL
, "dump object")
95 fabric_speed
= Param
.NetworkBandwidth('10Gbps', "switch fabric speed in "
97 interface
= VectorEtherInt("Ethernet Interface")
98 output_buffer_size
= Param
.MemorySize('1MiB',
99 "size of output port buffers")
100 delay
= Param
.Latency('0us', "packet transmit delay")
101 delay_var
= Param
.Latency('0ns', "packet transmit delay variability")
102 time_to_live
= Param
.Latency('10ms', "time to live of MAC address maping")
104 class EtherTapBase(SimObject
):
105 type = 'EtherTapBase'
107 cxx_header
= "dev/net/ethertap.hh"
108 bufsz
= Param
.Int(10000, "tap buffer size")
109 dump
= Param
.EtherDump(NULL
, "dump object")
110 tap
= EtherInt("Ethernet interface to connect to gem5's network")
112 if buildEnv
['USE_TUNTAP']:
113 class EtherTap(EtherTapBase
):
115 cxx_header
= "dev/net/ethertap.hh"
116 tun_clone_device
= Param
.String('/dev/net/tun',
117 "Path to the tun clone device node")
118 tap_device_name
= Param
.String('gem5-tap', "Tap device name")
120 class EtherTapStub(EtherTapBase
):
121 type = 'EtherTapStub'
122 cxx_header
= "dev/net/ethertap.hh"
123 port
= Param
.UInt16(3500, "Port helper should send packets to")
125 class EtherDump(SimObject
):
127 cxx_header
= "dev/net/etherdump.hh"
128 file = Param
.String("dump file")
129 maxlen
= Param
.Int(96, "max portion of packet data to dump")
131 class EtherDevice(PciDevice
):
134 cxx_header
= "dev/net/etherdevice.hh"
135 interface
= EtherInt("Ethernet Interface")
137 class IGbE(EtherDevice
):
138 # Base class for two IGbE adapters listed above
140 cxx_header
= "dev/net/i8254xGBe.hh"
141 hardware_address
= Param
.EthernetAddr(NextEthernetAddr
,
142 "Ethernet Hardware Address")
143 rx_fifo_size
= Param
.MemorySize('384KiB', "Size of the rx FIFO")
144 tx_fifo_size
= Param
.MemorySize('384KiB', "Size of the tx FIFO")
145 rx_desc_cache_size
= Param
.Int(64,
146 "Number of enteries in the rx descriptor cache")
147 tx_desc_cache_size
= Param
.Int(64,
148 "Number of enteries in the rx descriptor cache")
151 SubsystemVendorID
= 0x8086
156 BAR0
= PciMemBar(size
='128KiB')
157 MaximumLatency
= 0x00
161 wb_delay
= Param
.Latency('10ns', "delay before desc writeback occurs")
162 fetch_delay
= Param
.Latency('10ns', "delay before desc fetch occurs")
163 fetch_comp_delay
= Param
.Latency('10ns', "delay after desc fetch occurs")
164 wb_comp_delay
= Param
.Latency('10ns', "delay after desc wb occurs")
165 tx_read_delay
= Param
.Latency('0ns', "delay after tx dma read")
166 rx_write_delay
= Param
.Latency('0ns', "delay after rx dma read")
167 phy_pid
= Param
.UInt16("Phy PID that corresponds to device ID")
168 phy_epid
= Param
.UInt16("Phy EPID that corresponds to device ID")
170 class IGbE_e1000(IGbE
):
171 # Older Intel 8254x based gigabit ethernet adapter
172 # Uses Intel e1000 driver
177 class IGbE_igb(IGbE
):
178 # Newer Intel 8257x based gigabit ethernet adapter
179 # Uses Intel igb driver and in theory supports packet splitting and LRO
184 class EtherDevBase(EtherDevice
):
185 type = 'EtherDevBase'
187 cxx_header
= "dev/net/etherdevice.hh"
189 hardware_address
= Param
.EthernetAddr(NextEthernetAddr
,
190 "Ethernet Hardware Address")
192 dma_read_delay
= Param
.Latency('0us', "fixed delay for dma reads")
193 dma_read_factor
= Param
.Latency('0us', "multiplier for dma reads")
194 dma_write_delay
= Param
.Latency('0us', "fixed delay for dma writes")
195 dma_write_factor
= Param
.Latency('0us', "multiplier for dma writes")
197 rx_delay
= Param
.Latency('1us', "Receive Delay")
198 tx_delay
= Param
.Latency('1us', "Transmit Delay")
199 rx_fifo_size
= Param
.MemorySize('512KiB', "max size of rx fifo")
200 tx_fifo_size
= Param
.MemorySize('512KiB', "max size of tx fifo")
202 rx_filter
= Param
.Bool(True, "Enable Receive Filter")
203 intr_delay
= Param
.Latency('10us', "Interrupt propagation delay")
204 rx_thread
= Param
.Bool(False, "dedicated kernel thread for transmit")
205 tx_thread
= Param
.Bool(False, "dedicated kernel threads for receive")
206 rss
= Param
.Bool(False, "Receive Side Scaling")
208 class NSGigE(EtherDevBase
):
210 cxx_header
= "dev/net/ns_gige.hh"
212 dma_data_free
= Param
.Bool(False, "DMA of Data is free")
213 dma_desc_free
= Param
.Bool(False, "DMA of Descriptors is free")
214 dma_no_allocate
= Param
.Bool(True, "Should we allocate cache on read")
222 BARs
= (PciIoBar(size
='256B'), PciMemBar(size
='4KiB'))
223 MaximumLatency
= 0x34
230 class Sinic(EtherDevBase
):
232 cxx_class
= 'Sinic::Device'
233 cxx_header
= "dev/net/sinic.hh"
235 rx_max_copy
= Param
.MemorySize('1514B', "rx max copy")
236 tx_max_copy
= Param
.MemorySize('16KiB', "tx max copy")
237 rx_max_intr
= Param
.UInt32(10, "max rx packets per interrupt")
238 rx_fifo_threshold
= Param
.MemorySize('384KiB', "rx fifo high threshold")
239 rx_fifo_low_mark
= Param
.MemorySize('128KiB', "rx fifo low threshold")
240 tx_fifo_high_mark
= Param
.MemorySize('384KiB', "tx fifo high threshold")
241 tx_fifo_threshold
= Param
.MemorySize('128KiB', "tx fifo low threshold")
242 virtual_count
= Param
.UInt32(1, "Virtualized SINIC")
243 zero_copy_size
= Param
.UInt32(64, "Bytes to copy if below threshold")
244 zero_copy_threshold
= Param
.UInt32(256,
245 "Only zero copy above this threshold")
246 zero_copy
= Param
.Bool(False, "Zero copy receive")
247 delay_copy
= Param
.Bool(False, "Delayed copy transmit")
248 virtual_addr
= Param
.Bool(False, "Virtual addressing")
256 BARs
= PciMemBar(size
='64KiB')
257 MaximumLatency
= 0x34