1 # Copyright (c) 2015 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2005-2007 The Regents of The University of Michigan
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
22 # documentation and/or other materials provided with the distribution;
23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 # Authors: Nathan Binkert
41 from m5
.SimObject
import SimObject
42 from m5
.params
import *
43 from m5
.proxy
import *
44 from PciDevice
import PciDevice
46 class EtherObject(SimObject
):
49 cxx_header
= "dev/net/etherobject.hh"
51 class EtherLink(EtherObject
):
53 cxx_header
= "dev/net/etherlink.hh"
54 int0
= SlavePort("interface 0")
55 int1
= SlavePort("interface 1")
56 delay
= Param
.Latency('0us', "packet transmit delay")
57 delay_var
= Param
.Latency('0ns', "packet transmit delay variability")
58 speed
= Param
.NetworkBandwidth('1Gbps', "link speed")
59 dump
= Param
.EtherDump(NULL
, "dump object")
61 class MultiEtherLink(EtherObject
):
62 type = 'MultiEtherLink'
63 cxx_header
= "dev/net/multi_etherlink.hh"
64 int0
= SlavePort("interface 0")
65 delay
= Param
.Latency('0us', "packet transmit delay")
66 delay_var
= Param
.Latency('0ns', "packet transmit delay variability")
67 speed
= Param
.NetworkBandwidth('1Gbps', "link speed")
68 dump
= Param
.EtherDump(NULL
, "dump object")
69 multi_rank
= Param
.UInt32('0', "Rank of the this gem5 process (multi run)")
70 sync_start
= Param
.Latency('5200000000000t', "first multi sync barrier")
71 sync_repeat
= Param
.Latency('10us', "multi sync barrier repeat")
72 server_name
= Param
.String('localhost', "Message server name")
73 server_port
= Param
.UInt32('2200', "Message server port")
75 class EtherBus(EtherObject
):
77 cxx_header
= "dev/net/etherbus.hh"
78 loopback
= Param
.Bool(True, "send packet back to the sending interface")
79 dump
= Param
.EtherDump(NULL
, "dump object")
80 speed
= Param
.NetworkBandwidth('100Mbps', "bus speed in bits per second")
82 class EtherTap(EtherObject
):
84 cxx_header
= "dev/net/ethertap.hh"
85 bufsz
= Param
.Int(10000, "tap buffer size")
86 dump
= Param
.EtherDump(NULL
, "dump object")
87 port
= Param
.UInt16(3500, "tap port")
89 class EtherDump(SimObject
):
91 cxx_header
= "dev/net/etherdump.hh"
92 file = Param
.String("dump file")
93 maxlen
= Param
.Int(96, "max portion of packet data to dump")
95 class EtherDevice(PciDevice
):
98 cxx_header
= "dev/net/etherdevice.hh"
99 interface
= MasterPort("Ethernet Interface")
101 class IGbE(EtherDevice
):
102 # Base class for two IGbE adapters listed above
104 cxx_header
= "dev/net/i8254xGBe.hh"
105 hardware_address
= Param
.EthernetAddr(NextEthernetAddr
,
106 "Ethernet Hardware Address")
107 rx_fifo_size
= Param
.MemorySize('384kB', "Size of the rx FIFO")
108 tx_fifo_size
= Param
.MemorySize('384kB', "Size of the tx FIFO")
109 rx_desc_cache_size
= Param
.Int(64,
110 "Number of enteries in the rx descriptor cache")
111 tx_desc_cache_size
= Param
.Int(64,
112 "Number of enteries in the rx descriptor cache")
115 SubsystemVendorID
= 0x8086
126 MaximumLatency
= 0x00
131 wb_delay
= Param
.Latency('10ns', "delay before desc writeback occurs")
132 fetch_delay
= Param
.Latency('10ns', "delay before desc fetch occurs")
133 fetch_comp_delay
= Param
.Latency('10ns', "delay after desc fetch occurs")
134 wb_comp_delay
= Param
.Latency('10ns', "delay after desc wb occurs")
135 tx_read_delay
= Param
.Latency('0ns', "delay after tx dma read")
136 rx_write_delay
= Param
.Latency('0ns', "delay after rx dma read")
137 phy_pid
= Param
.UInt16("Phy PID that corresponds to device ID")
138 phy_epid
= Param
.UInt16("Phy EPID that corresponds to device ID")
140 class IGbE_e1000(IGbE
):
141 # Older Intel 8254x based gigabit ethernet adapter
142 # Uses Intel e1000 driver
147 class IGbE_igb(IGbE
):
148 # Newer Intel 8257x based gigabit ethernet adapter
149 # Uses Intel igb driver and in theory supports packet splitting and LRO
154 class EtherDevBase(EtherDevice
):
155 type = 'EtherDevBase'
157 cxx_header
= "dev/net/etherdevice.hh"
159 hardware_address
= Param
.EthernetAddr(NextEthernetAddr
,
160 "Ethernet Hardware Address")
162 dma_read_delay
= Param
.Latency('0us', "fixed delay for dma reads")
163 dma_read_factor
= Param
.Latency('0us', "multiplier for dma reads")
164 dma_write_delay
= Param
.Latency('0us', "fixed delay for dma writes")
165 dma_write_factor
= Param
.Latency('0us', "multiplier for dma writes")
167 rx_delay
= Param
.Latency('1us', "Receive Delay")
168 tx_delay
= Param
.Latency('1us', "Transmit Delay")
169 rx_fifo_size
= Param
.MemorySize('512kB', "max size of rx fifo")
170 tx_fifo_size
= Param
.MemorySize('512kB', "max size of tx fifo")
172 rx_filter
= Param
.Bool(True, "Enable Receive Filter")
173 intr_delay
= Param
.Latency('10us', "Interrupt propagation delay")
174 rx_thread
= Param
.Bool(False, "dedicated kernel thread for transmit")
175 tx_thread
= Param
.Bool(False, "dedicated kernel threads for receive")
176 rss
= Param
.Bool(False, "Receive Side Scaling")
178 class NSGigE(EtherDevBase
):
180 cxx_header
= "dev/net/ns_gige.hh"
182 dma_data_free
= Param
.Bool(False, "DMA of Data is free")
183 dma_desc_free
= Param
.Bool(False, "DMA of Descriptors is free")
184 dma_no_allocate
= Param
.Bool(True, "Should we allocate cache on read")
198 MaximumLatency
= 0x34
207 class Sinic(EtherDevBase
):
209 cxx_class
= 'Sinic::Device'
210 cxx_header
= "dev/net/sinic.hh"
212 rx_max_copy
= Param
.MemorySize('1514B', "rx max copy")
213 tx_max_copy
= Param
.MemorySize('16kB', "tx max copy")
214 rx_max_intr
= Param
.UInt32(10, "max rx packets per interrupt")
215 rx_fifo_threshold
= Param
.MemorySize('384kB', "rx fifo high threshold")
216 rx_fifo_low_mark
= Param
.MemorySize('128kB', "rx fifo low threshold")
217 tx_fifo_high_mark
= Param
.MemorySize('384kB', "tx fifo high threshold")
218 tx_fifo_threshold
= Param
.MemorySize('128kB', "tx fifo low threshold")
219 virtual_count
= Param
.UInt32(1, "Virtualized SINIC")
220 zero_copy_size
= Param
.UInt32(64, "Bytes to copy if below threshold")
221 zero_copy_threshold
= Param
.UInt32(256,
222 "Only zero copy above this threshold")
223 zero_copy
= Param
.Bool(False, "Zero copy receive")
224 delay_copy
= Param
.Bool(False, "Delayed copy transmit")
225 virtual_addr
= Param
.Bool(False, "Virtual addressing")
239 MaximumLatency
= 0x34